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2022-09-22ARM: 9243/1: riscpc: Unbreak the buildBart Van Assche1-0/+2
This patch fixes the following build error: In file included from ./include/linux/io.h:13, from ./arch/arm/mach-rpc/include/mach/uncompress.h:9, from arch/arm/boot/compressed/misc.c:31: ./arch/arm/include/asm/io.h:85:22: error: conflicting types for ‘__raw_writeb’ 85 | #define __raw_writeb __raw_writeb | ^~~~~~~~~~~~ ./arch/arm/include/asm/io.h:86:20: note: in expansion of macro ‘__raw_writeb’ 86 | static inline void __raw_writeb(u8 val, volatile void __iomem *addr) | ^~~~~~~~~~~~ In file included from arch/arm/boot/compressed/misc.c:26: arch/arm/boot/compressed/misc-ep93xx.h:13:20: note: previous definition of ‘__raw_writeb’ was here 13 | static inline void __raw_writeb(unsigned char value, unsigned int ptr) | ^~~~~~~~~~~~ To: Russell King <linux@armlinux.org.uk> Cc: Arnd Bergmann <arnd@arndb.de> Cc: linux-arm-kernel@lists.infradead.org Fixes: 0361c7e504b1 ("ARM: ep93xx: multiplatform support") Signed-off-by: Bart Van Assche <bvanassche@acm.org> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
2022-09-22ARM: decompressor: Include .data.rel.ro.localKees Cook1-0/+2
The .data.rel.ro.local section has the same semantics as .data.rel.ro here, so include it in the .rodata section of the decompressor. Additionally since the .printk_index section isn't usable outside of the core kernel, discard it in the decompressor. Avoids these warnings: arm-linux-gnueabi-ld: warning: orphan section `.data.rel.ro.local' from `arch/arm/boot/compressed/fdt_rw.o' being placed in section `.data.rel.ro.local' arm-linux-gnueabi-ld: warning: orphan section `.printk_index' from `arch/arm/boot/compressed/fdt_rw.o' being placed in section `.printk_index' Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/linux-mm/202209080545.qMIVj7YM-lkp@intel.com Cc: Russell King <linux@armlinux.org.uk> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Kees Cook <keescook@chromium.org>
2022-09-19ARM: dts: renesas: Fix USB PHY device and child node namesGeert Uytterhoeven8-25/+25
make dtbs_check: usb-phy@e6590100: '#phy-cells' is a required property From schema: dtschema/schemas/phy/phy-provider.yaml The R-Car Gen2 USB PHY device nodes do not represent USB PHYs theirselves, and thus do not have "#phy-cells" properties. Fix the warning by renaming them from "usb-phy" to "usb-phy-controller". Rename their child nodes from "usb-channel" to "usb-phy", as these do represent USB PHYs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/6442b4042e26537abc8632c4772f8201685f1f1f.1663165098.git.geert+renesas@glider.be
2022-09-17Merge tag 'at91-dt-6.1-2' of ↵Arnd Bergmann21-4/+413
https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/dt AT91 DT for v6.1 #2 It contains: - new SAMA5D3 based board, namely SAMA5D3-EDS - adjustments to pass the DT binding validations - disable AES on some LAN966 based boards as they are reserverd by secure OS * tag 'at91-dt-6.1-2' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: spi: dt-bindings: atmel,at91rm9200-spi: Add DMA related properties ARM: dts: at91: Add `atmel,usart-mode` required property to serial nodes ARM: dts: at91: sam9x60ek: Add DBGU compatibles to uart1 ARM: dts: at91: sama7g5: Swap rx and tx for spi11 dts: arm: at91: Add SAMA5D3-EDS Board dt-bindings: arm: at91: Add info on SAMA5D3-EDS ARM: dts: lan966x: disable aes Link: https://lore.kernel.org/r/20220916105407.1287452-1-claudiu.beznea@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-17ARM: dts: imx6qdl-gw54xx: add CAN regulatorTim Harvey1-1/+17
The GW54xx has a transceiver with a STBY pin connected to an IMX6 GPIO. Configure this as a regulator to drive it low when CAN is in use. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17ARM: dts: imx6qdl-gw53xx: add CAN regulatorTim Harvey1-1/+17
The GW53xx has a transceiver with a STBY pin connected to an IMX6 GPIO. Configure this as a regulator to drive it low when CAN is in use. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-17ARM: dts: imx6qdl-gw52xx: add CAN regulatorTim Harvey1-1/+17
The GW52xx has a transceiver with a STBY pin connected to an IMX6 GPIO. Configure this as a regulator to drive it low when CAN is in use. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-16ARM: dts: at91: Add `atmel,usart-mode` required property to serial nodesSergiu Moga16-0/+89
Add the missing required DT property `atmel,usart-mode` to the serial nodes of Atmel/Microchip DT files. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220913142205.162399-4-sergiu.moga@microchip.com
2022-09-16ARM: dts: at91: sam9x60ek: Add DBGU compatibles to uart1Sergiu Moga1-1/+1
Maintain consistency among the compatibles of the serial nodes of sam9x60ek and highlight the incremental characteristic of its serial IP's by making sure that all serial nodes contain both the sam9x60 and sam9260 usart/dbgu compatibles. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220913142205.162399-3-sergiu.moga@microchip.com
2022-09-16ARM: dts: at91: sama7g5: Swap rx and tx for spi11Sergiu Moga1-3/+3
Swap the rx and tx of the DMA related DT properties of the spi11 node in order to maintain consistency across Microchip/Atmel SoC files. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220913142205.162399-2-sergiu.moga@microchip.com
2022-09-15Merge tag 'arm-soc/for-6.1/devicetree' of ↵Arnd Bergmann1-0/+12
https://github.com/Broadcom/stblinux into arm/dt This pull request contains Broadcom ARM-based SoC Device Tree updates for 6.1, please pull the following: - Rafal improves the BCM5301X PCIe DT nodes schema validation by flagging the PCIe controller with a missing "device_type" property - William merges BCM4908 within BCMBCA since this chip is part of the Broadcom Broadband Carrier Access group and follows the architecture of those chips * tag 'arm-soc/for-6.1/devicetree' of https://github.com/Broadcom/stblinux: arm64: bcmbca: Merge ARCH_BCM4908 to ARCH_BCMBCA arm64: dts: Add BCM4908 generic board dts arm64: dts: Move BCM4908 dts to bcmbca folder arm64: dts: bcmbca: update BCM4908 board dts files dt-bindings: arm64: bcmbca: Update BCM4908 description dt-bindings: arm64: bcmbca: Merge BCM4908 into BCMBCA ARM: dts: BCM5301X: Add basic PCI controller properties Link: https://lore.kernel.org/r/20220915023044.2350782-2-f.fainelli@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-15Merge tag 'at91-fixes-6.0-2' of ↵Arnd Bergmann1-2/+2
https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/fixes AT91 fixes for 6.0 #2 It contains a fix for LAN966 SoCs that corrects the interrupt number for internal PHYs. * tag 'at91-fixes-6.0-2' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: dts: lan966x: Fix the interrupt number for internal PHYs Link: https://lore.kernel.org/r/20220915105833.4159850-1-claudiu.beznea@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-15ARM: dts: qcom: apq8026-lg-lenok: Enable ADSPLuca Weiss1-0/+13
Configure the reserved memory for ADSP and enable it. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220423155059.660387-5-luca@z3ntu.xyz
2022-09-15ARM: dts: qcom: apq8026-asus-sparrow: Enable ADSPLuca Weiss1-0/+4
The customized reserved memory for ADSP is already configured, so we just need to enable the node. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220423155059.660387-4-luca@z3ntu.xyz
2022-09-15ARM: dts: qcom: msm8226: Add ADSP nodeLuca Weiss2-0/+67
Add a node for the adsp found on msm8226. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220423155059.660387-3-luca@z3ntu.xyz
2022-09-15ARM: dts: aspeed: elbert: Enable mac3 controllerTao Ren1-0/+18
Enable mac3 controller in Elbert dts: Elbert MAC3 is connected to the BCM53134P onboard switch's IMP_RGMII port directly (fixed link, no PHY between BMC MAC and BCM53134P). Note: BMC's mdio0 controller is connected to BCM53134P's MDIO interface, and the MDIO channel will be enabled later, when BCM53134 is added to "bcm53xx" DSA driver. Signed-off-by: Tao Ren <rentao.bupt@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2022-09-14dts: arm: at91: Add SAMA5D3-EDS BoardJerry Ray2-0/+308
The SAMA5D3-EDS board is an Ethernet Development Platform allowing for evaluating many Microchip ethernet switch and PHY products. Various daughter cards can connect via an RGMII connector or an RMII connector. The EDS board is not intended for stand-alone use and has no ethernet capabilities when no daughter board is connected. As such, this device tree is intended to be used with a DT overlay defining the add-on board. To better ensure consistency, some items are defined here as a form of documentation so that all add-on overlays will use the same terms. Link: https://www.microchip.com/en-us/development-tool/SAMA5D3-ETHERNET-DEVELOPMENT-SYSTEM Signed-off-by: Jerry Ray <jerry.ray@microchip.com> [claudiu.beznea: s/gpio-inputs/gpio-keys in at91-sama5d3_eds.dts] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220909163022.13022-2-jerry.ray@microchip.com
2022-09-14ARM: dts: lan966x: disable aesHoratiu Vultur3-0/+12
Disable AES node on lan966x pcb8290, pcb891 and pcb8309 because these boards have lan966x that uses secure OS which reserves the AES block. Therefore it can't be exposed to non-secure world. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220908070451.3730608-1-horatiu.vultur@microchip.com
2022-09-14ARM: dts: qcom: ipq8064: pad addresses to 8 digitChristian Marangi1-3/+3
Pad reg addresses to 8 digit to make sorting easier. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220718153815.29414-2-ansuelsmth@gmail.com
2022-09-14ARM: dts: qcom: ipq8064: reorganize node order and sort themChristian Marangi1-381/+380
Reorganize node order and sort them by address. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220718153815.29414-1-ansuelsmth@gmail.com
2022-09-14ARM: dts: qcom: align SDHCI clocks with DT schemaKrzysztof Kozlowski5-29/+29
The DT schema expects clocks iface-core order. No functional change. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220712144245.17417-6-krzysztof.kozlowski@linaro.org
2022-09-14ARM: dts: qcom: align SDHCI reg-names with DT schemaKrzysztof Kozlowski5-9/+10
DT schema requires SDHCI reg names to be hc/core without "_mem" suffix, just like TXT bindings were expecting before the conversion. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220712144245.17417-5-krzysztof.kozlowski@linaro.org
2022-09-14ARM: dts: qcom: msm8960: add clocks to the MMCC device nodeDmitry Baryshkov1-0/+16
As we are converting this platform to use DT clock bindings, add clocks and clock-names properties to the MMCC device tree node. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: David Heidelberg <david@ixit.cz> # tested on Nexus 7 (2013) Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220623120418.250589-16-dmitry.baryshkov@linaro.org
2022-09-14ARM: dts: qcom: apq8064: add clocks to the MMCC device nodeDmitry Baryshkov1-0/+16
As we are converting this platform to use DT clock bindings, add clocks and clock-names properties to the MMCC device tree node. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: David Heidelberg <david@ixit.cz> # tested on Nexus 7 (2013) Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220623120418.250589-15-dmitry.baryshkov@linaro.org
2022-09-14ARM: dts: qcom: msm8960: add clocks to the GCC device nodeDmitry Baryshkov1-1/+6
As we are converting this platform to use DT clock bindings, add clocks and clock-names properties to the GCC device tree node. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: David Heidelberg <david@ixit.cz> # tested on Nexus 7 (2013) Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220623120418.250589-14-dmitry.baryshkov@linaro.org
2022-09-14ARM: dts: qcom: apq8064: add clocks to the GCC device nodeDmitry Baryshkov1-0/+5
As we are converting this platform to use DT clock bindings, add clocks and clock-names properties to the GCC device tree node. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: David Heidelberg <david@ixit.cz> # tested on Nexus 7 (2013) Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220623120418.250589-13-dmitry.baryshkov@linaro.org
2022-09-14ARM: dts: qcom: msm8960: add clocks to the LCC device nodeDmitry Baryshkov1-1/+15
As we are converting this platform to use DT clock bindings, add clocks and clock-names properties to the LCC device tree node. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: David Heidelberg <david@ixit.cz> # tested on Nexus 7 (2013) Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220623120418.250589-12-dmitry.baryshkov@linaro.org
2022-09-14ARM: dts: qcom: apq8064: add clocks to the LCC device nodeDmitry Baryshkov1-0/+14
As we are converting this platform to use DT clock bindings, add clocks and clock-names properties to the LCC device tree node. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: David Heidelberg <david@ixit.cz> # tested on Nexus 7 (2013) Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220623120418.250589-11-dmitry.baryshkov@linaro.org
2022-09-14ARM: dts: qcom: msm8226: switch TCSR mutex to MMIOKrzysztof Kozlowski1-10/+4
The TCSR mutex bindings allow device to be described only with address space (so it uses MMIO, not syscon regmap). This seems reasonable as TCSR mutex is actually a dedicated IO address space and it also fixes DT schema checks: qcom-msm8226-samsung-s3ve3g.dtb: hwlock: 'reg' is a required property qcom-msm8226-samsung-s3ve3g.dtb: hwlock: 'syscon' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220909092035.223915-16-krzysztof.kozlowski@linaro.org
2022-09-14ARM: dts: qcom: apq8084: switch TCSR mutex to MMIOKrzysztof Kozlowski1-8/+3
The TCSR mutex bindings allow device to be described only with address space (so it uses MMIO, not syscon regmap). This seems reasonable as TCSR mutex is actually a dedicated IO address space and it also fixes DT schema checks: qcom-apq8084-mtp.dtb: hwlock: 'reg' is a required property qcom-apq8084-mtp.dtb: hwlock: 'syscon' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220909092035.223915-15-krzysztof.kozlowski@linaro.org
2022-09-14ARM: dts: qcom: msm8660: fix node names for fixed clocksDmitry Baryshkov1-3/+6
Fix node names for three fixed clocks to follow the no-underscores-in-name rule. To remain compatible with the drivers expecting to find the old clock names, add clock-output-names properties. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220909105136.3733919-6-dmitry.baryshkov@linaro.org
2022-09-14ARM: dts: qcom: msm8660: add pxo/cxo clocks to the GCC nodeDmitry Baryshkov1-1/+3
Add pxo/cxo clocks to the GCC device tree node. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220909105136.3733919-5-dmitry.baryshkov@linaro.org
2022-09-13ARM: dts: qcom: apq8060-dragonboard: Add TMA340 to APQ8060 DragonBoardLinus Walleij1-1/+70
This adds the CY8CTMA340 Touchscreen to the APQ8060 DragonBoard. Tested without display by issuing cat /dev/input/input/event3 which produces appropriate noise and interrupts on the dedicated GPIO line. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220913132846.305716-3-linus.walleij@linaro.org
2022-09-13ARM: dts: qcom: msm8660: Add GSBI3 I2C busLinus Walleij1-0/+25
GSBI3 can be used to enable an external I2C bus on e.g. the APQ8060. On the DragonBoard APQ8060 this I2C bus is used to talk to the Cypress CY8CTMA340 CYTTSP touchscreen. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220913132846.305716-2-linus.walleij@linaro.org
2022-09-13ARM: dts: qcom: msm8660: Add GSBI1 SPI busLinus Walleij1-0/+26
GSBI1 can be used to enable an external SPI bus on e.g. the APQ8060. On the DragonBoard APQ8060 this SPI bus is used to talk to the LCD display. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> [bjorn: Moved status properties last] Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220913132846.305716-1-linus.walleij@linaro.org
2022-09-13ARM: dts: lan966x: Fix the interrupt number for internal PHYsHoratiu Vultur1-2/+2
According to the datasheet the interrupts for internal PHYs are 80 and 81. Fixes: 6ad69e07def67c ("ARM: dts: lan966x: add MIIM nodes") Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220912192629.461452-1-horatiu.vultur@microchip.com
2022-09-12Merge tag 'stm32-dt-for-v6.1-1' of ↵Arnd Bergmann14-32/+334
git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt STM32 DT for v6.1, round 1 Highlights: ---------- - MPU: - General: - Add I2C support (5 instances) on STM32MP13. - Add SPI support (5 instabces) on STM32MP13. - Add timer interrupts support on STM32MP15. - ST boards: - Enable I2C1 and I2C5 on stm32mp135f-dk board. - Add SPI5 on stm32mp135f-dk board but disabled as only available on the GPIO expansion connector. - ARGON: - Remove spidev node as not used by the code. * tag 'stm32-dt-for-v6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: ARM: dts: stm32: argon: remove spidev node ARM: dts: stm32: Create separate pinmux for qspi cs pin in stm32mp15-pinctrl.dtsi ARM: dts: stm32: Fix typo in license text for Engicam boards ARM: dts: stm32: Add timer interrupts on stm32mp15 ARM: dts: stm32: add pinctrl and disabled spi5 node in stm32mp135f-dk ARM: dts: stm32: add spi nodes into stm32mp131.dtsi ARM: dts: stm32: enable i2c1 and i2c5 on stm32mp135f-dk.dts ARM: dts: stm32: add i2c nodes into stm32mp131.dtsi Link: https://lore.kernel.org/r/d80afc20-2745-24a2-ab70-a5a03439bd50@foss.st.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-12Merge tag 'v6.1-rockchip-dts32-1' of ↵Arnd Bergmann7-37/+52
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt Adapt emac nodes to make them conform to the newly yaml-converted binding. * tag 'v6.1-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: restyle emac nodes ARM: dts: rockchip: fix rk3036 emac node compatible string Link: https://lore.kernel.org/r/4766760.31r3eYUQgx@phil Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-12ARM: dts: stm32: argon: remove spidev nodeWolfram Sang1-6/+0
Commit 956b200a846e ("spi: spidev: Warn loudly if instantiated from DT as "spidev"") states that there should not be spidev nodes in DTs. Remove this non-HW description. There won't be a regression because it won't bind since 2015 anyhow. Fixes: 16e3e44c5b87 ("ARM: dts: stm32: Add support for the emtrion emSBC-Argon") Cc: Reinhold Mueller <reinhold.mueller@emtrion.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-09-12ARM: dts: stm32: Create separate pinmux for qspi cs pin in ↵Patrice Chotard2-19/+43
stm32mp15-pinctrl.dtsi Create a separate pinmux for qspi chip select in stm32mp15-pinctrl.dtsi. In the case we want to use transfer_one() API to communicate with a SPI device, chip select signal must be driven individually. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-09-12ARM: dts: stm32: Fix typo in license text for Engicam boardsJagan Teki7-7/+7
Fix the Amarula Solutions typo mistake in license text added in below commits. commit <3ff0810ffc479> ("ARM: dts: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF") commit <6ca2898df59f7> ("ARM: dts: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0") commit <adc0496104b64> ("ARM: dts: stm32: Add Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit") commit <30f9a9da4ee13> ("ARM: dts: stm32: Add Engicam i.Core STM32MP1 SoM") commit <1d278204cbaa1> ("ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OF") commit <f838dae7afd00> ("ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 board") commit <0be81dfaeaf89> ("ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 SoM") Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-09-12ARM: dts: stm32: Add timer interrupts on stm32mp15Uwe Kleine-König1-0/+34
The timer units in the stm32mp15x CPUs have interrupts, depending on the timer flavour either one "global" or four dedicated ones. Add the irqs to the timer units on stm32mp15x. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-09-12ARM: dts: stm32: add pinctrl and disabled spi5 node in stm32mp135f-dkAlain Volmat2-0/+30
Add pinctrl information and a disabled spi5 node within stm32mp135f-dk.dts in order to use the spi5 bus which is available via the GPIO expansion pins of the STM32MP135 Discovery board. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-09-12ARM: dts: stm32: add spi nodes into stm32mp131.dtsiAlain Volmat1-0/+70
Add the 5 instances of spi busses supported by the stm32mp131. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-09-12ARM: dts: stm32: enable i2c1 and i2c5 on stm32mp135f-dk.dtsAlain Volmat2-0/+60
Enable the two i2c busses i2c1 and i2c5 available on the stm32mp135f-dk Discovery board. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-09-12ARM: dts: stm32: add i2c nodes into stm32mp131.dtsiAlain Volmat1-0/+90
Add the 5 instances of i2c busses supported by the stm32mp131. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2022-09-12ARM: dts: imx: update sdma node name formatJoy Zou11-11/+11
Node names should be generic, so change the sdma node name format 'sdma' into 'dma-controller'. Acked-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Joy Zou <joy.zou@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-09-10ARM: dts: rockchip: restyle emac nodesJohan Jonker7-36/+51
The emac_rockchip.txt file is converted to YAML. Phy nodes are now a subnode of mdio, so restyle the emac nodes of rk3036/rk3066/rk3188. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20220603163539.537-3-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-09-10ARM: dts: rockchip: fix rk3036 emac node compatible stringJohan Jonker1-1/+1
The Linux kernel has no logic to decide which driver to probe first. To prevent race conditions remove the rk3036 emac node fall back compatible string. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20220603163539.537-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-09-09ARM: dts: r9a06g032-rzn1d400-db: Enable CAN1Biju Das1-0/+28
The CN10/CN11 on RZ/N1-EB board are headers to add jumpers to select which CAN interface to route to the real CAN connector J16. For a normal use case either we need to wire CAN1 or CAN2, but not both. This patch enables CAN1 and disables CAN2 by default assuming CN10/CN11 is wired for CAN1. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220902062752.56841-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-28 06:41:02 +0300