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2019-04-23ARM: 8857/1: efi: enable CP15 DMB instructions before cleaning the cacheArd Biesheuvel1-1/+15
The EFI stub is entered with the caches and MMU enabled by the firmware, and once the stub is ready to hand over to the decompressor, we clean and disable the caches. The cache clean routines use CP15 barrier instructions, which can be disabled via SCTLR. Normally, when using the provided cache handling routines to enable the caches and MMU, this bit is enabled as well. However, but since we entered the stub with the caches already enabled, this routine is not executed before we call the cache clean routines, resulting in undefined instruction exceptions if the firmware never enabled this bit. So set the bit explicitly in the EFI entry code, but do so in a way that guarantees that the resulting code can still run on v6 cores as well (which are guaranteed to have CP15 barriers enabled) Cc: <stable@vger.kernel.org> # v4.9+ Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2019-04-23ARM: dts: Add queue manager and NPE to the IXP4xx DTSILinus Walleij1-0/+11
The AHB queue manager and Network Processing Engines are present on all IXP4xx SoCs, so we add them to the overarching device tree include. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23ARM: dts: Add some initial IXP4xx device treesLinus Walleij7-0/+338
This adds a device tree for the IXP4xx-based Linksys NSLU2 and Gateworks GW2358 which encompass the Gateworks Cambria family. These will be the first IXP4xx device tree platforms. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-23ARM: dts: imx7s: Specify #io-channel-cells in ADC nodesAndrey Smirnov1-0/+2
Specify #io-channel-cells in ADC nodes. Needed to be able to reference them by phandle. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Chris Healy <cphealy@gmail.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Fabio Estevam <festevam@gmail.com> Cc: Rob Herring <robh@kernel.org> Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-22ARM: dts: vf610-zii-dev-rev-b: Specify CS as GPIO_ACTIVE_LOW in spi0Andrey Smirnov1-1/+1
Specify CS as GPIO_ACTIVE_LOW in spi0 to fix the following warning: m25p128@0 enforce active low on chipselect handle Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Chris Healy <cphealy@gmail.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Fabio Estevam <festevam@gmail.com> Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-22ARM: dts: vf610-zii-dev: Mark i2c0 SCL as GPIO_OPEN_DRAINAndrey Smirnov1-1/+1
Mark i2c0 SCL as GPIO_OPEN_DRAIN to fix the following warning: gpio-36 (scl): enforced open drain please flag it properly in DT/ACPI DSDT/board file Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Chris Healy <cphealy@gmail.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Fabio Estevam <festevam@gmail.com> Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-22ARM: dts: Add support for ZII i.MX7 RPU2 boardAndrey Smirnov2-0/+942
Add support for ZII's i.MX7 based Remote Peripheral Unit 2 (RPU2) board. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Chris Healy <cphealy@gmail.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Fabio Estevam <festevam@gmail.com> Cc: Rob Herring <robh@kernel.org> Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-22ARM: dts: bugfix tqma7 soft reset issueBruno Thomsen2-11/+17
Running reboot command on the TQMa7 board would just hang infinite at the end of the system shutdown process. Handling of i.MX7 errata e10574: Watchdog: A watchdog timeout or software trigger will not reset the SOC. Moved pinctrl from common mba7 to common tqma7 dtsi as it improves readability of errata handling. Most integrators of this SoM will likely use the development board as inspiration for handling this SoC issue. Signed-off-by: Bruno Thomsen <bruno.thomsen@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-21ARM: dts: armada-38x: add interrupts for watchdogChris Packham1-0/+2
The first interrupt is for the regular watchdog timeout. Normally the RSTOUT line will trigger a reset before this interrupt fires but on systems with a non-standard reset it may still trigger. The second interrupt is for a timer1 which is used as a pre-timeout for the watchdog. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2019-04-21ARM: dts: imx53: Add Menlosystems M53 boardMarek Vasut2-0/+312
Add device tree for the Menlosystems board based on i.MX53 M53 SoM. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-21ARM: dts: imx53: Rename M53 SoM touchscreen nodeMarek Vasut1-1/+1
Rename the touchscreen node to match contemporary design. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: NXP Linux Team <linux-imx@nxp.com> To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-21ARM: dts: ls1021: Fix SGMII PCS link remaining down after PHY disconnectVladimir Oltean2-2/+18
Each eTSEC MAC has its own TBI (SGMII) PCS and private MDIO bus. But due to a DTS oversight, both SGMII-compatible MACs of the LS1021 SoC are pointing towards the same internal PCS. Therefore nobody is controlling the internal PCS of eTSEC0. Upon initial ndo_open, the SGMII link is ok by virtue of U-boot initialization. But upon an ifdown/ifup sequence, the code path from ndo_open -> init_phy -> gfar_configure_serdes does not get executed for the PCS of eTSEC0 (and is executed twice for MAC eTSEC1). So the SGMII link remains down for eTSEC0. On the LS1021A-TWR board, to signal this failure condition, the PHY driver keeps printing '803x_aneg_done: SGMII link is not ok'. Also, it changes compatible of mdio0 to "fsl,etsec2-mdio" to match mdio1 device. Fixes: 055223d4d22d ("ARM: dts: ls1021a: Enable the eTSEC ports on QDS and TWR") Signed-off-by: Vladimir Oltean <olteanv@gmail.com> Reviewed-by: Claudiu Manoil <claudiu.manoil@nxp.com> Acked-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-04-19ARM: dts: lpc32xx: use SPDX license identifierVladimir Zapolskiy1-7/+1
Replace GPLv2+ header with the SPDX identifier. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-19ARM: dts: lpc32xx: add address and size cell values to SPI controller nodesVladimir Zapolskiy2-2/+8
All 4 SPI controllers on NXP LPC32xx SoC support SPI slaves discerning them by one cell address value, set it as default to avoid duplication in board device tree files. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-19ARM: dts: lpc32xx: disable MAC controller by defaultVladimir Zapolskiy3-0/+3
NXP LPC3220 and LPC3230 SoCs do NOT contain a MAC controller, so, since for now there is just one dtsi file for all variants of NXP LPC32xx SoCs, it is reasonable to disable the controller by default and enable it in device tree files of particular boards. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-19ARM: dts: lpc32xx: disable I2S controllers by defaultVladimir Zapolskiy1-0/+2
The I2S controllers found on NXP LPC32xx SoCs are not yet in use by any boards supported in upstream, disable the controllers by default. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-19ARM: dts: lpc32xx: change hexadecimal values to lower caseVladimir Zapolskiy1-9/+10
This is a non-functional change, all inconsistent hexadecimal values found in the file are now fixed. Taking a chance to interfere into some non-functional change I add my copyright notice for work done during the last few years. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-18ARM: dts: sun8i: a83t: Enable USB OTG controller on some boardsChen-Yu Tsai2-0/+24
The Bananapi M3 and Cubietruck Plus both have USB OTG ports wired to the SoC and PMIC in the same way, with the N_VBUSEN pin on the PMIC controlling VBUS output, the PMIC's VBUS input for sensing VBUS, and PH11 on the SoC for sensing the ID pin. Enable OTG on both boards. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-18ARM: dtsi: axp81x: add USB power supply nodeQuentin Schulz1-0/+4
The AXP813/818 has a VBUS power input. Add a device node for it, now that we support it. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com> [wens@csie.org: Add commit message] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-18ARM: tegra: Add ACTMON support on Tegra30Dmitry Osipenko1-0/+11
Add support for ACTMON on Tegra30. This is used to monitor activity from different components. Based on the collected statistics, the rate at which the external memory needs to be clocked can be derived. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-18ARM: dts: Ux500: Add MCDE and Samsung displayLinus Walleij3-11/+65
This adds and updates the device tree nodes for the MCDE display controller and connects the Samsung display to the TVK1281618 user interface board (UIB) so we get nicely working graphics on this reference design. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-18ARM: dts: ux500: Add Mali-400Linus Walleij1-0/+24
This adds the Mali-400 block, also known as SGA500 or the Smart Graphics Adapter, to the DBx500 DTS file. All resources and bindings are already in place so this just works. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-04-17ARM: dts: ape6evm: Reorder bootargsMagnus Damm1-1/+1
Reorder bootargs parameters to make the APE6EVM board bootargs match other boards from Renesas. No need to be special. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-17ARM: dts: marzen: Add rw to bootargs and use ip=dhcpMagnus Damm1-1/+1
Add rw as bootargs parameter and change from ip=on to ip=dhcp to make the Marzen board bootargs match other boards from Renesas. No need to be special. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-17ARM: dts: bockw: Reorder bootargsMagnus Damm1-1/+1
Reorder bootargs parameters to make the BockW board bootargs match other boards from Renesas. No need to be special. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-17ARM: dts: kzm9d: Add rw parameter to bootargsMagnus Damm1-1/+1
Add rw as bootargs parameter to make the KZM9D board bootargs match other boards from Renesas. No need to be special. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-17ARM: dts: sun8i: mapleboard: Remove cd-invertedMaxime Ripard1-2/+1
The cd-inverted property can also be expressed using the GPIO flags. Use the active low GPIO flag to have the same semantic without the confusion. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-17ARM: dts: sun5i: Reorder pinctrl nodesMaxime Ripard1-10/+10
We try to keep the PIO nodes ordered alphabetically, but this doesn't always work out. Let's fix it. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-17ARM: dts: sun6i: i7: Remove useless propertyMaxime Ripard1-1/+0
The I7 DTS uses an spdif-out property with an "okay" value. However, that property isn't documented anywhere, and isn't used anywhere either. Remove it. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-17ARM: dts: sun4i: lime: Fix the USB PHY ID detect GPIO propertiesMaxime Ripard1-1/+1
While the USB PHY Device Tree mandates that the name of the ID detect pin should be usb0_id_det-gpios, a significant number of device tree use usb0_id_det-gpio instead. This was functional because the GPIO framework falls back to the gpio suffix that is legacy, but we should fix this. Commit 2c515b0d05a9 ("ARM: sunxi: Fix the USB PHY ID detect GPIO properties") was supposed to fix this, but one fell through the cracks. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-17ARM: dts: sun4i: protab2: Remove stale pinctrl-names entryMaxime Ripard1-1/+0
Some nodes still have pinctrl-names entry, yet they don't have any pinctrl group anymore. Drop them. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-17ARM: tegra: venice2: Move PLL power supplies to XUSB pad controllerThierry Reding1-0/+5
The XUSB pad controller is responsible for supplying power to the PLLs used to drive the various USB, PCI and SATA pads. Move the PLL power supplies from the PCIe and XUSB controllers to the XUSB pad controller to make sure they are available when needed. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-17ARM: tegra: nyan: Move PLL power supplies to XUSB pad controllerThierry Reding1-0/+5
The XUSB pad controller is responsible for supplying power to the PLLs used to drive the various USB, PCI and SATA pads. Move the PLL power supplies from the XUSB controller to the XUSB pad controller to make sure they are available when needed. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-17ARM: tegra: jetson-tk1: Move PLL power supplies to XUSB pad controllerThierry Reding1-0/+5
The XUSB pad controller is responsible for supplying power to the PLLs used to drive the various USB, PCI and SATA pads. Move the PLL power supplies from the PCIe and XUSB controllers to the XUSB pad controller to make sure they are available when needed. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-17ARM: tegra: apalis: Move PLL power supplies to XUSB pad controllerThierry Reding2-0/+12
The XUSB pad controller is responsible for supplying power to the PLLs used to drive the various USB, PCI and SATA pads. Move the PLL power supplies from the PCIe and XUSB controllers to the XUSB pad controller to make sure they are available when needed. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-17ARM: tegra: Remove gratuitous parentheses in SPDX license identifierThierry Reding2-2/+2
Parentheses in the SPDX license identifier are only used to group sub- expressions. If there's no need for such grouping, the parentheses can be omitted. Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-17ARM: tegra: Convert to SPDX license tags for Tegra124 ApalisIgor Opaniuk3-113/+6
Replace boiler plate licenses texts with the SPDX license identifiers in Colibri/Apalis DTS files. Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> [treding@nvidia.com: drop unneeded parentheses, keep license at X11] Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-17ARM: dts: sunxi: h3/h5: Remove useless phy-names from EHCI and OHCIMaxime Ripard1-6/+0
Neither the OHCI or EHCI bindings are using the phy-names property, so we can just drop it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-17ARM: dts: sunxi: Remove useless phy-names from EHCI and OHCIMaxime Ripard8-28/+0
Neither the OHCI or EHCI bindings are using the phy-names property, so we can just drop it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-16ARM: dts: meson8b: odroid-c1: prepare support for the RTCMartin Blumenstingl1-0/+14
The Odroid-C1 has the 32.768 kHz oscillator (X3 in the schematics) which is required for the RTC. A battery can be connected separately (to the BT1 header) - then the "rtc" node can be enabled manually. By default the RTC is disabled because the boards typically come without the RTC battery. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-04-16ARM: dts: meson8b: ec100: enable the RTCMartin Blumenstingl1-0/+14
The RTC is always enabled on this board since the battery is already connected in the factory. According to the schematics the VCC_RTC regulator (which is either powered by the internal 3.3V or a battery) is connected to the 0.9V RTC_VDD input of the SoCs. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-04-16ARM: dts: meson: add support for the RTCMartin Blumenstingl3-0/+19
The 32-bit Meson SoCs have an RTC block in the AO (always on) area. The RTC requires an external 32.768 kHz oscillator to work properly. Whether or not this crystal exists depends on the board, so it has to be added for each board.dts (instead of adding it somewhere in a generic .dtsi). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-04-15ARM: dts: am335x: wega: Replaced register offsets with definesChristina Quast1-34/+34
The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast <cquast@hanoverdisplays.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-15ARM: dts: am335x: sl50: Replaced register offsets with definesChristina Quast1-104/+104
The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast <cquast@hanoverdisplays.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-15ARM: dts: am335x: shc: Replaced register offsets with definesChristina Quast1-114/+112
The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast <cquast@hanoverdisplays.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-15ARM: dts: am335x: sbc-t335: Replaced register offsets with definesChristina Quast1-96/+56
The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast <cquast@hanoverdisplays.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-15ARM: dts: am335x: sancloud-bbe: Replaced register offsets with definesChristina Quast1-31/+31
The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast <cquast@hanoverdisplays.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-15ARM: dts: am335x: phycore-som: Replaced register offsets with definesChristina Quast1-30/+30
The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast <cquast@hanoverdisplays.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-15ARM: dts: am335x: pepper: Replaced register offsets with definesChristina Quast1-100/+100
The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast <cquast@hanoverdisplays.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-04-15ARM: dts: am335x: pdu001: Replaced register offsets with definesChristina Quast1-85/+85
The defines are taken from dt-bindings/pinctrl/am33xx.h Signed-off-by: Christina Quast <cquast@hanoverdisplays.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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