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2020-07-14ARM: OMAP2+: Drop legacy platform data for omap5 dwc3Tony Lindgren1-1/+0
We can now probe devices with ti-sysc interconnect driver and dts data. Let's drop the related platform data and custom ti,hwmods dts property. As we're just dropping data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-07-14ARM: dts: Fix dcan driver probe failed on am437x platformdillon min1-4/+10
Got following d_can probe errors with kernel 5.8-rc1 on am437x [ 10.730822] CAN device driver interface Starting Wait for Network to be Configured... [ OK ] Reached target Network. [ 10.787363] c_can_platform 481cc000.can: probe failed [ 10.792484] c_can_platform: probe of 481cc000.can failed with error -2 [ 10.799457] c_can_platform 481d0000.can: probe failed [ 10.804617] c_can_platform: probe of 481d0000.can failed with error -2 actually, Tony has fixed this issue on am335x with the patch [3] Since am437x has the same clock structure with am335x [1][2], so reuse the code from Tony Lindgren's patch [3] to fix it. [1]: https://www.ti.com/lit/pdf/spruh73 Chapter-23, Figure 23-1. DCAN Integration [2]: https://www.ti.com/lit/pdf/spruhl7 Chapter-25, Figure 25-1. DCAN Integration [3]: commit 516f1117d0fb ("ARM: dts: Configure osc clock for d_can on am335x") Fixes: 1a5cd7c23cc5 ("bus: ti-sysc: Enable all clocks directly during init to read revision") Signed-off-by: dillon min <dillon.minfei@gmail.com> [tony@atomide.com: aligned commit message a bit for readability] Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-07-14Merge branch 'for-linus' of ↵Linus Torvalds1-4/+8
git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input Pull input fixes from Dmitry Torokhov: "A few quirks for the Elan touchpad driver, another Thinkpad is being switched over from PS/2 to native RMI4 interface, and we gave a brand new SW_MACHINE_COVER switch definition" * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input: Input: elan_i2c - add more hardware ID for Lenovo laptops Input: i8042 - add Lenovo XiaoXin Air 12 to i8042 nomux list Revert "Input: elants_i2c - report resolution information for touch major" Input: elan_i2c - only increment wakeup count on touch Input: synaptics - enable InterTouch for ThinkPad X1E 1st gen ARM: dts: n900: remove mmc1 card detect gpio Input: add `SW_MACHINE_COVER`
2020-07-13ARM: dts: meson8b: odroidc1: enable the SDHC controllerMartin Blumenstingl1-0/+26
Odroid-C1 has an eMMC connector where users can optionally install an eMMC module. The eMMC modules run off a 1.8V VQMMC supply which means that HS-200 mode can be used (this is the highest mode that the SDHC controller supports). Enable the SDHC controller so eMMC modules can be accessed. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20200620163654.37207-4-martin.blumenstingl@googlemail.com
2020-07-13ARM: dts: meson8b: ec100: enable the SDHC controllerMartin Blumenstingl1-0/+25
EC-100 has built-in eMMC flash which is hard-wired to 3.3V VCC (which means it's limited to high-speed MMC modes). Enable the SDHC controller to access the contents of the eMMC flash. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20200620163654.37207-3-martin.blumenstingl@googlemail.com
2020-07-13ARM: dts: meson: add the SDHC MMC controllerMartin Blumenstingl4-0/+50
Meson6, Meson8, Meson8b and Meson8m2 are using a similar SDHC controller IP which typically connects to an eMMC chip (because unlike the SDIO controller the SDHC controller has an 8-bit bus interface). On Meson8, Meson8b and Meson8m2 the clock inputs are all the same. However, Meson8m2 seems to have an improved version of the SHDC controller IP which doesn't require the driver to wait manually for a flush of a DMA transfer. Thus every SoC has it's own compatible string so if more difference are discovered they can be implemented. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20200620163654.37207-2-martin.blumenstingl@googlemail.com
2020-07-13ARM: dts: meson8b: add power domain controllerMartin Blumenstingl1-0/+27
The Meson8b SoCs have a power domain controller which can turn on/off various register areas (such as: Ethernet, VPU, etc.). Add the main "pwrc" controller and configure the Ethernet power domain. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20200620161010.23171-4-martin.blumenstingl@googlemail.com
2020-07-13ARM: dts: meson8m2: add resets for the power domain controllerMartin Blumenstingl1-0/+19
The Meson8m2 SoCs has introduced additional reset lines for the VPU compared to Meson8. Also it uses a slightly different VPU clock frequency compared to Meson8 since it can now achieve 364MHz thanks to the addition of the GP_PLL. Add the reset lines, VPU clock configuration and update the compatible string so the implementation differences can be managed. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20200620161010.23171-3-martin.blumenstingl@googlemail.com
2020-07-13ARM: dts: meson8: add power domain controllerMartin Blumenstingl1-0/+13
The Meson8 SoCs have a power domain controller which can turn on/off various register areas (such as: Ethernet, VPU, etc.). Add the main "pwrc" controller and configure the Ethernet power domain. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20200620161010.23171-2-martin.blumenstingl@googlemail.com
2020-07-13Replace HTTP links with HTTPS ones: OMAP DEVICE TREE SUPPORTAlexander A. Klimov109-114/+114
Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-07-13ARM: dts: omap5-uevm: Add watchdog timers for IPU and DSPSuman Anna1-0/+2
The watchdog timers have been added for the IPU and DSP remoteproc devices for the OMAP5 uEVM board. The following timers (same as the timers on OMAP4 Panda boards) are used as the watchdog timers, DSP : GPT6 IPU : GPT9 & GPT11 (one for each Cortex-M4 core) The MPU-side drivers will use this data to initialize the watchdog timers, and listen for any watchdog triggers. The BIOS-side code needs to configure and refresh these timers properly to not throw a watchdog error. These timers can be changed or removed as per the system integration needs, alongside appropriate equivalent changes on the firmware side. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-07-13ARM: dts: omap4-panda-common: Add watchdog timers for IPU and DSPSuman Anna1-0/+2
The watchdog timers have been added for the IPU and DSP remoteproc devices on all the OMAP4-based Panda boards. The following timers are used as the watchdog timers, DSP : GPT6 IPU : GPT9 & GPT11 (one for each Cortex-M3 core) The MPU-side drivers will use this data to initialize the watchdog timers, and listen for any watchdog triggers. The BIOS-side code needs to configure and refresh these timers properly to not throw a watchdog error. These timers can be changed or removed as per the system integration needs, alongside appropriate equivalent changes on the firmware side. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-07-13ARM: dts: omap5-uevm: Add system timers to DSP and IPUSuman Anna1-0/+2
The BIOS System Tick timers have been added for the IPU and DSP remoteproc devices for the OMAP5 uEVM boards. The following timers (same as the timers on OMAP4 Panda boards) are chosen: IPU : GPT3 (SMP-mode) DSP : GPT5 IPU has two Cortex-M4 processors, and is currently expected to be running in SMP-mode, so only a single timer suffices to provide the BIOS tick timer. An additional timer should be added for the second processor in IPU if it were to be run in non-SMP mode. The timer value also needs to be unique from the ones used by other processors so that they can be run simultaneously. The timers are optional, but are mandatory to support device management features such as power management and watchdog support. The above are added to successfully boot and execute firmware images configured with the respective timers, images that use internal processor subsystem timers are not affected. The timers can be changed or removed as per the system integration needs, alongside equivalent changes on the firmware side. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-07-13ARM: dts: omap5-uevm: Add CMA pools and enable IPU & DSPSuman Anna1-0/+30
The CMA reserved memory nodes have been added for the IPU and DSP remoteproc devices on the OMAP5 uEVM board. These nodes are assigned to the respective rproc device nodes, and both the IPU and DSP remote processors are enabled for this board. The current CMA pools and sizes are defined statically for each device. The starting addresses are fixed to meet current dependencies on the remote processor firmwares, and will go away when the remote-side code has been improved to gather this information runtime during its initialization. An associated pair of the rproc node and its CMA node can be disabled later on if there is no use-case defined to use that remote processor. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-07-13ARM: dts: omap5: Add aliases for rproc nodesSuman Anna1-0/+2
Add aliases for the DSP and IPU remoteproc processor nodes common to all OMAP5 boards. The aliases uses the stem "rproc", and are identical to the values chosen on OMAP4 boards. The aliases can be overridden, if needed, in the respective board files. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-07-13ARM: dts: omap5: Add DSP and IPU nodesSuman Anna1-0/+23
OMAP5, like OMAP4, also has two remote processor subsystems, DSP and IPU. The IPU subsystem though has dual Cortex-M4 processors instead of the dual Cortex-M3 processors in OMAP4, but otherwise has almost the same set of features. Add the DT nodes for these two processor sub-systems for all OMAP5 SoCs. The nodes have the 'iommus', 'clocks', 'resets', 'firmware' and 'mboxes' properties added, and are disabled for now. The IPU node has its L2 RAM memory specified through the 'reg' and 'reg-names' properties. The DSP node doesn't have these since it doesn't have any L2 RAM memories, but has an additional 'ti,bootreg' property instead as it has a specific boot register that needs to be programmed for booting. These nodes should be enabled as per the individual product configuration in the corresponding board dts files. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-07-13ARM: dts: omap4-panda-common:: Add system timers to DSP and IPUSuman Anna1-0/+2
The BIOS System Tick timers have been added for the IPU and DSP remoteproc devices on all the OMAP4-based Panda boards. The following DMTimers are chosen: IPU : GPT3 (SMP-mode) DSP : GPT5 IPU has two Cortex-M3 processors, and is currently expected to be running in SMP-mode, so only a single timer suffices to provide the BIOS tick timer. An additional timer should be added for the second processor in IPU if it were to be run in non-SMP mode. The timer value also needs to be unique from the ones used by other processors so that they can be run simultaneously. The timers are optional, but are mandatory to support device management features such as power management and watchdog support. The above are added to successfully boot and execute firmware images configured with the respective timers, images that use internal processor subsystem timers are not affected. The timers can be changed or removed as per the system integration needs, alongside equivalent changes on the firmware side. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-07-13ARM: dts: omap4-panda-common: Add CMA pools and enable IPU & DSPSuman Anna1-0/+30
The CMA reserved memory nodes have been added for the IPU and DSP remoteproc devices on all the OMAP4-based Panda boards. These nodes are assigned to the respective rproc device nodes, and both the IPU and DSP remote processors are enabled for all these boards. The current CMA pools and sizes are defined statically for each device. The starting addresses are fixed to meet current dependencies on the remote processor firmwares, and will go away when the remote-side code has been improved to gather this information runtime during its initialization. An associated pair of the rproc node and its CMA node can be disabled later on if there is no use-case defined to use that remote processor. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-07-13ARM: dts: omap4: Add aliases for rproc nodesSuman Anna1-0/+2
Add aliases for the DSP and IPU remoteproc processor nodes common to all OMAP4 boards. The aliases uses the stem "rproc". The aliases can be overridden, if needed, in the respective board files. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-07-13ARM: dts: omap4: Add IPU DT nodeSuman Anna1-0/+12
The DT node for the Dual-Cortex M3 IPU processor sub-system has been added for OMAP4 SoCs. The L2RAM memory region information has been added to the node through the 'reg' and 'reg-names' properties. The node has the 'iommus', 'clocks', 'resets', 'mboxes' and 'firmware' properties also added, and is disabled for now. It should be enabled as per the individual product configuration in the corresponding board dts files. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-07-13ARM: dts: omap4: Update the DSP nodeSuman Anna1-4/+11
The compatible property for the DSP node is updated to match the OMAP remoteproc bindings. The node is moved from the soc node to the ocp node to better reflect the connectivity from MPU side. The node is updated with the 'ti,bootreg', 'clocks', 'resets', 'iommus', 'mboxes' and 'firmware' properties. Note that the node does not have any 'reg' or 'reg-names' properties since it doesn't have any L2 RAM memory, but only Unicaches. The node is disabled for now, and should be enabled as per the individual product configuration in the corresponding board dts files. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-07-13ARM: dts: omap5: Add timer_sys_ck clocks for timersSuman Anna2-22/+33
The commit d41e53040926 ("clk: ti: omap5: cleanup unnecessary clock aliases") has cleaned up all timer_sys_ck clock aliases and retained only the timer_32k_ck clock alias. The OMAP clocksource timer driver though still uses this clock alias when reconfiguring the parent clock source for the timer functional clocks, so add these clocks to all the timer nodes except for the always-on timers 1 and 12. This is required by the OMAP remoteproc driver to successfully acquire a timer and configure the source clock to be driven from timer_sys_ck clock. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-07-13ARM: dts: omap4: Add timer_sys_ck clocks for timersSuman Anna2-22/+33
The commit 1c7de9f27a65 ("clk: ti: omap4: cleanup unnecessary clock aliases") has cleaned up all timer_sys_ck clock aliases and retained only the timer_32k_ck clock alias. The OMAP clocksource timer driver though still uses this clock alias when reconfiguring the parent clock source for the timer functional clocks, so add these clocks to all the timer nodes. This is required by the OMAP remoteproc driver to successfully acquire a timer and configure the source clock to be driven from timer_sys_ck clock. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-07-13ARM: dts: am335x-pocketbeagle: set default mux for gpio pinsDrew Fustini1-0/+125
These pins on the PocketBeagle P1 and P2 headers are connected to AM3358 balls with gpio lines, and these pins are not used for any other peripherals by default. These GPIO lines are unclaimed and could be used by userspace program through the gpiod ABI. This patch adds a "default" state in the am33xx_pinmux node and sets the mux for those pins to gpio (mode 7) and input enable. The "pinctrl-single,bias-pullup" and "pinctrl-single,bias-pulldown" pinconf properties are also set for each pin per the ball reset state in section 4.2 of the datasheet [0]. This is the AM335x pin control register format in Table 9-60 [1]: bit attribute value ---------------------------------- 31-7 reserved 0 on reset 6 slew { 0: fast, 1: slow } 5 rx_active { 0: rx disable, 1: rx enabled } 4 pu_typesel { 0: pulldown select, 1: pullup select } 3 puden { 0: pud enable, 1: disabled } 2 mode 3 bits to selec mode 0 to 7 1 mode 0 mode The values for the bias pinconf properties are derived as follows: pinctrl-single,bias-pullup = <[input] [enabled] [disable] [mask]>; pinctrl-single,bias-pullup = < 0x10 0x10 0x10 0x18 >; 2^5 2^4 2^3 2^2 2^1 2^0 | 0x20 0x10 0x08 0x04 0x02 0x01 | --------------------------------------------------| input x 1 0 x x x | 0x10 enabled x 1 0 x x x | 0x10 disabled x 0 0 x x x | 0x00 mask x 1 1 x x x | 0x18 pinctrl-single,bias-pulldown = <[input] [enabled] [disable] [mask]>; pinctrl-single,bias-pulldown = < 0x0 0x0 0x10 0x18 >; 2^5 2^4 2^3 2^2 2^1 2^0 | 0x20 0x10 0x08 0x04 0x02 0x01 | --------------------------------------------------| input x 0 0 x x x | 0x00 enabled x 0 0 x x x | 0x00 disabled x 1 0 x x x | 0x10 mask x 1 1 x x x | 0x18 [0] http://www.ti.com/lit/ds/symlink/am3358.pdf [1] https://www.ti.com/lit/ug/spruh73q/spruh73q.pdf Signed-off-by: Drew Fustini <drew@beagleboard.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-07-13ARM: OMAP2+: Drop legacy platform data for am4 dwc3Tony Lindgren1-2/+0
We can now probe devices with ti-sysc interconnect driver and dts data. Let's drop the related platform data and custom ti,hwmods dts property. As we're just dropping data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. [tony@atomide.com: fixed typo for am3 vs am4] Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-07-13Merge tag 'arm-soc/for-5.9/devicetree' of ↵Arnd Bergmann14-4/+254
https://github.com/Broadcom/stblinux into arm/dt This pull request contains Broadcom ARM-based SoCs Device Tree changes for 5.9 please pull the following: - Rafal specifies the switch ports for various Luxul devices (XAP-1410, XAP-1510, XAP-1610, XWC-1000, XWC-2000, XWR-1200, XWR-3100, XWR-3150) - Krzysztof fixes the L2 cache controller node name to conform to dtschema - Maxime introduces two new clock providers for Raspberry Pi 4, one to support firmware based clocks and another one for the DVP block feeding into the two HDMI blocks. * tag 'arm-soc/for-5.9/devicetree' of https://github.com/Broadcom/stblinux: ARM: dts: bcm: Align L2 cache-controller nodename with dtschema ARM: dts: BCM5301X: Specify switch ports for Luxul devices ARM: dts: bcm2711: Add HDMI DVP ARM: dts: bcm2711: Add firmware clocks node Link: https://lore.kernel.org/r/20200707045759.17562-1-f.fainelli@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-13Merge tag 'omap-for-v5.9/dt-signed' of ↵Arnd Bergmann6-54/+335
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt Device tree changes for omaps for v5.9 merge window This series of changes configures the GPIO line names for am335x beaglebone black and pocketbeagle to make it easier to configure the pins. To make use of the pins, we also add the gpio-ranges for am335x. We also enable IPU and DSP repmoteproc for am5729-beaglebone-ai, and then there are two non-urgent dtschema validator warning fixes. * tag 'omap-for-v5.9/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: am335x-pocketbeagle: add gpio-line-names ARM: dts: am335x-boneblack: add gpio-line-names ARM: dts: am33xx-l4: add gpio-ranges ARM: dts: am5729-beaglebone-ai: Disable ununsed mailboxes ARM: dts: am5729-beaglebone-ai: Enable IPU & DSP rprocs ARM: dts: am: Align L2 cache-controller nodename with dtschema ARM: dts: omap: Align L2 cache-controller nodename with dtschema Link: https://lore.kernel.org/r/pull-1594402929-762188@atomide.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-13Merge tag 'uniphier-dt-v5.9' of ↵Arnd Bergmann11-28/+73
git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into arm/dt UniPhier ARM SoC DT updates for v5.9 - add missing interrupts property to support card serial - fix node names to follow the DT schema - add PCIe endpoint and PHY nodes for Pro5 SoC - simplify device hierarchy of support-card.dtsi * tag 'uniphier-dt-v5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier: ARM: dts: uniphier: simplify support-card node structure ARM: dts: uniphier: Add PCIe endpoint and PHY node for Pro5 ARM: dts: uniphier: Rename ethphy node to ethernet-phy ARM: dts: uniphier: give fixed port number to support card serial ARM: dts: uniphier: rename support card serial node to fix schema warning ARM: dts: uniphier: add interrupts to support card serial Link: https://lore.kernel.org/r/CAK7LNARGDcCKxV3-H7WmuZAVe49n0QF+672-KN0tsP0och0a_A@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-13ARM: dts: imx6ull: add MYiR MYS-6ULX SBCParthiban Nallathambi3-0/+257
Add support for the MYiR imx6ULL based single board computer equipped with on board 256MB NAND & RAM. The board also provides expansion header for expansion board, but this commit adds only support for SBC. Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-13ARM: dts: vf610-zii-spb4: Add node for switch watchdogChris Healy1-0/+19
Add I2C child node for switch watchdog present on SPB4 Signed-off-by: Chris Healy <cphealy@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-13ARM: dts: colibri-imx6: remove pinctrl-names orphanPhilippe Schenker1-1/+0
This is not necessary without a pinctrl-0 statement. Remove this orphan. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-13ARM: dts: imx: default to #pwm-cells = <3> in the SoC dtsi filesUwe Kleine-König68-53/+116
The imx-pwm driver supports 3 cells and this is the more flexible setting. So use it by default and overwrite it back to two for the files that reference the PWMs with just 2 cells to minimize changes. This allows to drop explicit setting to 3 cells for the boards that already depend on this. The boards that are now using 2 cells explicitly can be converted to 3 individually. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-13ARM: dts: vf610-zii-scu4-aib: Configure fibre ports to 1000BaseXAndrew Lunn1-10/+10
The SFF soldered onto the board expect the ports to use 1000BaseX. It makes no sense to have the ports set to SGMII, since they don't even support that mode. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Chris Healy <cphealy@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-13ARM: dts: vf610-zii-dev-rev-c: Configure fiber port to 1000BaseXChris Healy1-1/+1
The SFF soldered onto the board expects the port to use 1000BaseX. It makes no sense to have the port set to SGMII, since it doesn't even support that mode. Signed-off-by: Chris Healy <cphealy@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-13ARM: dts: ZII: update MDIO speed and preambleChris Healy6-0/+12
Update MDIO configuration with ZII devices to fully utilize MDIO endpoint capabilities. All devices support 12.5MHz clock and don't require MDIO preable. Signed-off-by: Chris Healy <cphealy@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-13ARM: dts: vfxxx: Add node for CAAMAndrey Smirnov1-0/+22
Add node for CAAM device in NXP Vybrid SoC. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Chris Healy <cphealy@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-13ARM: dts: imx6qp-sabresd: enable sataRichard Zhu1-0/+4
Enable SATA on iMX6QP SABRESD board. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-13ARM: dts: imx6qp-sabreauto: enable sataRichard Zhu1-0/+4
Enable SATA on iMX6QP SABREAUTO board. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-13ARM: dts: add Protonic RVT boardOleksij Rempel2-0/+185
Protonic RVT is an internal development platform for a wireless ISObus Virtual Terminal based on COTS tablets, and the predecessor of the WD2 platform. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: David Jander <david@protonic.nl> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-13ARM: dts: add Protonic VT7 boardOleksij Rempel2-0/+412
The Protonic VT7 is a mid-class ISObus Virtual Terminal with a 7 inch touchscreen display. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Robin van der Gracht <robin@protonic.nl> Signed-off-by: David Jander <david@protonic.nl> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-13ARM: dts: add Protonic WD2 boardOleksij Rempel2-0/+189
Add support for the Protonic WD2 board, which is an internal development platform for low-cost agricultural Virtual Terminals based on COTS tablets and web applications. It inherits from the PRTI6Q base class. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: David Jander <david@protonic.nl> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-13ARM: dts: add Protonic PRTI6Q boardOleksij Rempel3-0/+707
Protonic PRTI6Q is a development board and a base class for different specific customer application boards based on the i.MX6 family of SoCs, developed by Protonic Holland. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: David Jander <david@protonic.nl> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-13ARM: dts: imx6ul: Add ASRC device nodeShengjiu Wang1-0/+25
Add ASRC device node. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-13ARM: dts: imx: Align L2 cache-controller nodename with dtschemaKrzysztof Kozlowski5-5/+5
Fix dtschema validator warnings like: l2-cache@a02000: $nodename:0: 'l2-cache@a02000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-13ARM: dts: vf610: Align L2 cache-controller nodename with dtschemaKrzysztof Kozlowski1-1/+1
Fix dtschema validator warnings like: l2-cache@40006000: $nodename:0: 'l2-cache@40006000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-13ARM: dts: imx6sx-sdb: Add MQS supportShengjiu Wang4-0/+62
Add MQS support. As the pin conflict with usdhc2, then need to add a separate dts. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-13ARM: dts: ls1021a: add ftm_alarm0 DT nodeBiwen Li1-0/+15
The patch add ftm_alarm0 DT node - add rcpm node - add ftm_alarm0 node - aliases ftm_alarm0 as rtc1 Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-13ARM: dts: imx6sx-sabreauto: Add cs42888 sound card supportShengjiu Wang2-0/+79
Complete the ESAI node and Add cs42888 sound card support. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-13ARM: dts: imx6sx-sabreauto: Add SPDIF supportShengjiu Wang1-0/+21
Add SPDIF support. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-13ARM: dts: imx6sx-sdb: Add SPDIF supportShengjiu Wang1-0/+23
Add SPDIF support. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-03 21:02:22 +0300