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2021-01-07ARM: dts: qcom: sdx55-mtp: Add regulator nodesVinod Koul1-0/+164
This adds the regulators found on SDX55 MTP. Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210106125322.61840-19-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-07ARM: dts: qcom: sdx55-mtp: Add pmx55 pmicVinod Koul1-0/+1
SDX55-mtp features PMX55 pmic, so include the dts as well Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210106125322.61840-16-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-07ARM: dts: qcom: Add PMIC pmx55 dtsVinod Koul1-0/+84
This adds DTS for PMIC PMX55 found in Qualcomm platforms. Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210106125322.61840-18-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-07ARM: dts: qcom: sdx55: Add rpmpd nodeVinod Koul1-0/+51
This adds rpmpd node and opps for this node to the SDX55 dts. Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210106125322.61840-17-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-07ARM: dts: qcom: sdx55-mtp: Add pm8150b pmicVinod Koul1-0/+1
SDX55-mtp features PM8150B pmic, so include the dts as well Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210106125322.61840-15-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-07ARM: dts: qcom: sdx55: Add spmi nodeVinod Koul1-0/+19
This adds SPMI node to SDX55 dts. Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210106125322.61840-14-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-07ARM: dts: qcom: sdx55-mtp: Enable QPIC NANDManivannan Sadhasivam1-0/+12
Enable QPIC NAND on SDX55-MTP board. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210106125322.61840-13-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-07ARM: dts: qcom: sdx55-mtp: Enable BAM DMAManivannan Sadhasivam1-0/+4
Enable BAM DMA on SDX55-MTP board. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210106125322.61840-12-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-07ARM: dts: qcom: sdx55: Add QPIC NAND supportManivannan Sadhasivam1-0/+22
Add qpic_nand node to support QPIC NAND controller on SDX55 platform. Since there is no "aon" clock in SDX55, a dummy clock is provided. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210106125322.61840-11-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-07ARM: dts: qcom: sdx55: Add QPIC BAM supportManivannan Sadhasivam1-0/+12
Add qpic_bam node to support QPIC BAM DMA controller on SDX55 platform. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210106125322.61840-10-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-07ARM: dts: qcom: sdx55: Add Shared memory manager supportManivannan Sadhasivam1-0/+6
Add smem node to support shared memory manager on SDX55 platform. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210106125322.61840-9-manivannan.sadhasivam@linaro.org [bjorn: Moved smem node out from /soc] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-07ARM: dts: qcom: sdx55: Add support for TCSR MutexManivannan Sadhasivam1-0/+6
Add TCSR Mutex node to support Qualcomm Hardware Mutex block on SDX55 platform. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210106125322.61840-8-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-07ARM: dts: qcom: sdx55: Enable ARM SMMUBjorn Andersson1-0/+24
Add a node for the ARM SMMU found in the SDX55. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210106125322.61840-7-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-07ARM: dts: qcom: sdx55: Add support for SDHCI controllerManivannan Sadhasivam1-0/+13
Add devicetree support for SDHCI controller found in Qualcomm SDX55 platform. The SDHCI controller is based on the MSM SDHCI v5 IP. Hence, the support is added by reusing the existing sdhci driver with "qcom,sdhci-msm-v5" as the fallback. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210106125322.61840-5-manivannan.sadhasivam@linaro.org [bjorn: added include of qcom,gcc-sdx55.h] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-06ARM: dts: sun8i-h2-plus-bananapi-m2-zero: add poweroff nodeMichael Klein1-0/+5
Add add devicetree information for the regulator-poweroff driver. Signed-off-by: Michael Klein <michael@fossekall.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20201211151445.115943-4-michael@fossekall.de
2021-01-06ARM: dts: sun8i-v3: Add support for the SL631 Action Camera with IMX179Paul Kocialkowski3-0/+151
The SL631 is a family of Allwinner V3 action cameras sold under various names, such as SJCAM SJ4000 Air or F60 Action Camera. Devices in this family share a common board design but can be found with different image sensors, including the IMX179 and the OV4689. This adds support for a common dtsi for the SL631 family as well as a specific dts for the IMX179 fashion, which will later be populated with an IMX179 node when a driver is available. Features that were tested on the device include: - UART debug - MMC - USB peripheral (e.g. g_ether) - Buttons - SPI NOR flash Note that the exact designer/vendor of these boards is unknown. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20201206165131.1041983-6-contact@paulk.fr
2021-01-06ARM: dts: sun8i: Cleanup the Pinecube AXP209 nodePaul Kocialkowski1-6/+2
This fixes a few things with the Pinecube AXP209 node: - No compatible is required since it is using an AXP209 (not AXP203) according to the schematics and this is what the included axp209.dtsi already has; - The interrupt-controller and #interrupt-cells properties are already described in the included axp209.dtsi; - The interrupt comes through the NMI controller, not directly through the GIC. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20201206165131.1041983-4-contact@paulk.fr
2021-01-06ARM: dts: sun8i-v3s: Add the V3s NMI IRQ controllerPaul Kocialkowski1-1/+10
The V3s/V3 has a NMI interrupt controller, mainly used for the AXP209. Its address follows the system controller block, which was previously incorrectly described as spanning over 0x1000 address bytes. Even though this is what the Allwinner documentation indicates, precedence from other SoCs such as the R40 suggests that this is not actually the case. This reduces the system controller address span up to the NMI controller and adds a node for the controller, with its dedicated compatible. While the interrupt number was found in Allwinner's documentation, the address for the controller is specified in any Allwinner SDK supporting sun8iw8 (V3/V3s) at: drivers/power/axp_power/axp20/axp20-board.c It was tested to work on a V3 board with an AXP209 connected to the NMI interrupt line. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20201206165131.1041983-3-contact@paulk.fr
2021-01-06ARM: dts: qcom: sdx55: Add reserved memory nodesVinod Koul2-0/+73
This adds reserved memory nodes to the SDX55 dtsi as defined by v6 of the memory map Signed-off-by: Vinod Koul <vkoul@kernel.org> [mani: moved modem regions to board dts] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210106125322.61840-3-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-06ARM: dts: qcom: sdx55: Add pincontrol nodeVinod Koul1-0/+10
This adds pincontrol node to SDX55 dts. Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210106125322.61840-2-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-05ARM: dts: imx6qdl-kontron-samx6i: fix pwms for lcd-backlightMarco Felsch1-1/+1
The pwms property have to specify the no-/inverted flag since commit fa28d8212ede ("ARM: dts: imx: default to #pwm-cells = <3> in the SoC dtsi files"). Fixes: fa28d8212ede ("ARM: dts: imx: default to #pwm-cells = <3> in the SoC dtsi files") Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-01-04ARM: dts: sun6i-a31s-sinovoip-bpi-m2: add gpio-line-namesMichael Klein1-0/+71
Add gpio-line-names as documented on gitbooks [1] and in the schematics [2]. [1]: https://bananapi.gitbook.io/bpi-m2/en/bpi-m2_gpio_pin_define [2]: https://drive.google.com/file/d/0B4PAo2nW2KfnRERWNnJGSGxJbmM/view Signed-off-by: Michael Klein <michael@fossekall.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20201202195144.2105036-1-michael@fossekall.de
2021-01-03ARM: dts: exynos: Add top-off charging regulator node for I9100Timon Baetz1-7/+14
Value taken from Galaxy S2 Epic 4G Touch SPH-D710 Android vendor kernel [0] which always sets 200mA. Also rearrange regulators based on definition in max8997.h. [0] https://github.com/krzk/linux-vendor-backup/blob/samsung/galaxy-s2-epic-4g-touch-sph-d710-exynos4210-dump/drivers/power/sec_battery_u1.c#L1525 Signed-off-by: Timon Baetz <timon.baetz@protonmail.com> Link: https://lore.kernel.org/r/20201230205139.1812366-8-timon.baetz@protonmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2021-01-03ARM: dts: exynos: Fix charging regulator voltage and current for I9100Timon Baetz1-5/+4
Set CHARGER current and CHARGER_CV voltage according to Galaxy S2 Epic 4G Touch SPH-D710 Android vendor sources [0,1]. Remove regulator-always-on. The regulator can be enabled and disabled based on extcon events. [0] https://github.com/krzk/linux-vendor-backup/blob/samsung/galaxy-s2-epic-4g-touch-sph-d710-exynos4210-dump/drivers/power/max8997_charger_u1.c#L169-L170 [1] https://github.com/krzk/linux-vendor-backup/blob/samsung/galaxy-s2-epic-4g-touch-sph-d710-exynos4210-dump/drivers/power/max8997_charger_u1.c#L390-L391 Signed-off-by: Timon Baetz <timon.baetz@protonmail.com> Link: https://lore.kernel.org/r/20201230205139.1812366-7-timon.baetz@protonmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-12-31ARM: dts: qcom: Add SDX55 platform and MTP board supportManivannan Sadhasivam3-1/+222
Add basic devicetree support for SDX55 platform and MTP board from Qualcomm. The SDX55 platform features an ARM Cortex A7 CPU which forms the Application Processor Sub System (APSS) along with standard Qualcomm peripherals like GCC, TLMM, BLSP, QPIC, and BAM etc... Also, there exists the networking parts such as IPA, MHI, PCIE-EP, EMAC, and Modem etc.. Currently, this basic devicetree support includes GCC, RPMh clock, INTC and Debug UART. Co-developed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20201126083138.47047-3-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-12-31arm: dts: owl-s500-roseapplepi: Add I2C pinctrl configurationCristian Ciocaltea1-0/+44
Add pinctrl definitions for the I2C controllers used in RoseapplePi SBC. For the moment enable only I2C0, which is used by the ATC2603C PMIC. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2020-12-31arm: dts: owl-s500-roseapplepi: Add uSD supportCristian Ciocaltea1-0/+50
Add uSD support for RoseapplePi SBC using a fixed regulator as a temporary solution until PMIC support becomes available. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2020-12-31arm: dts: owl-s500: Add SIRQ controllerCristian Ciocaltea1-0/+10
Add SIRQ controller node for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2020-12-31arm: dts: owl-s500: Add I2C supportCristian Ciocaltea1-0/+40
Add I2C controller nodes for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2020-12-31arm: dts: owl-s500: Add MMC supportCristian Ciocaltea1-0/+33
Add MMC controller nodes for Actions Semi S500 SoC, in order to facilitate access to SD/EMMC/SDIO cards. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2020-12-31arm: dts: owl-s500: Add pinctrl & GPIO supportCristian Ciocaltea1-0/+20
Add pinctrl node for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2020-12-31arm: dts: owl-s500: Add DMA controllerCristian Ciocaltea1-0/+14
Add DMA controller node for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2020-12-31arm: dts: owl-s500: Add Reset controllerCristian Ciocaltea1-0/+2
Add reset controller property and bindings header for the Actions Semi S500 SoC DTS. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2020-12-31arm: dts: owl-s500: Set CMU clocks for UARTsCristian Ciocaltea6-35/+7
Set Clock Management Unit clocks for the UART nodes of Actions Semi S500 SoCs and remove the dummy "uart2_clk" and "uart3_clk" fixed clocks. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2020-12-31arm: dts: owl-s500: Add Clock Management UnitCristian Ciocaltea1-0/+14
Add Clock Management Unit for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2020-12-30ARM: dts; gta04: SPI panel chip select is active lowH. Nikolaus Schaller1-1/+1
With the arrival of commit 2fee9583198eb9 ("spi: dt-bindings: clarify CS behavior for spi-cs-high and gpio descriptors") it was clarified what the proper state for cs-gpios should be, even if the flag is ignored. The driver code is doing the right thing since 766c6b63aa04 ("spi: fix client driver breakages when using GPIO descriptors") The chip-select of the td028ttec1 panel is active-low, so we must omit spi-cs-high; attribute (already removed by separate patch) and should now use GPIO_ACTIVE_LOW for the client device description to be fully consistent. Fixes: 766c6b63aa04 ("spi: fix client driver breakages when using GPIO descriptors") CC: stable@vger.kernel.org Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2020-12-29ARM: dts: exynos: correct PMIC interrupt trigger level on Odroid XU3 familyKrzysztof Kozlowski1-1/+1
The Samsung PMIC datasheets describe the interrupt line as active low with a requirement of acknowledge from the CPU. The falling edge interrupt will mostly work but it's not correct. Fixes: aac4e0615341 ("ARM: dts: odroidxu3: Enable wake alarm of S2MPS11 RTC") Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/20201210212903.216728-6-krzk@kernel.org
2020-12-29ARM: dts: exynos: correct PMIC interrupt trigger level on Arndale OctaKrzysztof Kozlowski1-1/+1
The Samsung PMIC datasheets describe the interrupt line as active low with a requirement of acknowledge from the CPU. The falling edge interrupt will mostly work but it's not correct. Fixes: 1fed2252713e ("ARM: dts: fix pinctrl for s2mps11-irq on exynos5420-arndale-octa") Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/20201210212903.216728-5-krzk@kernel.org
2020-12-29ARM: dts: exynos: correct PMIC interrupt trigger level on SpringKrzysztof Kozlowski1-1/+1
The Samsung PMIC datasheets describe the interrupt line as active low with a requirement of acknowledge from the CPU. Without specifying the interrupt type in Devicetree, kernel might apply some fixed configuration, not necessarily working for this hardware. Fixes: 53dd4138bb0a ("ARM: dts: Add exynos5250-spring device tree") Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20201210212903.216728-4-krzk@kernel.org
2020-12-29ARM: dts: exynos: correct PMIC interrupt trigger level on RinatoKrzysztof Kozlowski1-1/+1
The Samsung PMIC datasheets describe the interrupt line as active low with a requirement of acknowledge from the CPU. Without specifying the interrupt type in Devicetree, kernel might apply some fixed configuration, not necessarily working for this hardware. Fixes: faaf348ef468 ("ARM: dts: Add board dts file for exynos3250-rinato") Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/20201210212903.216728-3-krzk@kernel.org
2020-12-29ARM: dts: exynos: correct PMIC interrupt trigger level on MonkKrzysztof Kozlowski1-1/+1
The Samsung PMIC datasheets describe the interrupt line as active low with a requirement of acknowledge from the CPU. Without specifying the interrupt type in Devicetree, kernel might apply some fixed configuration, not necessarily working for this hardware. Fixes: e0cefb3f79d3 ("ARM: dts: add board dts file for Exynos3250-based Monk board") Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20201210212903.216728-2-krzk@kernel.org
2020-12-29ARM: dts: exynos: correct PMIC interrupt trigger level on Artik 5Krzysztof Kozlowski1-1/+1
The Samsung PMIC datasheets describe the interrupt line as active low with a requirement of acknowledge from the CPU. Without specifying the interrupt type in Devicetree, kernel might apply some fixed configuration, not necessarily working for this hardware. Fixes: b004a34bd0ff ("ARM: dts: exynos: Add exynos3250-artik5 dtsi file for ARTIK5 module") Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/20201210212903.216728-1-krzk@kernel.org
2020-12-29ARM: dts: exynos: use Exynos5420 dedicated USB2 PHY compatibleMarek Szyprowski1-3/+3
USB2.0 PHY in Exynos5420 differs from Exynos5250 variant a bit, so use the recently introduced dedicated compatible for Exynos5420. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/20201120085637.7299-3-m.szyprowski@samsung.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-12-28ARM: dts: sun8i-h2-plus-bananapi-m2-zero: add regulator nodes vcc-dram and ↵Michael Klein1-0/+24
vcc1v2 Add regulator nodes vcc-dram and vcc1v2 to the devicetree. These regulators correspond to U4 and U5 in the schematics: http://forum.banana-pi.org/t/bpi-m2-zero-schematic-diagram-public/4111 Signed-off-by: Michael Klein <michael@fossekall.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20201130183841.136708-1-michael@fossekall.de
2020-12-23Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linuxLinus Torvalds3-36/+44
Pull ARM updates from Russell King: - Rework phys/virt translation - Add KASan support - Move DT out of linear map region - Use more PC-relative addressing in assembly - Remove FP emulation handling while in kernel mode - Link with '-z norelro' - remove old check for GCC <= 4.2 in ARM unwinder code - disable big endian if using clang's linker * tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm: (46 commits) ARM: 9027/1: head.S: explicitly map DT even if it lives in the first physical section ARM: 9038/1: Link with '-z norelro' ARM: 9037/1: uncompress: Add OF_DT_MAGIC macro ARM: 9036/1: uncompress: Fix dbgadtb size parameter name ARM: 9035/1: uncompress: Add be32tocpu macro ARM: 9033/1: arm/smp: Drop the macro S(x,s) ARM: 9032/1: arm/mm: Convert PUD level pgtable helper macros into functions ARM: 9031/1: hyp-stub: remove unused .L__boot_cpu_mode_offset symbol ARM: 9044/1: vfp: use undef hook for VFP support detection ARM: 9034/1: __div64_32(): straighten up inline asm constraints ARM: 9030/1: entry: omit FP emulation for UND exceptions taken in kernel mode ARM: 9029/1: Make iwmmxt.S support Clang's integrated assembler ARM: 9028/1: disable KASAN in call stack capturing routines ARM: 9026/1: unwind: remove old check for GCC <= 4.2 ARM: 9025/1: Kconfig: CPU_BIG_ENDIAN depends on !LD_IS_LLD ARM: 9024/1: Drop useless cast of "u64" to "long long" ARM: 9023/1: Spelling s/mmeory/memory/ ARM: 9022/1: Change arch/arm/lib/mem*.S to use WEAK instead of .weak ARM: kvm: replace open coded VA->PA calculations with adr_l call ARM: head.S: use PC relative insn sequence to calculate PHYS_OFFSET ...
2020-12-22ARM: dts: ux500/golden: Set display max brightnessLinus Walleij1-0/+1
A too high brightness by default (default is max) makes the screen go blank. Set this to 15 as in the Vendor tree. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Cc: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20201214223413.253893-1-linus.walleij@linaro.org' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-12-21Merge branch 'devel-stable' into for-nextRussell King1-15/+3
2020-12-21ARM: 9037/1: uncompress: Add OF_DT_MAGIC macroGeert Uytterhoeven1-5/+7
The DTB magic marker is stored as a 32-bit big-endian value, and thus depends on the CPU's endianness. Add a macro to define this value in native endianness, to reduce #ifdef clutter and (future) duplication. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Nicolas Pitre <nico@fluxnic.net> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2020-12-21ARM: 9036/1: uncompress: Fix dbgadtb size parameter nameGeert Uytterhoeven1-2/+2
The dbgadtb macro is passed the size of the appended DTB, not the end address. Fixes: c03e41470e901123 ("ARM: 9010/1: uncompress: Print the location of appended DTB") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
2020-12-21ARM: 9035/1: uncompress: Add be32tocpu macroGeert Uytterhoeven1-14/+12
DTB stores all values as 32-bit big-endian integers. Add a macro to convert such values to native CPU endianness, to reduce duplication. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Nicolas Pitre <nico@fluxnic.net> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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