index
:
starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starfive-6.6.48-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
arch
/
arm
/
boot
/
dts
/
sun8i-v3s.dtsi
Age
Commit message (
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)
Author
Files
Lines
2019-06-06
ARM: dts: sun8i: v3s: Add external crystals accuracy
Maxime Ripard
1
-0
/
+2
2019-06-06
ARM: dts: sun8i: v3s: Fix the RTC node
Maxime Ripard
1
-4
/
+7
2019-03-25
ARM: dts: sunxi: Fix the TCON output clock
Maxime Ripard
1
-0
/
+1
2019-03-25
ARM: dts: sunxi: Fix GIC compatible
Maxime Ripard
1
-1
/
+1
2019-03-25
ARM: dts: sun8i: v3s: Fix Display Engine DTC warnings
Maxime Ripard
1
-8
/
+2
2018-11-28
ARM: dts: sun8i: v3s: Provide default muxing for relevant controllers
Maxime Ripard
1
-0
/
+2
2018-11-28
ARM: dts: sun8i: v3s: Change pinctrl nodes to avoid warning
Maxime Ripard
1
-5
/
+5
2017-10-20
arm: dts: fix unit-address leading 0s
Rob Herring
1
-16
/
+16
2017-06-07
ARM: sun8i: v3s: add device nodes for DE2 display pipeline
Icenowy Zheng
1
-0
/
+83
2017-05-18
ARM: sun8i: v3s: enable SPI
Icenowy Zheng
1
-0
/
+19
2017-05-15
ARM: sun8i: v3s: add pinmux for mmc1
Icenowy Zheng
1
-0
/
+10
2017-05-15
ARM: sun8i: v3s: add LRADC device node
Icenowy Zheng
1
-0
/
+7
2017-05-15
ARM: sun8i: v3s: restore the usage of CCU definitions
Icenowy Zheng
1
-31
/
+33
2017-01-27
ARM: dts: sunxi: add dtsi file for V3s SoC
Icenowy Zheng
1
-0
/
+309