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2021-01-07ARM: dts: arria10: add PMU nodeDinh Nguyen1-2/+11
Add the PMU node for Arria10. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2020-08-17ARM: dts: socfpga: fix register entry for timer3 on Arria10Dinh Nguyen1-1/+1
Fixes the register address for the timer3 entry on Arria10. Fixes: 475dc86d08de4 ("arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC") Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2020-08-04Merge tag 'arm-dt-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-0/+2
Pull ARM SoC DT updates from Arnd Bergmann: "As usual, there are many patches addressing minor issues in existing DTS files, such as DTC warnings, or adding support for additional peripherals. There are three added SoCs in existing product families: - Amazon: Alpine v3 is a 16-core Cortex-A72 SoC from Amazon's Annapurna Labs, otherwise known as AL73400 or first-generation Graviton, and following the already supported Cortex-A1`5 and Cortex-A57 based Alpine chips. This one is added together with the official Evaluation platform. - Qualcomm: The Snapdragon SDM630 platform is a family of mid-range mobile phone chips from 2017 based on Cortex-A53 or Kryo 260 CPUs. A total of five end-user products are added based on these, all Android phones from Sony: Xperia 10, 10 Plus, XA2, XA2 Plus and XA2 Ultra. - Renesas: RZ/G2H (r8a774e1) is currently the top model in the Renesas RZ/G family, and apparently closely related to the RZ/G2N and RZ/G2M models we already support but has a faster GPU and additional on-chip peripherals. It is added along with the HopeRun HiHope RZ/G2H development board A small number of new boards for already supported SoCs also debut: - Allwinner sunxi: Only one new machine, revision v1.2 of the Pine64 PinePhone (non-Android) smartphone, containing minor changes compared to earlier versions. - Amlogic Meson: WeTek Core2 is an Amlogic S912 (GXM) based Set-top-box - Aspeed: EthanolX is AMD's EPYC data center rerence platform, using an ASpeed AST2600 baseboard management controller. - Mediatek: Lenovo IdeaPad Duet 10.1" (kukui/krane) is a new Chromebook based on the MT8183 (Helio P60t) SoC. - Nvidia Tegra: ASUS Google Nexus 7 and Acer Iconia Tab A500 are two Android tablets from around 2012 using Tegra 3 and Tegra 2, respectively. Thanks to PostmarketOS, these can now run mainline kernels and become useful again. The Jetson Xavier NX Developer Kit uses a SoM and carrier board for the Tegra194, their latest 64-bit chip based on Carmel CPU cores and Volta graphics. - NXP i.MX: Five new boards based on the 32-bit i.MX6 series are added: The MYiR MYS-6ULX single-board computer, and four different models of industrial computers from Protonic. - Qualcomm: MikroTik RouterBoard 3011 is a rackmounted router based on the 32-bit IPQ8064 networking SoC Three older phones get added, the Snapdragon 808 (msm8992) based Xiaomi Libra (Mi 4C) and Microsoft Lumia 950, originally running Windows Phone, and the Snapdragon 810 (msm8994) based Sony Xperia Z5. - Renesas: In addition to the HiHope RZ/G2H board mentioned above, we gain support for board versions 3.0 and 4.0 of the earlier RZ/G2M and RZ/G2N reference boards. Beacon EmbeddedWorks adds another SoM+Carrier development board for RZ/G2M. - Rockchips: Radxa Rock Pi N8 development board and the VMARC RK3288 SoM it is based on, using the high-end 32-bit rk3288 SoC. Notable updates to existing platforms are usually for added on-chip peripherals, including: - ASpeed AST2xxx (various) - Allwinner (cpufreq, thermal, Pinephone touchscreen) - Amlogic Meson (audio, gpu dvdfs, board updates) - Arm Versatile - Broadcom (board updates for switch ports, Raspberry pi clock updates) - Hisilicon (various) - Intel/Altera SoCFPGA (various) - Marvell Armada 7xxx/8xxx (smmu) - Marvell MMP (GPU on mmp2/mmp3) - Mediatek mt8183 (USB, pericfg) - NXP Layerscape (VPU, thermal, DSPI) - NXP i.MX (VPU, bindings, board updates) - Nvidia Tegra194 (GPU) - Qualcomm (GPU, Interconnect, ...) - Renesas R-Car (SPI, IPMMU, board updates) - STMicroelectronics STM32 (various) - Samsung Exynos (various) - Socionext Uniphier (updates to serial, and pcie) - TI K3 (serdes, usb3, audio, sd, chipid) - TI OMAP (IPU/DSP remoteproc changes, dropping platform data)" * tag 'arm-dt-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (605 commits) arm64: dts: meson: odroid-n2: add jack audio output support arm64: dts: meson: odroid-n2: enable audio loopback ARM: dts: berlin: Align L2 cache-controller nodename with dtschema arm64: dts: qcom: Add Microsoft Lumia 950 (Talkman) device tree arm64: dts: qcom: Add Xiaomi Libra (Mi 4C) device tree arm64: dts: qcom: msm8992: Add RPMCC node arm64: dts: qcom: msm8992: Add PSCI support. arm64: dts: qcom: msm8992: Add PMU node arm64: dts: qcom: msm8992: Add BLSP2_UART2 and I2C nodes arm64: dts: qcom: msm8992: Add SPMI PMIC arbiter device arm64: dts: qcom: msm8992: Add a SCM node arm64: dts: qcom: msm8992: Add a proper CPU map arm64: dts: qcom: bullhead: Move UART pinctrl to SoC arm64: dts: qcom: bullhead: Add qcom,msm-id arm64: dts: qcom: msm8992: Fix SDHCI1 arm64: dts: qcom: msm8992: Modernize the DTS style arm64: dts: qcom: Add support for Sony Xperia Z5 (SoMC Sumire-RoW) arm64: dts: qcom: Move msm8994-smd-rpm contents to lg-bullhead. arm64: dts: qcom: msm8994: Add support for SMD RPM arm64: dts: qcom: msm8992: Add a label to rpm-requests ...
2020-07-19arm: dts: socfpga: add reset-names to spi nodeDinh Nguyen1-0/+2
Add reset-names = "spi" to spi dts nodes. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2020-07-15ARM: dts: socfpga: Align L2 cache-controller nodename with dtschemaKrzysztof Kozlowski1-1/+1
Fix dtschema validator warnings like: l2-cache@fffff000: $nodename:0: 'l2-cache@fffff000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' Fixes: 475dc86d08de ("arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC") Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2020-03-20ARM: socfpga: arria10: Add ptp_ref clock to ethernet nodesDalon Westergreen1-6/+6
The ptp_ref clock for Arria10 defaults to using the peripheral pll emac ptp clock. Without the ptp_ref clock in the gmac nodes the driver defaults to the gmac main clock resulting in an incorrect period for the ptp counter. Signed-off-by: Dalon Westergreen <dalon.westergreen@linux.intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-07-30ARM: dts: socfpga: update to new Denali NAND bindingMasahiro Yamada1-1/+1
With commit d8e8fd0ebf8b ("mtd: rawnand: denali: decouple controller and NAND chips"), the Denali NAND controller driver migrated to the new controller/chip representation. Update DT for it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-07-30ARM: dts: socfpga: add reset properties for DMADinh Nguyen1-0/+2
Add both the reset and reset-ocp properties for the DMA node on Arria10. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-07-30ARM: dts: socfpga: add the QSPI OCP reset property on arria10Dinh Nguyen1-1/+2
The QSPI module needs the OCP reset bit deasserted as well. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-06-10ARM: dts: arria10: Add EMAC OCP reset propertyDinh Nguyen1-5/+6
Add the EMAC's OCP reset property on Arria10. The OCP reset bits are also needed to correctly bring the EMACs out of reset correctly. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-06-07ARM: dts: socfpga: use the "altr,socfpga-stmmac-a10-s10" bindingDinh Nguyen1-5/+5
Because of register and bits difference for setting PHY modes, PTP reference clock, and FPGA signalling, the Arria10 SoC needs to use the "altr,socfpga-stmmac-a10-s10" binding to set the correct modes. On Arria10, each EMAC has its own register for PHY modes, and they all have the same offset, thus we can use the 2nd parameter to specify the offsets for the FPGA signal bits. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-01-15ARM: dts: socfpga: update missing reset property peripheralsDinh Nguyen1-0/+18
Add reset property for gpio, i2c, sdmmc, nand, qspi, spi, uart, and watchdog on base socfpga and socfpga_arria10. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-11-28arm: dts: socfpga: remove dma-mask propertyDinh Nguyen1-1/+0
The dma-mask property has been removed from the NAND driver. Remove the property from the DTS files. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-11-28arm: dts: socfpga*.dts*: use SPDX-License-IdentifierSimon Goldschmidt1-12/+1
Follow the recent trend for the license description. This is also in an effort to fully sync the devicetrees with U-Boot. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-09-27ARM: dts: socfpga: Fix SDRAM node address for Arria10Thor Thayer1-1/+1
The address in the SDRAM node was incorrect. Fix this to agree with the correct address and to match the reg definition block. Cc: stable@vger.kernel.org Fixes: 54b4a8f57848b("arm: socfpga: dts: Add Arria10 SDRAM EDAC DTS support") Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-09-17ARM: dts: socfpga: add timer resets for SoCFPGA platformDinh Nguyen1-0/+8
Add the resets property for all the timers on the Cyclone5/Arria5/Arria10 platforms. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-08-30ARM: dts: arria10: update NAND clockingDinh Nguyen1-2/+18
The NAND IP needs 3 clocks(nand_x_clk, nand_clk, and nand_ecc_clk). This patch adds a nand_clk, which is derived from the nand_x_clk, but has a fixed divider of 4, and the nand_ecc_clk, which is derived from the nand_x_clk. Update the NAND node to use the additional clocks. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v2: add nand_ecc_clk and update commit message
2018-08-30ARM: dts: socfpga: set timer interrupt to edge sensitiveSilvan Murer1-1/+1
Change timer interrupt to edge sensitive. Signed-off-by: Silvan Murer <silvan.murer@gmail.com> Reviewed-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-07-02ARM: dts: Add SPI0 node for Arria10Thor Thayer1-0/+12
Add the SPI0 node for Arria10. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-06-26ARM: dts: Fix SPI node for Arria10Thor Thayer1-2/+1
Remove the unused bus-num node and change num-chipselect to num-cs to match SPI bindings. Cc: stable@vger.kernel.org Fixes: f2d6f8f817814 ("ARM: dts: socfpga: Add SPI Master1 for Arria10 SR chip") Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2018-05-14ARM: dts: socfpga: Fix NAND controller node compatible for Arria10Dinh Nguyen1-1/+1
The NAND compatible "denali,denal-nand-dt" property has never been used and is obsolete. Remove it. Cc: stable@vger.kernel.org Fixes: f549af06e9b6("ARM: dts: socfpga: Add NAND device tree for Arria10") Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-07ARM: dts: socfpga: Do not include skeleton.dtsiFlorian Vaussard1-1/+0
The skeleton.dtsi file is now deprecated as noted in commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"). The SoCFPGA device trees already contain the nodes that are defined in skeleton.dtsi (#address-cells, #size-cells, chosen, aliases, memory). Including skeleton.dtsi is useless and will produce the following warning when compiled with W=1: Node /memory has a reg or ranges property, but no unit name Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-07ARM: dts: socfpga: Remove unneeded unit namesFlorian Vaussard1-2/+2
Node eccmgr has a unit name, but do not have a reg property as only the child nodes do have this property. Likewise the usbphy node do not have a reg property. This will trigger the following warnings when compiled with W=1: Node /soc/eccmgr@ffd08140 has a unit name, but no reg property Node /soc/usbphy@0 has a unit name, but no reg property Remove the superfluous unit names. Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-07ARM: dts: socfpga: Add unit name to clock nodesFlorian Vaussard1-23/+23
Most clock nodes in Arria5, Cyclone5 and Arria10 have a reg property but does not have a unit name. This will trigger several warnings like this one (when compiled with W=1): Node /soc/clkmgr@ffd04000/clocks/periph_pll has a reg or ranges property, but no unit name Add the corresponding unit name to each node. Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-02-03ARM: dts: Add EMAC AXI settings for Arria10Thor Thayer1-0/+9
Add the device tree entries needed to support the EMAC AXI bus settings on the Arria10 SoCFPGA chip. Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-01-06ARM: dts: socfpga: add missing compatible string for SDRAM controllerDinh Nguyen1-1/+1
Add "altr,sdr-ctl" to the SDRAM controller node. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-01-06ARM: dts: socfpga: add fpga region support on Arria10Dinh Nguyen1-0/+8
Add the base FPGA region for DT overlay support in FPGA programming. Signed-off-by: Alan Tull <atull@opensource.altera.com> Signed-off-by: Matthew Gerlach <mgerlach@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-01-05ARM: dts: socfpga: Add NAND device tree for Arria10Graham Moore1-0/+13
Add socfpga_arria10_socdk_nand.dts board file for supporting NAND. Signed-off-by: Graham Moore <grmoore@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v2: move nand dts node to socfpga_arria10.dtsi
2017-01-05ARM: dts: socfpga: add fpga-manager node for Arria10Dinh Nguyen1-0/+9
Add the FPGA manger DTS entry for Arria10. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2016-11-09ARM: dts: socfpga: Add QSPI node for the Arria10Dinh Nguyen1-0/+14
Add the QSPI device node for Arria10 SOC. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-19ARM: dts: socfpga: Add SPI Master1 for Arria10 SR chipThor Thayer1-0/+15
Add the Altera Arria10 SPI Master Node in preparation for the A10SR MFD node. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-18ARM: dts: socfpga: enable arm,shared-override in the pl310Dinh Nguyen1-0/+3
Enable the bit(22) shared-override bit for the SoCFPGA family. While at it, enable the prefetch-data and prefetch-instr settings for the Arria10. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-08-08ARM: dts: Add Arria10 USB EDAC devicetree entryThor Thayer1-0/+8
Add the device tree entries needed to support the Altera USB FIFO buffer EDAC on the Arria10 chip. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/1468512408-5156-11-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov <bp@suse.de>
2016-08-08ARM: dts: Add Arria10 DMA EDAC devicetree entryThor Thayer1-0/+8
Add the device tree entries needed to support the Altera DMA FIFO buffer EDAC on the Arria10 chip. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/1468512408-5156-10-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov <bp@suse.de>
2016-08-02Merge tag 'armsoc-dt' of ↵Linus Torvalds1-11/+13
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "Device tree contents continue to be the largest branches we submit. This time around, some of the contents worth pointing out is: New SoC platforms: - Freescale i.MX 7Solo - Broadcom BCM23550 - Cirrus Logic EP7209 and EP7211 (clps711x platforms)_ - Hisilicon HI3519 - Renesas R8A7792 Some of the other delta that is sticking out, line-count wise: - Exynos moves of IP blocks under an SoC bus, which causes a large delta due to indentation changes - a new Tegra K1 board: Apalis - a bunch of small updates to many Allwinner platforms; new hardware support, some cleanup, etc" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (426 commits) ARM: dts: sun8i: Add dts file for inet86dz board ARM: dts: sun8i: Add dts file for Polaroid MID2407PXE03 tablet ARM: dts: sun8i: Use sun8i-reference-design-tablet for ga10h dts ARM: dts: sun8i: Use sun8i-reference-design-tablet for polaroid mid2809pxe04 ARM: dts: sun8i: reference-design-tablet: Add drivevbus-supply ARM: dts: Copy sun8i-q8-common.dtsi sun8i-reference-design-tablet.dtsi ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for utoo p66 dts ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for dit4350 dts ARM: dts: sun5i: reference-design-tablet: Remove mention of q8 ARM: dts: sun5i: reference-design-tablet: Set lradc vref to avcc ARM: dts: sun5i: Rename sun5i-q8-common.dtsi sun5i-reference-design-tablet.dtsi ARM: dts: sun5i: Move q8 display bits to sun5i-a13-q8-tablet.dts ARM: dts: sunxi: Rename sunxi-q8-common.dtsi sunxi-reference-design-tablet.dtsi ARM: dts: at91: Don't build unnecessary dtbs ARM: dts: at91: sama5d3x: separate motherboard gmac and emac definitions ARM: dts: at91: at91sam9g25ek: fix isi endpoint node ARM: dts: at91: move isi definition to at91sam9g25ek ARM: dts: at91: fix i2c-gpio node name ARM: dts: at91: vinco: fix regulator name ARM: dts: at91: ariag25 : fix onewire node ...
2016-06-27ARM: dts: Add Arria10 Ethernet EDAC devicetree entryThor Thayer1-0/+16
Add the device tree entries needed to support the Altera Ethernet FIFO buffer EDAC on the Arria10 chip. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/1466603939-7526-9-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov <bp@suse.de>
2016-06-08ARM: dts: socfpga: fix definitions of serial consoleMatthew Gerlach1-5/+0
The notion of which uart instance is serial0 or serial1 is board specific rather than generic to the chip. This patch removes the serial aliases from generic chip dtsi and adds an appropriate alias to the board specific dtsi. By making the alias for serial0 point to uart1 for the arria10_socdk, the linux boot command line supports specifying console=ttyS0,115200 for backwards compatibility, and it supports not specifying the console at all. Signed-off-by: Matthew Gerlach <mgerlach@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-06-03ARM: dts: Move Arria10 SDRAM as child of ECC ManagerThor Thayer1-6/+7
Changes to support ECC Manager as SDRAM IRQ parent by 1) updating IRQ property values to correct child IRQs 2) moving node under ECC Manager. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-06-03ARM: dts: Arria10 ECC Manager IRQ controller changesThor Thayer1-0/+6
Changes to support IRQ controller implementation including adding new property irq-controller to eccmgr and adding IRQ property to children. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-04-11ARM: dts: socfpga: add reset control for USBDinh Nguyen1-0/+4
Add the resets property for the 2 USB controllers. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-04-11ARM: dts: socfpga: Add Altera Arria10 OCRAM EDAC devicetree entryThor Thayer1-0/+5
Add the device tree entries needed to support the Altera On-Chip RAM EDAC on the Arria10 chip. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-04-11ARM: dts: socfpga: Add Altera Arria10 L2 Cache EDAC devicetree entryThor Thayer1-0/+15
Add the device tree entries needed to support the Altera L2 cache EDAC on the Arria10 chip. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-04-11ARM: dts: socfpga: Add missing clock and interrupt fields for Arria10 DMAGraham Moore1-1/+4
The PL330 DMA driver will not load on Arria10 without devicetree entries for clocks and clock_names. This patch adds those entries. It also adds the ninth interrupt, which is required for error detection. Signed-off-by: Graham Moore <grmoore@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-04-11ARM: dts: socfpga: add the clk-phase property for sd/mmc clockDinh Nguyen1-1/+2
The CIU clock for the SD/MMC should be the sdmmc_clk and not the sdmmc_free_clk. Also, add the correct phase shift the sdmmc_clk. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-03-13ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus"Masahiro Yamada1-1/+1
The compatible string "simple-bus" is well defined in ePAPR, while I see no documentation for the "arm,amba-bus" arnywhere in ePAPR or Documentation/devicetree/. DT is also used by other projects than Linux kernel. It is not a good idea to rely on such an unofficial binding. This commit - replaces "arm,amba-bus" with "simple-bus" - drops "arm,amba-bus" where it is used along with "simple-bus" Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2015-10-06ARM: socfpga: dts: add clock fields for I2C, UART and USB on Arria10Dinh Nguyen1-0/+8
Add the required clock fields for all the I2C nodes. Also add missing clock fields for UART0 and USB1. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-13Merge tag 'socfpga_dts_for_v4.3_part_2' of ↵Olof Johansson1-0/+6
git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt SoCFPGA DTS updates for v4.3, take 2 - Add DTS property "altr,modrst-offset" for reset driver to use - Add updated reset defines for the reset driver - Add reset property for EMACs on Arria10 * tag 'socfpga_dts_for_v4.3_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: socfpga: dts: Add resets for EMACs on Arria10 ARM: socfpga: dts: add "altr,modrst-offset" property dt-bindings: Add reset manager offsets for Arria10 Signed-off-by: Olof Johansson <olof@lixom.net>
2015-08-10ARM: socfpga: dts: Add resets for EMACs on Arria10Dinh Nguyen1-0/+5
Add the reset property for the EMAC controllers on Arria10. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-10ARM: socfpga: dts: add "altr,modrst-offset" propertyDinh Nguyen1-0/+1
The "altr,modrst-offset" property represents the offset into the reset manager that is the first register to be used by the driver to bring peripherals out of reset. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-07-20ARM: dts: socfpga: use stdout-path for chosen nodeDinh Nguyen1-0/+5
Use stdout-path dts property for kernel console. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-24 16:44:25 +0300