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path: root/arch/arm/boot/dts/socfpga_arria10.dtsi
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2023-01-23ARM: dts: socfpga: align UART node name with bindingsKrzysztof Kozlowski1-2/+2
2022-11-18arm: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc nodeDinh Nguyen1-0/+1
2022-11-18arm: dts: socfpga: remove "clk-phase" in sdmmc_clkDinh Nguyen1-1/+0
2022-11-18arm: dts: socfpga: align mmc node names with dtschemaDinh Nguyen1-1/+1
2022-06-14ARM: dts: socfpga: Move sdmmc-ecc node to Arria 10 dtsPaweł Anikiel1-0/+10
2022-05-04ARM: dts: socfpga: drop useless 'dma-channels/requests' propertiesKrzysztof Kozlowski1-2/+0
2022-04-07ARM: dts: socfpga: align interrupt controller node name with dtschemaKrzysztof Kozlowski1-1/+1
2021-12-27ARM: dts: socfpga: change qspi to "intel,socfpga-qspi"Dinh Nguyen1-1/+1
2021-01-07ARM: dts: arria10: add PMU nodeDinh Nguyen1-2/+11
2020-08-17ARM: dts: socfpga: fix register entry for timer3 on Arria10Dinh Nguyen1-1/+1
2020-08-04Merge tag 'arm-dt-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-0/+2
2020-07-19arm: dts: socfpga: add reset-names to spi nodeDinh Nguyen1-0/+2
2020-07-15ARM: dts: socfpga: Align L2 cache-controller nodename with dtschemaKrzysztof Kozlowski1-1/+1
2020-03-20ARM: socfpga: arria10: Add ptp_ref clock to ethernet nodesDalon Westergreen1-6/+6
2019-07-30ARM: dts: socfpga: update to new Denali NAND bindingMasahiro Yamada1-1/+1
2019-07-30ARM: dts: socfpga: add reset properties for DMADinh Nguyen1-0/+2
2019-07-30ARM: dts: socfpga: add the QSPI OCP reset property on arria10Dinh Nguyen1-1/+2
2019-06-10ARM: dts: arria10: Add EMAC OCP reset propertyDinh Nguyen1-5/+6
2019-06-07ARM: dts: socfpga: use the "altr,socfpga-stmmac-a10-s10" bindingDinh Nguyen1-5/+5
2019-01-15ARM: dts: socfpga: update missing reset property peripheralsDinh Nguyen1-0/+18
2018-11-28arm: dts: socfpga: remove dma-mask propertyDinh Nguyen1-1/+0
2018-11-28arm: dts: socfpga*.dts*: use SPDX-License-IdentifierSimon Goldschmidt1-12/+1
2018-09-27ARM: dts: socfpga: Fix SDRAM node address for Arria10Thor Thayer1-1/+1
2018-09-17ARM: dts: socfpga: add timer resets for SoCFPGA platformDinh Nguyen1-0/+8
2018-08-30ARM: dts: arria10: update NAND clockingDinh Nguyen1-2/+18
2018-08-30ARM: dts: socfpga: set timer interrupt to edge sensitiveSilvan Murer1-1/+1
2018-07-02ARM: dts: Add SPI0 node for Arria10Thor Thayer1-0/+12
2018-06-26ARM: dts: Fix SPI node for Arria10Thor Thayer1-2/+1
2018-05-14ARM: dts: socfpga: Fix NAND controller node compatible for Arria10Dinh Nguyen1-1/+1
2017-03-07ARM: dts: socfpga: Do not include skeleton.dtsiFlorian Vaussard1-1/+0
2017-03-07ARM: dts: socfpga: Remove unneeded unit namesFlorian Vaussard1-2/+2
2017-03-07ARM: dts: socfpga: Add unit name to clock nodesFlorian Vaussard1-23/+23
2017-02-03ARM: dts: Add EMAC AXI settings for Arria10Thor Thayer1-0/+9
2017-01-06ARM: dts: socfpga: add missing compatible string for SDRAM controllerDinh Nguyen1-1/+1
2017-01-06ARM: dts: socfpga: add fpga region support on Arria10Dinh Nguyen1-0/+8
2017-01-05ARM: dts: socfpga: Add NAND device tree for Arria10Graham Moore1-0/+13
2017-01-05ARM: dts: socfpga: add fpga-manager node for Arria10Dinh Nguyen1-0/+9
2016-11-09ARM: dts: socfpga: Add QSPI node for the Arria10Dinh Nguyen1-0/+14
2016-10-19ARM: dts: socfpga: Add SPI Master1 for Arria10 SR chipThor Thayer1-0/+15
2016-10-18ARM: dts: socfpga: enable arm,shared-override in the pl310Dinh Nguyen1-0/+3
2016-08-08ARM: dts: Add Arria10 USB EDAC devicetree entryThor Thayer1-0/+8
2016-08-08ARM: dts: Add Arria10 DMA EDAC devicetree entryThor Thayer1-0/+8
2016-08-02Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/ar...Linus Torvalds1-11/+13
2016-06-27ARM: dts: Add Arria10 Ethernet EDAC devicetree entryThor Thayer1-0/+16
2016-06-08ARM: dts: socfpga: fix definitions of serial consoleMatthew Gerlach1-5/+0
2016-06-03ARM: dts: Move Arria10 SDRAM as child of ECC ManagerThor Thayer1-6/+7
2016-06-03ARM: dts: Arria10 ECC Manager IRQ controller changesThor Thayer1-0/+6
2016-04-11ARM: dts: socfpga: add reset control for USBDinh Nguyen1-0/+4
2016-04-11ARM: dts: socfpga: Add Altera Arria10 OCRAM EDAC devicetree entryThor Thayer1-0/+5
2016-04-11ARM: dts: socfpga: Add Altera Arria10 L2 Cache EDAC devicetree entryThor Thayer1-0/+15
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