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path: root/arch/arm/boot/dts/socfpga_arria10.dtsi
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2018-09-27ARM: dts: socfpga: Fix SDRAM node address for Arria10Thor Thayer1-1/+1
2018-09-17ARM: dts: socfpga: add timer resets for SoCFPGA platformDinh Nguyen1-0/+8
2018-08-30ARM: dts: arria10: update NAND clockingDinh Nguyen1-2/+18
2018-08-30ARM: dts: socfpga: set timer interrupt to edge sensitiveSilvan Murer1-1/+1
2018-07-02ARM: dts: Add SPI0 node for Arria10Thor Thayer1-0/+12
2018-06-26ARM: dts: Fix SPI node for Arria10Thor Thayer1-2/+1
2018-05-14ARM: dts: socfpga: Fix NAND controller node compatible for Arria10Dinh Nguyen1-1/+1
2017-03-07ARM: dts: socfpga: Do not include skeleton.dtsiFlorian Vaussard1-1/+0
2017-03-07ARM: dts: socfpga: Remove unneeded unit namesFlorian Vaussard1-2/+2
2017-03-07ARM: dts: socfpga: Add unit name to clock nodesFlorian Vaussard1-23/+23
2017-02-03ARM: dts: Add EMAC AXI settings for Arria10Thor Thayer1-0/+9
2017-01-06ARM: dts: socfpga: add missing compatible string for SDRAM controllerDinh Nguyen1-1/+1
2017-01-06ARM: dts: socfpga: add fpga region support on Arria10Dinh Nguyen1-0/+8
2017-01-05ARM: dts: socfpga: Add NAND device tree for Arria10Graham Moore1-0/+13
2017-01-05ARM: dts: socfpga: add fpga-manager node for Arria10Dinh Nguyen1-0/+9
2016-11-09ARM: dts: socfpga: Add QSPI node for the Arria10Dinh Nguyen1-0/+14
2016-10-19ARM: dts: socfpga: Add SPI Master1 for Arria10 SR chipThor Thayer1-0/+15
2016-10-18ARM: dts: socfpga: enable arm,shared-override in the pl310Dinh Nguyen1-0/+3
2016-08-08ARM: dts: Add Arria10 USB EDAC devicetree entryThor Thayer1-0/+8
2016-08-08ARM: dts: Add Arria10 DMA EDAC devicetree entryThor Thayer1-0/+8
2016-08-02Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/ar...Linus Torvalds1-11/+13
2016-06-27ARM: dts: Add Arria10 Ethernet EDAC devicetree entryThor Thayer1-0/+16
2016-06-08ARM: dts: socfpga: fix definitions of serial consoleMatthew Gerlach1-5/+0
2016-06-03ARM: dts: Move Arria10 SDRAM as child of ECC ManagerThor Thayer1-6/+7
2016-06-03ARM: dts: Arria10 ECC Manager IRQ controller changesThor Thayer1-0/+6
2016-04-11ARM: dts: socfpga: add reset control for USBDinh Nguyen1-0/+4
2016-04-11ARM: dts: socfpga: Add Altera Arria10 OCRAM EDAC devicetree entryThor Thayer1-0/+5
2016-04-11ARM: dts: socfpga: Add Altera Arria10 L2 Cache EDAC devicetree entryThor Thayer1-0/+15
2016-04-11ARM: dts: socfpga: Add missing clock and interrupt fields for Arria10 DMAGraham Moore1-1/+4
2016-04-11ARM: dts: socfpga: add the clk-phase property for sd/mmc clockDinh Nguyen1-1/+2
2016-03-13ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus"Masahiro Yamada1-1/+1
2015-10-06ARM: socfpga: dts: add clock fields for I2C, UART and USB on Arria10Dinh Nguyen1-0/+8
2015-08-13Merge tag 'socfpga_dts_for_v4.3_part_2' of git://git.kernel.org/pub/scm/linux...Olof Johansson1-0/+6
2015-08-10ARM: socfpga: dts: Add resets for EMACs on Arria10Dinh Nguyen1-0/+5
2015-08-10ARM: socfpga: dts: add "altr,modrst-offset" propertyDinh Nguyen1-0/+1
2015-07-20ARM: dts: socfpga: use stdout-path for chosen nodeDinh Nguyen1-0/+5
2015-06-26Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/ar...Linus Torvalds1-16/+336
2015-06-24arm: socfpga: dts: Add Arria10 SDRAM EDAC DTS supportThor Thayer1-0/+11
2015-06-11ARM: socfpga: dts: enable ethernet for Arria10 devkitDinh Nguyen1-0/+11
2015-06-11Merge tag 'socfpga_dts_for_v4.2_part_3' of git://git.kernel.org/pub/scm/linux...Kevin Hilman1-0/+6
2015-06-02ARM: socfpga: dts: add enable-method property for cpu nodesDinh Nguyen1-0/+1
2015-06-02ARM: socfpga: dts: add the a9-scu node for arria10Dinh Nguyen1-0/+5
2015-05-11ARM: socfpga: dts: add clocks to the Arria10 platformDinh Nguyen1-4/+305
2015-05-11ARM: socfpga: dts: Add tx-fifo-depth and rx-fifo-depth propertiesVince Bridgers1-0/+4
2015-05-11ARM: socfpga: dts: Add multicast bins and unicast filter entriesVince Bridgers1-0/+6
2015-05-11ARM: socfpga: dts: enable UART1 for the debug uartDinh Nguyen1-12/+0
2015-05-11ARM: socfpga: dts: disable the sdmmc, and uart nodes in the base arria10Dinh Nguyen1-0/+3
2015-05-11ARM: socfpga: dts: add cpu1-start-addr for Arria 10Dinh Nguyen1-0/+1
2014-11-21arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOCDinh Nguyen1-0/+374
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