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starfive-tech/linux.git
JH7100_VisionFive_OH_dev
JH7110_VisionFive2_510_devel
JH7110_VisionFive2_6.1.y_devel
JH7110_VisionFive2_6.6.y_devel
JH7110_VisionFive2_devel
JH7110_VisionFive2_upstream
beaglev-5.13.y
beaglev_fedora_devel
buildroot-upstream
esmil_starlight
fedora-vic-7100_5.10.6
master
openwrt-6.1.y
rt-ethercat-release
rt-linux-6.6.y-release
rt-linux-release
rtthread_AMP
starfive-5.13
starfive-5.15-dubhe
starfive-6.1-dubhe
starfive-6.1.65-dubhe
starfive-6.6.10-dubhe
starfive-6.6.31-dubhe
starlight-5.14.y
visionfive
visionfive-5.13.y-devel
visionfive-5.15.y
visionfive-5.15.y-devel
visionfive-5.15.y_fedora_devel
visionfive-5.16.y
visionfive-5.17.y
visionfive-5.18.y
visionfive-5.19.y
visionfive-6.4.y
visionfive_fedora_devel
StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)
Andrey V.Kosteltsev
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path:
root
/
arch
/
arm
/
boot
/
dts
/
socfpga.dtsi
Age
Commit message (
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)
Author
Files
Lines
2014-01-08
ARM: dts: socfpga: add pl330 clock
Steffen Trumtrar
1
-0
/
+2
2014-01-08
ARM: dts: socfpga: update L2 tag and data latency
Dinh Nguyen
1
-0
/
+2
2013-12-04
arm: dts: socfpga: Change some clocks of gate-clk type to perip-clk
Dinh Nguyen
1
-3
/
+4
2013-10-10
ARM: socfpga: dts: fix s2f_* clock name
Steffen Trumtrar
1
-8
/
+8
2013-10-10
ARM: socfpga: dts: cleanup indentation
Steffen Trumtrar
1
-145
/
+145
2013-10-04
arm: socfpga: Add clock for smp_twd timer
Dinh Nguyen
1
-0
/
+1
2013-08-29
dts: Rename DW APB timer compatible strings
Dinh Nguyen
1
-4
/
+4
2013-06-12
ARM: socfpga: dts: Add gate-clock bindings
Dinh Nguyen
1
-0
/
+199
2013-06-12
ARM: socfpga: dts: Add ethernet bindings for SOCFPGA
Dinh Nguyen
1
-2
/
+16
2013-04-15
ARM: socfpga: Add clock entries into device tree
Dinh Nguyen
1
-0
/
+157
2013-03-12
Arm: socfpga: pl330: Add #dma-cells for generic dma binding support
Padmavathi Venna
1
-0
/
+3
2013-02-12
arm: socfpga: Add new device tree source for actual socfpga HW
Dinh Nguyen
1
-12
/
+10
2012-10-26
ARM: socfpga: Enable SMP for socfpga
Dinh Nguyen
1
-0
/
+10
2012-07-19
ARM: socfpga: initial support for Altera's SOCFPGA platform
Dinh Nguyen
1
-0
/
+147