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2022-02-01ARM: dts: qcom: fill missing power-domain-cells for gcc controllersDavid Heidelberg1-0/+1
Add missing #power-domain-cells to the clock controllers. Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220108202719.82424-1-david@ixit.cz
2022-02-01ARM: dts: qcom: ipq4019: fix sleep clockPavel Kubelun1-1/+2
It seems like sleep_clk was copied from ipq806x. Fix ipq40xx sleep_clk to the value QSDK defines. Link: https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-msm/commit/?id=d92ec59973484acc86dd24b67f10f8911b4b4b7d Link: https://patchwork.kernel.org/comment/22721613/ Fixes: bec6ba4cdf2a ("qcom: ipq4019: Add basic board/dts support for IPQ4019 SoC") Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org> (clock-output-names) Signed-off-by: Pavel Kubelun <be.dissent@gmail.com> Signed-off-by: Christian Lamparter <chunkeey@gmail.com> (removed clock rename) Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211220170352.34591-1-chunkeey@gmail.com
2021-11-18ARM: dts: qcom: update USB nodes with new platform specific compatibleDavid Heidelberg1-2/+2
To match dwc3 documentation, add compatible for platform. Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211029103340.26828-2-david@ixit.cz
2021-04-14ARM: dts: qcom: Fix node name for NAND controller nodeManivannan Sadhasivam1-1/+1
Use the common "nand-controller" node name for NAND controller node to fix the `make dtbs_check` validation for Qcom platforms. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210408170457.91409-10-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-25ARM: dts: qcom: ipq4019: add SDHCI VQMMC LDO nodeRobert Marko1-0/+10
Since we now have driver for the SDHCI VQMMC LDO needed for I/0 voltage levels lets introduce the necessary node for it. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Link: https://lore.kernel.org/r/20200907101937.10155-1-robert.marko@sartura.hr Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-22ARM: dts: qcom: ipq4019: add more labelsRobert Marko1-3/+3
Lets add labels to more commonly used nodes for easier modification in board DTS files. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Link: https://lore.kernel.org/r/20200909195640.3127341-2-robert.marko@sartura.hr Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-01-22ARM: dts: qcom: ipq4019: add USB devicetree nodesJohn Crispin1-0/+74
Since we now have driver for the USB PHY, and USB controller is already supported by the DWC3 driver lets add the necessary nodes to DTSI. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20200909163831.1894142-1-robert.marko@sartura.hr Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-06-05Merge tag 'arm-dt-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-0/+1
Pull ARM devicetree updates from Arnd Bergmann: "This is the set of device tree changes, mostly covering new hardware support, with 577 patches touching a little over 500 files. There are five new Arm SoCs supported in this release, all of them for existing SoC families: - Realtek RTD1195, RTD1395 and RTD1619 -- three SoCs used in both NAS devices and Android Set-top-box designs, along with the "Horseradish", "Lion Skin" and "Mjolnir" reference platforms; the Mele X1000 and Xnano X5 set-top-boxes and the Banana Pi BPi-M4 single-board computer. - Renesas RZ/G1H (r8a7742) -- a high-end 32-bit industrial SoC and the iW-RainboW-G21D-Qseven-RZG1H board/SoM - Rockchips RK3326 -- low-end 64-bit SoC along with the Odroid-GO Advance game console Newly added machines on already supported SoCs are: - AMLogic S905D based Smartlabs SML-5442TW TV box - AMLogic S905X3 based ODROID-C4 SBC - AMLogic S922XH based Beelink GT-King Pro TV box - Allwinner A20 based Olimex A20-OLinuXino-LIME-eMMC SBC - Aspeed ast2500 based BMCs in Facebook x86 "Yosemite V2" and YADRO OpenPower P9 "Nicole" - Marvell Kirkwood based Check Point L-50 router - Mediatek MT8173 based Elm/Hana Chromebook laptops - Microchip SAMA5D2 "Industrial Connectivity Platform" reference board - NXP i.MX8m based Beacon i.MX8m-Mini SoM development kit - Octavo OSDMP15x based Linux Automation MC-1 development board - Qualcomm SDM630 based Xiaomi Redmi Note 7 phone - Realtek RTD1295 based Xnano X5 TV Box - STMicroelectronics STM32MP1 based Stinger96 single-board computer and IoT Box - Samsung Exynos4210 based based Samsung Galaxy S2 phone - Socionext Uniphier based Akebi96 SBC - TI Keystone based K2G Evaluation board - TI am5729 based Beaglebone-AI development board Include device descriptions for additional hardware support in existing SoCs and machines based on all major SoC platforms: - AMlogic Meson - Allwinner sunxi - Arm Juno/VFP/Vexpress/Integrator - Broadcom bcm283x/bcm2711 - Hisilicon hi6220 - Marvell EBU - Mediatek MT27xx, MT76xx, MT81xx and MT67xx - Microchip SAMA5D2 - NXP i.MX6/i.MX7/i.MX8 and Layerscape - Nvidia Tegra - Qualcomm Snapdragon - Renesas r8a77961, r8a7791 - Rockchips RK32xx/RK33xx - ST-Ericsson ux500 - STMicroelectronics SMT32 - Samsung Exynos and S5PV210 - Socionext Uniphier - TI OMAP5/DRA7 and Keystone" * tag 'arm-dt-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (564 commits) ARM: dts: keystone: Rename "msmram" node to "sram" arm: dts: mt2712: add uart APDMA to device tree arm64: dts: mt8183: add mmc node arm64: dts: mt2712: add ethernet device node arm64: tegra: Make the RTC a wakeup source on Jetson Nano and TX1 ARM: dts: mmp3: Add the fifth SD HCI ARM: dts: berlin*: Fix up the SDHCI node names ARM: dts: mmp3: Fix USB & USB PHY node names ARM: dts: mmp3: Fix L2 cache controller node name ARM: dts: mmp*: Fix up encoding of the /rtc interrupts property ARM: dts: pxa*: Fix up encoding of the /rtc interrupts property ARM: dts: pxa910: Fix the gpio interrupt cell number ARM: dts: pxa3xx: Fix up encoding of the /gpio interrupts property ARM: dts: pxa168: Fix the gpio interrupt cell number ARM: dts: pxa168: Add missing address/size cells to i2c nodes ARM: dts: dove: Fix interrupt controller node name ARM: dts: kirkwood: Fix interrupt controller node name arm64: dts: Add SC9863A emmc and sd card nodes arm64: dts: Add SC9863A clock nodes arm64: dts: mt6358: add PMIC MT6358 related nodes ...
2020-04-30ARM: dts: qcom: ipq4019: add MDIO nodeRobert Marko1-0/+28
This patch adds the necessary MDIO interface node to the Qualcomm IPQ4019 DTSI. Built-in QCA8337N switch is managed using it, and since we have a driver for it lets add it. Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-04-14ARM: dts: qcom: ipq4019: fix high resolution timerAbhishek Sahu1-0/+1
Cherry-picked from CAF QSDK repo. Original commit message: The kernel is failing in switching the timer for high resolution mode and clock source operates in 10ms resolution. The always-on property needs to be given for timer device tree node to make clock source working in 1ns resolution. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Pavel Kubelun <be.dissent@gmail.com> Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Tested-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Link: https://lore.kernel.org/r/20200403114040.349787-1-robert.marko@sartura.hr Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-02-25ARM: dts: qcom: add gpio-ranges propertyChristian Lamparter1-0/+1
This patch adds the gpio-ranges property to almost all of the Qualcomm ARM platforms that utilize the pinctrl-msm framework. The gpio-ranges property is part of the gpiolib subsystem. As a result, the binding text is available in section "2.1 gpio- and pin-controller interaction" of Documentation/devicetree/bindings/gpio/gpio.txt For more information please see the patch titled: "pinctrl: msm: fix gpio-hog related boot issues" from this series. Reported-by: Sven Eckelmann <sven.eckelmann@openmesh.com> Tested-by: Sven Eckelmann <sven.eckelmann@openmesh.com> [ipq4019] Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Tested-by: Robert Marko <robert.marko@sartura.hr> [ipq4019] Cc: Luka Perkov <luka.perkov@sartura.hr> Signed-off-by: Robert Marko <robert.marko@sartura.hr> Link: https://lore.kernel.org/r/20200108125455.308969-1-robert.marko@sartura.hr Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-29ARM: dts: qcom: Add nodes for SMP boot in IPQ40xxDamir Franusic1-0/+7
Add missing nodes and properties to enable SMP support on IPQ40xx devices. Booting without "saw_l2" node: [ 0.001400] CPU: Testing write buffer coherency: ok [ 0.001856] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 [ 0.060163] Setting up static identity map for 0x80300000 - 0x80300060 [ 0.080140] rcu: Hierarchical SRCU implementation. [ 0.120258] smp: Bringing up secondary CPUs ... [ 0.200540] CPU1: failed to boot: -19 [ 0.280689] CPU2: failed to boot: -19 [ 0.360874] CPU3: failed to boot: -19 [ 0.360966] smp: Brought up 1 node, 1 CPU [ 0.360979] SMP: Total of 1 processors activated (96.00 BogoMIPS). [ 0.360988] CPU: All CPU(s) started in SVC mode. Then, booting with "saw_l2" node present (this patch applied): [ 0.001450] CPU: Testing write buffer coherency: ok [ 0.001904] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 [ 0.060161] Setting up static identity map for 0x80300000 - 0x80300060 [ 0.080137] rcu: Hierarchical SRCU implementation. [ 0.120252] smp: Bringing up secondary CPUs ... [ 0.200958] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001 [ 0.281091] CPU2: thread -1, cpu 2, socket 0, mpidr 80000002 [ 0.361264] CPU3: thread -1, cpu 3, socket 0, mpidr 80000003 [ 0.361430] smp: Brought up 1 node, 4 CPUs [ 0.361460] SMP: Total of 4 processors activated (384.00 BogoMIPS). [ 0.361469] CPU: All CPU(s) started in SVC mode. Signed-off-by: Damir Franusic <damir.franusic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Robert Marko <robert.marko@sartura.hr> Cc: Andy Gross <agross@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-arm-msm@vger.kernel.org Link: https://lore.kernel.org/r/20191121152902.21394-1-damir.franusic@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-10-02ARM: dts: qcom: ipq4019: Add SDHCI controller nodeRobert Marko1-0/+12
IPQ4019 has a built in SD/eMMC controller which is supported by the SDHCI MSM driver, by the "qcom,sdhci-msm-v4" binding. So lets add the appropriate node for it. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 284Thomas Gleixner1-9/+1
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 and only version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 294 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.825281744@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-04-10ARM: dts: qcom: ipq4019: enlarge PCIe BAR rangeChristian Lamparter1-2/+2
David Bauer reported that the VDSL modem (attached via PCIe) on his AVM Fritz!Box 7530 was complaining about not having enough space in the BAR. A closer inspection of the old qcom-ipq40xx.dtsi pulled from the GL-iNet repository listed: | qcom,pcie@80000 { | compatible = "qcom,msm_pcie"; | reg = <0x80000 0x2000>, | <0x99000 0x800>, | <0x40000000 0xf1d>, | <0x40000f20 0xa8>, | <0x40100000 0x1000>, | <0x40200000 0x100000>, | <0x40300000 0xd00000>; | reg-names = "parf", "phy", "dm_core", "elbi", | "conf", "io", "bars"; Matching the reg-names with the listed reg leads to <0xd00000> as the size for the "bars". Cc: stable@vger.kernel.org BugLink: https://www.mail-archive.com/openwrt-devel@lists.openwrt.org/msg45212.html Reported-by: David Bauer <mail@david-bauer.net> Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: Andy Gross <agross@kernel.org>
2019-02-15Merge tag 'qcom-dts-for-5.1-2' of ↵Arnd Bergmann1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into arm/dt Qualcomm Device Tree Changes for v5.1 - Part 2 * Fix MSI IRQ type on IPQ4019 * tag 'qcom-dts-for-5.1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: ARM: dts: qcom: ipq4019: Fix MSI IRQ type Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-15Merge tag 'qcom-dts-for-5.1' of ↵Arnd Bergmann1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into arm/dt Qualcomm Device Tree Changes for v5.1 * Fixup GIC IRQ flags and GSBI state on MSM8660 * Add USB OTG, gpio ranges, and Wifi support on MSM8974 Hammerhead * Remove skeleton.dtsi on IPQ4019 * tag 'qcom-dts-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: ARM: dts: ipq4019: Remove skeleton.dtsi ARM: dts: qcom: msm8974-hammerhead: add USB OTG support ARM: dts: qcom: msm8974: add gpio-ranges ARM: dts: qcom: msm8974-hammerhead: add WiFi support ARM: dts: msm8660: Fix up GIC IRQ flags ARM: dts: msm8660: Mark two GSBI blocks "disabled" Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-07ARM: dts: qcom: ipq4019: Fix MSI IRQ typeNiklas Cassel1-1/+1
The databook clearly states that the MSI IRQ (msi_ctrl_int) is a level triggered interrupt. The msi_ctrl_int will be high for as long as any MSI status bit is set, thus the IRQ type should be set to IRQ_TYPE_LEVEL_HIGH, causing the IRQ handler to keep getting called, as long as any MSI status bit is set. A git grep shows that ipq4019 is the only SoC using snps,dw-pcie that has configured this IRQ incorrectly. Not having the correct IRQ type defined will cause us to lose interrupts, which in turn causes timeouts in the PCIe endpoint drivers. Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2019-01-30ARM: dts: Kill off skeleton{64}.dtsiRob Herring1-1/+7
Remove the usage of skeleton.dtsi in the remaining dts files. It was deprecated since commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"). This will make adding a unit-address to memory nodes easier. The main tricky part to removing skeleton.dtsi is we could end up with no /memory node at all when a bootloader depends on one being present. I hacked up dtc to check for this condition. Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com> Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-01-23ARM: dts: ipq4019: Remove skeleton.dtsiRobert Marko1-1/+3
The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi"). These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future: "Node /memory has a reg or ranges property, but no unit name" The disassembled DTB are almost the same besides an empty chosen node being removed and nodes reordered, so it should not have functional changes. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom: ipq4019: fix space vs tab indenting inside qcom-ipq4019.dtsiJohn Crispin1-38/+38
There are various places inside this dtsi file where 8 spaces where used for indenting instead of tabs. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom: ipq4019: fix PCI rangeMathias Kresin1-1/+1
The PCI range is invalid and PCI attached devices doen't work. Signed-off-by: Mathias Kresin <dev@kresin.me> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom: ipq4019: fix cpu0's qcom,saw2 reg valueChristian Lamparter1-1/+1
while compiling an ipq4019 target, dtc will complain: regulator@b089000 unit address format error, expected "2089000" The saw0 regulator reg value seems to be copied and pasted from qcom-ipq8064.dtsi. This patch fixes the reg value to match that of the unit address which in turn silences the warning. (There is no driver for qcom,saw2 right now. So this went unnoticed) Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom: ipq4019: add cpu operating points for cpufreq supportMatthew McClintock1-28/+26
This adds some operating points for cpu frequeny scaling Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-09-13ARM: dts: qcom: ipq4019: use v2 of the kpss bringup mechanismMatthew McClintock1-8/+17
v1 was the incorrect choice here and sometimes the board would not come up properly. Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-07-22ARM: dts: qcom: Add missing OPP properties for CPUsViresh Kumar1-0/+24
The OPP properties, like "operating-points", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can create an OPP table. Add such missing properties. Fix other missing property (clock latency) as well to make it all work. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-05-25ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsiSricharan R1-1/+1
Add the common parts for the dk04 boards. Reviewed-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-05-25ARM: dts: ipq4019: Change the max opp frequencySricharan R1-1/+1
The max opp frequency is 716MHZ. So update that. Reviewed-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-05-25ARM: dts: ipq4019: Add a few peripheral nodesSricharan R1-11/+145
Now with the driver updates for some peripherals being there, add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available peripheral support. Reviewed-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-05-25ARM: dts: ipq4019: Add a default chosen nodeSricharan R1-1/+1
Add a 'chosen' node to select the serial console. This is needed when bootloaders do not pass the 'console=' bootargs. Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-05-14ARM: dts: ipq4019: Add TZ and SMEM reserved regionsSven Eckelmann1-0/+16
The QSEE (trustzone) is started on IPQ4019 before Linux is started. According to QCA, it is placed in in the the memory region 0x87e80000-0x88000000 and must not be accessed directly. There is an additional memory region 0x87e00000-0x87E80000 smem which which can be used for communication with the TZ. The driver for the latter is not yet ready but it is still not allowed to use this memory region like any other memory region. Not reserving this memory region either leads to kernel crashes, kernel hangs (often during the boot) or bus errors for userspace programs. The latter happens when a program is using a memory region which is mapped to these physical memory regions. [ 571.758058] Unhandled fault: imprecise external abort (0xc06) at 0x01715ff8 [ 571.758099] pgd = cebec000 [ 571.763826] [01715ff8] *pgd=8e7fa835, *pte=87e7f75f, *ppte=87e7fc7f Bus error Signed-off-by: Sven Eckelmann <sven.eckelmann@openmesh.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-08-08ARM: dts: qcom: add and enable both wifi blocks on the IPQ4019Christian Lamparter1-0/+84
This patch adds and enables the device-tree definitions for both qcom,ipq4019-wifi blocks for the IPQ4019. Support for these have been added into the ath10k driver since: commit 280e762e9c72 ("ath10k: enable ipq4019 device probe in ahb module") The binding documentation was added in: commit a47aaa69de88 ("dt: bindings: add new dt entry for pre calibration in qcom, ath10k.txt") This has been tested on an ASUS RT-AC58U (IPQ4019), an AVM Fritz!Box 4040 (IPQ4018), a Compex WPJ428 (IPQ4028) and a Cisco Meraki MR33 (IPQ4029). | a000000.wifi: qca4019 hw1.0 target 0x01000000 chip_id 0x003b00ff [...] | a000000.wifi: kconfig debug 0 debugfs 1 tracing 0 dfs 1 testmode 1 | a000000.wifi: firmware ver 10.4-3.4-00082 api 5 features no-p2p,mfp,[...] | a000000.wifi: board_file api 2 bmi_id 0:16 crc32 5773b188 | a000000.wifi: htt-ver 2.2 wmi-op 6 htt-op 4 cal pre-cal-file [...] ... | a800000.wifi: qca4019 hw1.0 target 0x01000000 chip_id 0x003b00ff sub 0000:0000 | a800000.wifi: kconfig debug 0 debugfs 1 tracing 0 dfs 1 testmode 1 | a800000.wifi: firmware ver 10.4-3.4-00082 api 5 features no-p2p, [...] | a800000.wifi: board_file api 2 bmi_id 0:17 crc32 5773b188 | a800000.wifi: htt-ver 2.2 wmi-op 6 htt-op 4 cal pre-cal-file [...] Signed-off-by: Christian Lamparter <chunkeey@googlemail.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-08-08ARM: dts: qcom: add pseudo random number generator on the IPQ4019Christian Lamparter1-0/+8
This architecture has a pseudo random number generator supported by the existing "qcom,prng" binding. rngtest: bits received from input: 5795960032 rngtest: FIPS 140-2 successes: 289591 rngtest: FIPS 140-2 failures: 207 rngtest: FIPS 140-2(2001-10-10) Monobit: 25 rngtest: FIPS 140-2(2001-10-10) Poker: 28 rngtest: FIPS 140-2(2001-10-10) Runs: 91 rngtest: FIPS 140-2(2001-10-10) Long run: 67 rngtest: FIPS 140-2(2001-10-10) Continuous run: 0 rngtest: input channel speed: (min=244; avg=46122; max=3906250)Kibits/s rngtest: FIPS tests speed: (min=1.327; avg=20.966; max=26.345)Mibits/s rngtest: Program run time: 386965827 microseconds Signed-off-by: Christian Lamparter <chunkeey@googlemail.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-08-08ARM: dts: ipq4019: Move xo and timer nodes to SoC dtsiVaradarajan Narayanan1-0/+15
The node for xo and timer belong to the SoC DTS file. Else, new board DT files may not inherit these nodes. Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-08-08ARM: dts: ipq4019: Fix pinctrl node nameVaradarajan Narayanan1-1/+1
This patch fixes the pinctrl node addresses to be the correct format. Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2017-06-06ARM: dts: qcom: ipq4019: fix i2c_0 nodeChristian Lamparter1-2/+2
This patch fixes two typos in the i2c_0 node for the ipq4019. The reg property length is just 0x600. The core clock is GCC_BLSP1_QUP1_I2C_APPS_CLK. GCC_BLSP1_QUP2_I2C_APPS_CLK is used by the second i2c. Fixes: e76b4284b520ba3 ("qcom: ipq4019: add i2c node to ipq4019 SoC and DK01 device tree") Signed-off-by: Christian Lamparter <chunkeey@googlemail.com> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-08-02Merge tag 'armsoc-dt' of ↵Linus Torvalds1-0/+6
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "Device tree contents continue to be the largest branches we submit. This time around, some of the contents worth pointing out is: New SoC platforms: - Freescale i.MX 7Solo - Broadcom BCM23550 - Cirrus Logic EP7209 and EP7211 (clps711x platforms)_ - Hisilicon HI3519 - Renesas R8A7792 Some of the other delta that is sticking out, line-count wise: - Exynos moves of IP blocks under an SoC bus, which causes a large delta due to indentation changes - a new Tegra K1 board: Apalis - a bunch of small updates to many Allwinner platforms; new hardware support, some cleanup, etc" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (426 commits) ARM: dts: sun8i: Add dts file for inet86dz board ARM: dts: sun8i: Add dts file for Polaroid MID2407PXE03 tablet ARM: dts: sun8i: Use sun8i-reference-design-tablet for ga10h dts ARM: dts: sun8i: Use sun8i-reference-design-tablet for polaroid mid2809pxe04 ARM: dts: sun8i: reference-design-tablet: Add drivevbus-supply ARM: dts: Copy sun8i-q8-common.dtsi sun8i-reference-design-tablet.dtsi ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for utoo p66 dts ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for dit4350 dts ARM: dts: sun5i: reference-design-tablet: Remove mention of q8 ARM: dts: sun5i: reference-design-tablet: Set lradc vref to avcc ARM: dts: sun5i: Rename sun5i-q8-common.dtsi sun5i-reference-design-tablet.dtsi ARM: dts: sun5i: Move q8 display bits to sun5i-a13-q8-tablet.dts ARM: dts: sunxi: Rename sunxi-q8-common.dtsi sunxi-reference-design-tablet.dtsi ARM: dts: at91: Don't build unnecessary dtbs ARM: dts: at91: sama5d3x: separate motherboard gmac and emac definitions ARM: dts: at91: at91sam9g25ek: fix isi endpoint node ARM: dts: at91: move isi definition to at91sam9g25ek ARM: dts: at91: fix i2c-gpio node name ARM: dts: at91: vinco: fix regulator name ARM: dts: at91: ariag25 : fix onewire node ...
2016-07-17watchdog: qcom: add option for standalone watchdog not in timer blockMatthew McClintock1-1/+1
Commit 0dfd582e026a ("watchdog: qcom: use timer devicetree binding") moved to use the watchdog as a subset timer register block. Some devices have the watchdog completely standalone with slightly different register offsets as well so let's account for the differences here. The existing "kpss-standalone" compatible string doesn't make it entirely clear exactly what the device is so rename to "kpss-wdt" to reflect watchdog timer functionality. Also update ipq4019 DTS with an SoC specific compatible. Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: Thomas Pedersen <twp@codeaurora.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
2016-06-28dts: ipq4019: support ARMv7 PMUtwp@codeaurora.org1-0/+6
Add support for cortex-a7-pmu present on ipq4019 SoCs. Signed-off-by: Thomas Pedersen <twp@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-04-20qcom: ipq4019: add DMA nodes to ipq4019 SoC and DK01 device treeMatthew McClintock1-0/+15
This adds the blsp_dma node to the device tree and the required properties for using DMA with serial Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-04-20qcom: ipq4019: add crypto nodes to ipq4019 SoC and DK01 device treeMatthew McClintock1-0/+25
This adds the crypto nodes to the ipq4019 device tree, it also adds the BAM node used by crypto as well which the driver currently requires to operate properly The crypto driver itself depends on some other patches to qcom_bam_dma to function properly: https://lkml.org/lkml/2015/12/1/113 CC: Stanimir Varbanov <svarbanov@mm-sol.com> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-04-20qcom: ipq4019: add cpu operating points for cpufreq supportMatthew McClintock1-0/+8
This adds some operating points for cpu frequeny scaling Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-04-20qcom: ipq4019: add i2c node to ipq4019 SoC and DK01 device treeMatthew McClintock1-0/+13
This will allow boards to enable the I2C bus CC: Sricharan R <srichara@qti.qualcomm.com> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-04-20qcom: ipq4019: add spi node to ipq4019 SoC and DK01 device treeMatthew McClintock1-0/+18
This will allow boards to enable the SPI bus Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-04-20qcom: ipq4019: add support for reset via qcom,ps-holdMatthew McClintock1-0/+5
This will allow these types of boards to be rebooted. Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-04-20qcom: ipq4019: add watchdog node to ipq4019 SoC and DK01 device treeMatthew McClintock1-0/+8
This will allow boards to enable watchdog support Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-04-20qcom: ipq4019: add acc and saw nodes to bring up secondary coresMatthew McClintock1-0/+60
This adds the required device tree nodes to bring up the secondary cores on the ipq4019 SoC. Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-04-20qcom: ipq4019: Add basic board/dts support for IPQ4019 SoCMatthew McClintock1-0/+115
Add initial dts files and SoC support for IPQ4019 Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-18 14:07:27 +0300