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The clock controller driver has provided the XTAL clock so far. This
does not match how the hardware actually works because the XTAL clock is
an actual crystal which is mounted on the PCB.
Add the "xtal" clock to meson.dtsi and replace all references to the
clock controller's CLKID_XTAL with the new xtal clock node.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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The VDDEE regulator is basically a copy of the VCCK regulator. VDDEE
supplies for example the Mali GPU and is controlled by PWM_D instead of
PWM_C.
Add the VDDEE PWM regulator and make it the supply of the Mali GPU.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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The snps,reset-gpio bindings are deprecated in favour of the generic
"Ethernet PHY reset" bindings.
Replace snps,reset-gpio from the ðmac node with reset-gpios in the
ethernet-phy node. The old snps,reset-active-low property is now encoded
directly as GPIO flag inside the reset-gpios property.
snps,reset-delays-us is converted to reset-assert-us and
reset-deassert-us. reset-assert-us is the second cell from
snps,reset-delays-us while reset-deassert-us was the third cell.
Instead of blindly copying the old values (which seems strange since
they gave the PHY one second to come out of reset) over this also
updates the delays based on the datasheets:
- RTL8211F PHY on the Odroid-C1 and MXIII-Plus needs a 10ms assert
delay (the datasheet mentions: "For a complete PHY reset, this pin
must be asserted low for at least 10ms") and a 30ms deassert delay
(the datasheet mentions: "Wait for a further 30ms (for internal
circuits settling time) before accessing the PHY register"). The
old settings used 10ms for assert and 1000ms for deassert.
- IP101GR PHY on the EC-100 and MXQ needs a 10ms assert delay (the
datasheet mentions: "Trst | Reset period | 10ms") and a 10ms deassert
delay as well (the datasheet mentions: "Tclk_MII_rdy | MII/RMII clock
output ready after reset released | 10ms")). The old settings used
10ms for assert and 1000ms for deassert.
No functional changes intended.
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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The RTC is always enabled on this board since the battery is already
connected in the factory.
According to the schematics the VCC_RTC regulator (which is either
powered by the internal 3.3V or a battery) is connected to the 0.9V
RTC_VDD input of the SoCs.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Pull ARM SoC device tree updates from Arnd Bergmann:
"This is a smaller update than the past few times, but with just over
500 non-merge changesets still dwarfes the rest of the SoC tree.
Three new SoC platforms get added, each one a follow-up to an existing
product, and added here in combination with a reference platform:
- Renesas RZ/A2M (R7S9210) 32-bit Cortex-A9 Real-time imaging
processor:
https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rza/rza2m.html
- Renesas RZ/G2E (r8a774c0) 64-bit Cortex-A53 SoC "for Rich Graphics
Applications":
https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rzg/rzg2e.html
- NXP i.MX8QuadXPlus 64-bit Cortex-A35 SoC:
https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-8-processors/i.mx-8x-family-arm-cortex-a35-3d-graphics-4k-video-dsp-error-correcting-code-on-ddr:i.MX8X
These are actual commercial products we now support with an in-kernel
device tree source file:
- Bosch Guardian is a product made by Bosch Power Tools GmbH, based
on the Texas Instruments AM335x chip
- Winterland IceBoard is a Texas Instruments AM3874 based machine
used in telescopes at the south pole and elsewhere, see commit
d031773169df2 for some pointers:
- Inspur on5263m5 is an x86 server platform with an Aspeed ast2500
baseboard management controller. This is for running on the BMC.
- Zodiac Digital Tapping Unit, apparently a kind of ethernet switch
used in airplanes.
- Phicomm K3 is a WiFi router based on Broadcom bcm47094
- Methode Electronics uDPU FTTdp distribution point unit
- X96 Max, a generic TV box based on Amlogic G12a (S905X2)
- NVIDIA Shield TV (Darcy) based on Tegra210
And then there are several new SBC, evaluation, development or modular
systems that we add:
- Three new Rockchips rk3399 based boards:
- FriendlyElec NanoPC-T4 and NanoPi M4
- Radxa ROCK Pi 4
- Five new i.MX6 family SoM modules and boards for industrial
products:
- Logic PD i.MX6QD SoM and evaluation baseboad
- Y Soft IOTA Draco/Hydra/Ursa family boards based on i.MX6DL
- Phytec phyCORE i.MX6 UltraLite SoM and evaluation module
- MYIR Tech MYD-LPC4357 development based on the NXP lpc4357
microcontroller
- Chameleon96, an Intel/Altera Cyclone5 based FPGA development system
in 96boards form factor
- Arm Fixed Virtual Platforms(FVP) Base RevC, a purely virtual
platform for corresponding to the latest "fast model"
- Another Raspberry Pi variant: Model 3 A+, supported both in 32-bit
and 64-bit mode.
- Oxalis Evalkit V100 based on NXP Layerscape LS1012a, in 96Boards
enterprise form factor
- Elgin RV1108 R1 development board based on 32-bit Rockchips RV1108
For already supported boards and SoCs, we often add support for new
devices after merging the drivers. This time, the largest changes
include updates for
- STMicroelectronics stm32mp1, which was now formally launched last
week
- Qualcomm Snapdragon 845, a high-end phone and low-end laptop chip
- Action Semi S700
- TI AM654x, their recently merged 64-bit SoC from the OMAP family
- Various Amlogic Meson SoCs
- Mediatek MT2712
- NVIDIA Tegra186 and Tegra210
- The ancient NXP lpc32xx family
- Samsung s5pv210, used in some older mobile phones
Many other chips see smaller updates and bugfixes beyond that"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (506 commits)
ARM: dts: exynos: Fix max voltage for buck8 regulator on Odroid XU3/XU4
dt-bindings: net: ti: deprecate cpsw-phy-sel bindings
ARM: dts: am335x: switch to use phy-gmii-sel
ARM: dts: am4372: switch to use phy-gmii-sel
ARM: dts: dm814x: switch to use phy-gmii-sel
ARM: dts: dra7: switch to use phy-gmii-sel
arch: arm: dts: kirkwood-rd88f6281: Remove disabled marvell,dsa reference
ARM: dts: exynos: Add support for secondary DAI to Odroid XU4
ARM: dts: exynos: Add support for secondary DAI to Odroid XU3
ARM: dts: exynos: Disable ARM PMU on Odroid XU3-lite
ARM: dts: exynos: Add stdout path property to Arndale board
ARM: dts: exynos: Add minimal clkout parameters to Exynos3250 PMU
ARM: dts: exynos: Enable ADC on Odroid HC1
arm64: dts: sprd: Remove wildcard compatible string
arm64: dts: sprd: Add SC27XX fuel gauge device
arm64: dts: sprd: Add SC2731 charger device
arm64: dts: sprd: Add ADC calibration support
arm64: dts: sprd: Remove PMIC INTC irq trigger type
arm64: dts: rockchip: Enable tsadc device on rock960
ARM: dts: rockchip: add chosen node on veyron devices
...
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git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt
ARM: dts: Amlogic updates for v5.1
- more features for Endless EC100 board
- chip temperature sensor support
- fix ethernet pins
- add Mali-450 GPU
* tag 'amlogic-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
ARM: dts: meson8b: ec100: add the GPIO line names
ARM: dts: meson8b: ec100: improve the description of the regulators
ARM: dts: meson8b: ec100: enable the Ethernet PHY interrupt
ARM: dts: meson8m2: mxiii-plus: add iio-hwmon for the chip temperature
ARM: dts: meson8b: odroidc1: add iio-hwmon for the chip temperature
ARM: dts: meson8b: ec100: add iio-hwmon for the chip temperature
ARM: dts: meson8b: add the temperature calibration data for the SAR ADC
ARM: dts: meson8: add the temperature calibration data for the SAR ADC
ARM: dts: meson8m2: use the Meson8m2 specific SAR ADC compatible
ARM: dts: meson: switch the clock controller to the HHI register area
ARM: dts: meson8b: fix the Ethernet data line signals in eth_rgmii_pins
ARM: dts: meson8b: add the Mali-450 MP2 GPU
ARM: dts: meson8: add the Mali-450 MP6 GPU
dt-bindings: gpu: mali-utgard: add Amlogic Meson8 and Meson8b compatible
ARM: dts: meson8b: add the APB bus
ARM: dts: meson8: add the APB bus
ARM: dts: meson6: add the APB2 bus
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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This adds the GPIO line names from the schematics to get them displayed
in the debugfs output of each GPIO controller.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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USB_VBUS is a controlled by a Silergy SY6288CCAC-GP 2A Power
Distribution Switch. The name of it's enable GPIO signal is USB_PWR_EN.
VCC5V is supplied by the main power input called PWR_5V_STB. The name of
it's enable GPIO signal is 3V3_5V_EN.
VCC3V3, VCC_DDR3_1V5 and VCCK (the CPU power supply) each use a separate
Silergy SY8089AAC-GP 2A step down regulator. They are all supplied by the
board's main 5V. VCC3V3 and VCC_DDR3_1V5 are fixed regulators while the
voltage of VCCK can be changed by changing it's feedback voltage via
PWM_C.
VCC1V8 is an ABLIC S-1339D18-M5001-GP fixed voltage regulator which is
supplied by VCC3V3.
VCC_RTC is a Global Mixed-mode Technology Inc. G918T12U-GP LDO which. It
is supplied by either VCC3V3 (when the board is powered) or the RTC coin
cell battery.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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The INTR32 pin of the IP101GR Ethernet PHY is routed to the GPIOH_3 pad
on the SoC.
Enable the interrupt function of the PHY's INTR32 pin to switch it from
it's default "receive error" mode to "interrupt pin" mode.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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SAR ADC enabled channel 8 can be used to measure the chip temperature.
This can be made available to the hwmon subsystem by using iio-hwmon.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Remove the usage of skeleton.dtsi in the remaining dts files. It was
deprecated since commit 9c0da3cc61f1 ("ARM: dts: explicitly mark
skeleton.dtsi as deprecated"). This will make adding a unit-address to
memory nodes easier.
The main tricky part to removing skeleton.dtsi is we could end up with
no /memory node at all when a bootloader depends on one being present. I
hacked up dtc to check for this condition.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Antoine Tenart <antoine.tenart@bootlin.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
Acked-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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After commit 89a5e15bcba87d ("gpio/mmc/of: Respect polarity in the device
tree") SD cards are not detected anymore.
The CD GPIO is "active low" on the EC-100. The MMC dt-bindings specify:
"[...] using the "cd-inverted" property means, that the CD line is active
high, i.e. it is high, when a card is inserted".
Fix the description of the SD card by marking it as GPIO_ACTIVE_LOW and
drop the "cd-inverted" property. This makes the definition consistent
with the existing dt-bindings and fixes the check whether an SD card is
inserted.
Fixes: bbedc1f1d90e33 ("ARM: dts: meson8b: Add support for the Endless Mini (EC-100)")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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The Endless Mini (EC-100) is a grapefruit-sized computer based on the
Amlogic Meson8b (S805) SoC which comes in two variants.
Both variants have in common:
- Amlogic Meson8b (S805) SoC
- two USB 2.0 ports on the rear, one one the front (connected to the SoC
through an internal hub)
- 3.5mm Stereo out and MIC combo port
- HDMI and CVBS output
- 5V power supply (rated at 3A / 15W)
- an internal embedded micro-controller (called "EC") which implements a
"breathing" effect for the LED and allows shutting down (powering off)
the whole device
- 10/100 Mbit/s Ethernet using an IC Plus IP101A/G PHY (note: the website
incorrectly lists a Gigabit Ethernet port)
- the CPU voltage is regulated using a PWM regulator. The GPL sources of
the EC-100 are using a PWM value of 0x1c0000 for 0.86V and a PWM value
of 0x00001c for 1.14V. When using the XTAL (24MHz) as input this
translates into a PWM period of 1148ns with 0.86V using a duty cycle of
100% and 1.14V using a duty cycle of 0%.
The main differences are:
- the main indicator for the variant is the RAM size: the "cheaper"
variant has 1 GB of RAM, while the more expensive one comes with 2GB
- the storage size differs: 24 GB vs 32 GB
- the "1 GB RAM" variant has Ethernet connectivity only, while the "2 GB"
variant has a Realtek RTL8723BS SDIO chip which adds 802.11b/g/n wifi
and Bluetooth 4.0 support
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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