summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/meson8.dtsi
AgeCommit message (Expand)AuthorFilesLines
2019-04-16ARM: dts: meson: add support for the RTCMartin Blumenstingl1-0/+5
2019-03-18ARM: dts: meson8: add the internal clock measurerMartin Blumenstingl1-0/+5
2019-02-11ARM: dts: meson8: add the temperature calibration data for the SAR ADCMartin Blumenstingl1-0/+8
2019-02-11ARM: dts: meson: switch the clock controller to the HHI register areaMartin Blumenstingl1-7/+8
2019-01-11ARM: dts: meson8: add the Mali-450 MP6 GPUMartin Blumenstingl1-0/+58
2019-01-11ARM: dts: meson8: add the APB busMartin Blumenstingl1-0/+8
2018-12-05ARM: dts: meson: meson8: add the CPU OPP tableMartin Blumenstingl1-0/+72
2018-12-05ARM: dts: meson8: add the Cortex-A9 global timerMartin Blumenstingl1-0/+13
2018-12-05ARM: dts: meson8: add the ARM TWD timerMartin Blumenstingl1-0/+7
2018-12-05ARM: dts: meson: group the Cortex-A5 / Cortex-A9 peripheralsMartin Blumenstingl1-5/+7
2018-11-29ARM: dts: meson: add the clock inputs for the Meson timerMartin Blumenstingl1-0/+5
2018-11-29ARM: dts: meson: consistently disable pin biasJerome Brunet1-0/+12
2018-09-05ARM: dts: meson8: fix the clock controller register sizeMartin Blumenstingl1-1/+1
2018-05-11ARM: dts: meson8: add the uart_A pinsMartin Blumenstingl1-0/+16
2018-04-27ARM: dts: meson8: add the cortex-a9-pmu compatible PMUMartin Blumenstingl1-4/+13
2018-02-13ARM: dts: meson8: add the USB reset lineMartin Blumenstingl1-0/+2
2018-02-13ARM: dts: meson8: add the reset controllerMartin Blumenstingl1-0/+7
2017-12-12ARM: dts: meson8: enable the GPIO interrupt controllerMartin Blumenstingl1-0/+5
2017-12-07ARM: dts: meson8: use stable UART bindings with correct gate clockMartin Blumenstingl1-4/+12
2017-12-07ARM: dts: meson: drop "sana" clock from SAR ADCXingyu Chen1-3/+2
2017-12-07ARM: dts: meson8: add more L2 cache settingsMartin Blumenstingl1-0/+3
2017-10-30Merge tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khi...Arnd Bergmann1-1/+1
2017-10-29ARM: dts: meson: add the efuse nodeMartin Blumenstingl1-0/+6
2017-10-29ARM: dts: meson8: add support for booting the secondary CPU coresMartin Blumenstingl1-0/+21
2017-10-12ARM: dts: meson: add the SDIO MMC controllerMartin Blumenstingl1-0/+6
2017-10-12ARM: dts: meson8: remove gpio offsetJerome Brunet1-1/+1
2017-10-07ARM: dts: meson: add SoC information nodesMartin Blumenstingl1-0/+5
2017-08-01ARM: dts: meson: mark the clock controller also as reset controllerMartin Blumenstingl1-0/+1
2017-07-28ARM: dts: meson8: add the PWM controller nodesMartin Blumenstingl1-0/+15
2017-06-16ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8bMartin Blumenstingl1-1/+1
2017-06-16ARM: dts: meson8b: add the SCU device nodeMartin Blumenstingl1-0/+5
2017-06-16ARM: dts: meson: add USB support on Meson8 and Meson8bMartin Blumenstingl1-0/+24
2017-06-16ARM: dts: meson: add the hardware random number generatorMartin Blumenstingl1-0/+6
2017-06-16ARM: dts: meson8: add reserved memory zonesMartin Blumenstingl1-0/+27
2017-06-16ARM: dts: meson: add the SAR ADCMartin Blumenstingl1-0/+8
2017-06-16ARM: dts: meson8: add the pins for the SDIO controllerMartin Blumenstingl1-0/+24
2017-06-16ARM: dts: meson8: add the PWM_E and PWM_F pinsMartin Blumenstingl1-0/+14
2017-06-16ARM: dts: meson: use C preprocessor friendly include syntaxMartin Blumenstingl1-1/+1
2017-06-16ARM: dts: meson8: fix the IR receiver pinsMartin Blumenstingl1-7/+7
2017-06-09ARM: dts: meson8: add and use the real clock controllerMartin Blumenstingl1-16/+16
2017-05-26ARM: dts: meson: Extend L2 cache controller node for Meson8 and Meson8bCarlo Caione1-0/+6
2017-05-26ARM: dts: meson: organize devices in their corresponding bussesMartin Blumenstingl1-38/+78
2017-03-28ARM: dts: meson8: Add gpio-ranges propertiesNeil Armstrong1-0/+2
2016-03-30ARM: dts: amlogic: Split pinctrl device for Meson8 / Meson8bCarlo Caione1-25/+32
2015-03-02ARM: dts: meson8: add pinctrl nodeBeniamino Galvani1-0/+68
2014-11-18ARM: meson: DTS: enable L2 cacheBeniamino Galvani1-0/+4
2014-11-18ARM: dts: add dtsi for Amlogic Meson8 SoCsBeniamino Galvani1-0/+88
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-26 11:59:12 +0300