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2022-11-18ARM: dts: lpc32xx: trim addresses to 8 digitsKrzysztof Kozlowski1-1/+1
Hex numbers in addresses and sizes should be rather eight digits, not nine. Drop leading zeros. No functional change (same DTB). Link: https://lore.kernel.org/r/20221115105049.95313-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2021-02-03ARM: dts: lpc32xx: Revert set default clock rate of HCLK PLLAlexandre Belloni1-3/+0
This reverts commit c17e9377aa81664d94b4f2102559fcf2a01ec8e7. The lpc32xx clock driver is not able to actually change the PLL rate as this would require reparenting ARM_CLK, DDRAM_CLK, PERIPH_CLK to SYSCLK, then stop the PLL, update the register, restart the PLL and wait for the PLL to lock and finally reparent ARM_CLK, DDRAM_CLK, PERIPH_CLK to HCLK PLL. Currently, the HCLK driver simply updates the registers but this has no real effect and all the clock rate calculation end up being wrong. This is especially annoying for the peripheral (e.g. UARTs, I2C, SPI). Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com> Link: https://lore.kernel.org/r/20210203090320.GA3760268@piout.net' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-12-14ARM: dts: lpc32xx: Remove unused and undocumented 'pnx,timeout'Rob Herring1-3/+0
'pnx,timeout' is unused, undocumented and 'pnx' is not a vendor prefix, so let's remove it. Acked-by: Vladimir Zapolskiy <vz@mleia.com> Cc: Sylvain Lemieux <slemieux.tyco@gmail.com> Link: https://lore.kernel.org/r/20201210175238.2721550-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
2019-04-19ARM: dts: lpc32xx: use SPDX license identifierVladimir Zapolskiy1-7/+1
Replace GPLv2+ header with the SPDX identifier. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-19ARM: dts: lpc32xx: add address and size cell values to SPI controller nodesVladimir Zapolskiy1-0/+8
All 4 SPI controllers on NXP LPC32xx SoC support SPI slaves discerning them by one cell address value, set it as default to avoid duplication in board device tree files. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-19ARM: dts: lpc32xx: disable MAC controller by defaultVladimir Zapolskiy1-0/+1
NXP LPC3220 and LPC3230 SoCs do NOT contain a MAC controller, so, since for now there is just one dtsi file for all variants of NXP LPC32xx SoCs, it is reasonable to disable the controller by default and enable it in device tree files of particular boards. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-19ARM: dts: lpc32xx: disable I2S controllers by defaultVladimir Zapolskiy1-0/+2
The I2S controllers found on NXP LPC32xx SoCs are not yet in use by any boards supported in upstream, disable the controllers by default. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-04-19ARM: dts: lpc32xx: change hexadecimal values to lower caseVladimir Zapolskiy1-9/+10
This is a non-functional change, all inconsistent hexadecimal values found in the file are now fixed. Taking a chance to interfere into some non-functional change I add my copyright notice for work done during the last few years. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-02-15Merge tag 'lpc32xx-dt-for-5.1' of ↵Arnd Bergmann1-13/+15
https://github.com/vzapolskiy/linux-lpc32xx into arm/dt ARM: lpc32xx: devicetree updates for v5.1 Here are the changes for ARM NXP LPC32xx and ARM NXP LPC18xx/LPC43xx devicetree files: * added dts file for MYIR Tech MYD-LPC4357 development board, * two missing properties are added to LPC32xx keypad controller device tree node, this fixes a long-standing problem with its initialization, * LPC32xx PL11x LCD controller device node got corrected properties, which allows to use it with a new PL11x DRM driver, * output voltage level on one of Phytec phyCORE-LPC3250 fixed regulators is corrected, the fix is needed to remove duplicating platform data, * Phytec phyCORE-LPC3250 board gets a description of a kit LCD panel, this completes setup of CLCD device tree node for the board, * added unit addresses to memory device nodes on EA and Phytec boards, * fixes of ordinary warnings in dts formatting like leading zeroes, unused address and size cell properties and so on. * tag 'lpc32xx-dt-for-5.1' of https://github.com/vzapolskiy/linux-lpc32xx: ARM: dts: lpc32xx: ea3250: beautify gpio keys children nodes ARM: dts: lpc32xx: ea3250: add unit address to memory device node ARM: dts: lpc32xx: phy3250: add unit address to memory device node ARM: dts: lpc32xx: phy3250: setup LCD controller to panel interface ARM: dts: lpc32xx: phy3250: remove regulators umbrella device node ARM: dts: lpc32xx: phy3250: fix SD card regulator voltage ARM: dts: lpc32xx: fix ARM PrimeCell LCD controller clocks property ARM: dts: lpc32xx: fix ARM PrimeCell LCD controller variant ARM: dts: lpc32xx: reparent keypad controller to SIC1 ARM: dts: lpc32xx: add required clocks property to keypad device node ARM: dts: Add DT for MYIR Tech MYD-LPC4357 Development Board ARM: dts: lpc32xx: Remove leading 0x and 0s from bindings notation ARM: dts: lpc435x: remove address and size cells from gpio-keys-polled nodes Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-03ARM: dts: lpc32xx: fix ARM PrimeCell LCD controller clocks propertyVladimir Zapolskiy1-2/+2
The originally added ARM PrimeCell PL111 clocks property misses the required "clcdclk" clock, which is the same as a clock to enable the LCD controller on NXP LPC3230 and NXP LPC3250 SoCs. Fixes: 93898eb775e5 ("arm: dts: lpc32xx: add clock properties to device nodes") Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-02-03ARM: dts: lpc32xx: fix ARM PrimeCell LCD controller variantVladimir Zapolskiy1-1/+1
ARM PrimeCell PL111 LCD controller is found on On NXP LPC3230 and LPC3250 SoCs variants, the original reference in compatible property to an older one ARM PrimeCell PL110 is invalid. Fixes: e04920d9efcb3 ("ARM: LPC32xx: DTS files for device tree conversion") Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-02-03ARM: dts: lpc32xx: reparent keypad controller to SIC1Vladimir Zapolskiy1-1/+2
After switching to a new interrupt controller scheme by separating SIC1 and SIC2 from MIC interrupt controller just one SoC keypad controller was not taken into account, fix it now: WARNING: CPU: 0 PID: 1 at kernel/irq/irqdomain.c:524 irq_domain_associate+0x50/0x1b0 error: hwirq 0x36 is too large for interrupt-controller@40008000 ... lpc32xx_keys 40050000.key: failed to get platform irq lpc32xx_keys: probe of 40050000.key failed with error -22 Fixes: 9b8ad3fb81ae ("ARM: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC") Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-02-03ARM: dts: lpc32xx: add required clocks property to keypad device nodeVladimir Zapolskiy1-0/+1
NXP LPC32xx keypad controller requires a clock property to be defined. The change fixes the driver initialization problem: lpc32xx_keys 40050000.key: failed to get clock lpc32xx_keys: probe of 40050000.key failed with error -2 Fixes: 93898eb775e5 ("arm: dts: lpc32xx: add clock properties to device nodes") Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-02-03ARM: dts: lpc32xx: Remove leading 0x and 0s from bindings notationMathieu Malaterre1-9/+9
Improve the DTS files by removing all the leading "0x" and zeros to fix the following dtc warnings: Warning (unit_address_format): Node /XXX unit name should not have leading "0x" and Warning (unit_address_format): Node /XXX unit name should not have leading 0s Converted using the following command: find . -type f \( -iname *.dts -o -iname *.dtsi \) -exec sed -i -e "s/@\([0-9a-fA-FxX\.;:#]+\)\s*{/@\L\1 {/g" -e "s/@0x\(.*\) {/@\1 {/g" -e "s/@0+\(.*\) {/@\1 {/g" {} + For simplicity, two sed expressions were used to solve each warnings separately. To make the regex expression more robust a few other issues were resolved, namely setting unit-address to lower case, and adding a whitespace before the opening curly brace: https://elinux.org/Device_Tree_Linux#Linux_conventions This will solve as a side effect warning: Warning (simple_bus_reg): Node /XXX@<UPPER> simple-bus unit address format error, expected "<lower>" This is a follow up to commit 4c9847b7375a ("dt-bindings: Remove leading 0x from bindings notation") Reported-by: David Daney <ddaney@caviumnetworks.com> Suggested-by: Rob Herring <robh@kernel.org> Signed-off-by: Mathieu Malaterre <malat@debian.org> [vzapolskiy: fixed commit message to pass checkpatch.pl test] Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2019-01-30ARM: dts: Kill off skeleton{64}.dtsiRob Herring1-2/+2
Remove the usage of skeleton.dtsi in the remaining dts files. It was deprecated since commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"). This will make adding a unit-address to memory nodes easier. The main tricky part to removing skeleton.dtsi is we could end up with no /memory node at all when a bootloader depends on one being present. I hacked up dtc to check for this condition. Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Gregory CLEMENT <gregory.clement@bootlin.com> Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-09-28ARM: dts: lpc32xx: Fix SPI controller node namesRob Herring1-2/+2
SPI controller nodes should be named 'spi' rather than 'ssp'. Fixing the name enables dtc SPI bus checks. Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-10-20arm: dts: fix unit-address leading 0sRob Herring1-1/+1
Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-10-25ARM: dts: lpc32xx: set default parent clock for pwm1 & pwm2Sylvain Lemieux1-0/+4
The change setup the peripheral clock (PERIPH_CLK) as the default parent clock for PWM1 & PWM2. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2016-10-03ARM: dts: lpc32xx: add device node for IRAM on-chip memoryVladimir Zapolskiy1-1/+11
The change adds a new device node with description of generic SRAM on-chip memory found on NXP LPC32xx SoC series and connected to AHB matrix slave port 3. Note that NXP LPC3220 SoC has 128KiB of SRAM memory, the other LPC3230, LPC3240 and LPC3250 SoCs all have 256KiB SRAM space, in the shared DTSI file this change specifies 128KiB SRAM size. Also it's worth to mention that the SRAM area contains of 64KiB banks, 2 banks on LPC3220 and 4 banks on the other SoCs from the series, and all SRAM banks but the first one have independent power controls, the description of this feature will be added with the introduction of power domains for the SoC series. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Cc: Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2016-04-28ARM: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MICVladimir Zapolskiy1-18/+42
The change adds separate device nodes for SIC1 and SIC2 interrupt controllers and reparents all defined SIC1 and SIC2 interrupt producers to the correspondent interrupt controller, this is needed to perform switching to a new LPC32xx MIC/SIC interrupt controller driver. Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2016-04-21ARM: dts: lpc32xx: disabled ssp0/spi1 & ssp1/spi2 by defaultSylvain Lemieux1-0/+12
The SSP0/SPI1 and SSP1/SPI2 shared pinout and should be disable by default. Board specific dts should enable them, as needed. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2016-04-21ARM: dts: lpc32xx: add clock properties to spi nodesSylvain Lemieux1-0/+2
The change adds clock properties to spi peripheral devices, clock ids are taken from dt-bindings/clock/lpc32xx-clock.h Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2016-04-18ARM: dts: lpc32xx: set default clock rate of HCLK PLLVladimir Zapolskiy1-0/+3
Probably most of NXP LPC32xx boards have 13MHz main oscillator and therefore for HCLK PLL and ARM core clock rate default hardware setting is 16 * 13MHz = 208MHz, however a user may vary HCLK PLL/ARM core rate from 156MHz to about 266MHz for 13MHz clock source. The change explicitly defines HCLK PLL output rate to default 208MHz to overwrite any settings done by a bootloader, if needed it can be redefined in a board DTS file. Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2016-02-11arm: dts: lpc32xx: assign interrupt typesVladimir Zapolskiy1-29/+34
LPC32xx interrupt controller has two cells, instead of zero specify proper irq types for all consumers. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2016-02-11arm: dts: lpc32xx: remove clock frequency property from UART device nodesVladimir Zapolskiy1-4/+0
If clock-frequency property is given, then it substitutes calculation of supplying clock frequency from parent clock, this may break UART, if parent clock is given and managed by common clock framework. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2016-02-11arm: dts: lpc32xx: add USB clock controllerVladimir Zapolskiy1-0/+9
The change adds device node of LPC32xx USB clock controller and adds clock properties to USB OHCI, USB device and I2C controller to USB phy device nodes. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2016-02-11arm: dts: lpc32xx: add clock properties to device nodesVladimir Zapolskiy1-0/+41
The change adds clock properties to all described peripheral devices, clock ids are taken from dt-bindings/clock/lpc32xx-clock.h Some existing drivers expect to get clock names, in those cases clock-names are added as well. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2016-02-11arm: dts: lpc32xx: add clock controller device nodeVladimir Zapolskiy1-0/+17
NXP LPC32xx SoC has a clocking and power control unit (CPC) as a part of system control block (SCB). CPC is supplied by two external oscillators and it manages core and most of peripheral clocks, the change adds SCB and CPC descriptions to shared LPC32xx dtsi file. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2016-02-11arm: dts: lpc32xx: add device nodes for external oscillatorsVladimir Zapolskiy1-0/+16
NXP LPC32xx SoC has two external oscillators - one is mandatory and always on 32768 Hz oscillator and one optional 10-20MHz oscillator, which is practically always present on LPC32xx boards, because its presence is needed to supply USB controller clock and by default it supplies ARM and most of the peripheral clocks, LPC32xx User's Manual references it as a main oscillator. The change adds device nodes for both oscillators, frequency of the main oscillator is selected to be 13MHz by default, this variant is found on all LPC32xx reference boards. The device nodes for external oscillators are needed to describe input clocks of LPC32xx clock controller. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2015-11-18arm: dts: lpc32xx: move USB controller subdevices into own device nodeVladimir Zapolskiy1-23/+30
NXP LPC32xx SoC has one USB OTG controller, which is supposed to work with an external phy (default is NXP ISP1301). Practically the USB controller contains 5 subdevices: - host controller 0x3102 0000 -- 0x3102 00FF - OTG controller 0x3102 0100 -- 0x3102 01FF - device controller 0x3102 0200 -- 0x3102 02FF - I2C controller 0x3102 0300 -- 0x3102 03FF - clock controller 0x3102 0F00 -- 0x3102 0FFF The USB controller can be considered as a "bus", because the subdevices above are relatively independent, for example I2C controller is the same as other two general purpose I2C controllers found on SoC. The change is not intended to modify any logic, but it rearranges existing device nodes, in future it is planned to add a USB clock controller device node into the same group. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2015-11-18arm: dts: lpc32xx: add device nodes for standard timersVladimir Zapolskiy1-0/+40
NXP LPC32xx SoCs have 6 standard timers, add device nodes to describe them. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2015-11-18arm: dts: lpc32xx: add external memory controller device nodeVladimir Zapolskiy1-1/+15
The change adds a description of ARM PrimeCell PL175 memory controller, which is found on NXP LPC32xx SoCs. The controller supports up to 4 static memory devices mapped to 0xE000 0000 - 0xE3FF FFFF physical memory area. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2015-11-18arm: dts: lpc32xx: add device node for the second pwm controllerVladimir Zapolskiy1-2/+8
LPC32xx SoCs have two independent PWM controllers, they have different clock parents, clock gates and even slightly different controls, each of these two PWM controllers has one output channel. Due to almost similar controls arranged in a row it is incorrectly assumed that there is one PWM controller with two channels, fix this problem in lpc32xx.dtsi, which at the moment prevents separate configuration of different clock parents and gates for both PWM controllers. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2015-11-18arm: dts: lpc32xx: add reg property to cpu device nodeVladimir Zapolskiy1-2/+3
According to device tree bindings for ARM cpus cpu node must contain a reg property for enumeration scheme. The change adds reg = <0x0> indicating that the processor does not have CPU identification register and updates cell settings. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2015-11-18arm: dts: lpc32xx: add labels to all defined peripheral nodesVladimir Zapolskiy1-10/+10
To simplify writing of dts files for all lpc32xx.dtsi users who adjust device node properties, add labels to all defined peripheral device nodes in lpc32xx.dtsi. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2015-11-18arm: dts: lpc32xx: change include syntax to be C preprocessor friendlyVladimir Zapolskiy1-1/+1
The change replaces /include/ to #include in lpc32xx.dtsi and derivatives, it is required, if C preprocessor is intended to be used over dtsi/dts files, otherwise errors like one below are generated: Error: ea3250.dts:15.1-9 syntax error FATAL ERROR: Unable to parse input tree Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2013-05-23ARM: dts: lpc32xx: cpus/cpu nodes dts updatesLorenzo Pieralisi1-2/+6
This patch updates the in-kernel dts files according to the latest cpus and cpu bindings updates for ARM. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2012-11-14ARM: LPC32xx: Add the motor PWM to base dts fileAlban Bedel1-0/+7
Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Signed-off-by: Roland Stigge <stigge@antcom.de>
2012-07-20ARM: LPC32xx: Add PWM to base dts fileAlexandre Pereira da Silva1-0/+5
Signed-off-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com> Signed-off-by: Roland Stigge <stigge@antcom.de>
2012-06-14ARM: LPC32xx: Fix lpc32xx.dtsi status property: "disable" -> "disabled"Roland Stigge1-7/+7
This patches fixes some status = "disable" strings to "disabled", the correct way of disabling nodes in the devicetree. Signed-off-by: Roland Stigge <stigge@antcom.de>
2012-06-14ARM: LPC32xx: High Speed UART configuration via DTRoland Stigge1-5/+11
This patch fixes the DTS files for the High Speed UARTs 1, 2 and 7 of the LPC32xx SoC, adjusting the compatible strings, adding interrupts and status configuration. On the PHY3250 reference board, UART2 is enabled. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
2012-06-14ARM: LPC32xx: DT conversion of Standard UARTsRoland Stigge1-8/+26
This patch switches from static serial driver initialization to devicetree configuration. This way, the Standard UARTs of the LPC32xx SoC can be enabled individually via DT. E.g., instead of Kconfig configuration, the phy3250.dts activates UARTs 3 and 5. Signed-off-by: Roland Stigge <stigge@antcom.de> Tested-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
2012-06-14ARM: LPC32xx: DTS adjustment for using pl18x primecellRoland Stigge1-1/+2
This patch adjusts the dts files to reference the pl18x primecell driver correctly. Signed-off-by: Roland Stigge <stigge@antcom.de>
2012-06-14ARM: LPC32xx: DTS adjustment for key matrix controllerRoland Stigge1-0/+2
This patch connects the lpc32xx-key driver to the LPC32xx platform (via lpc32xx.dtsi), and more specifically to the reference board via its dts file. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
2012-06-14ARM: LPC32xx: Adjust dtsi file for MLC controller configurationRoland Stigge1-2/+3
This patch takes into account that the MTD NAND MLC controller needs more registers, located actually before the previously allocated memory range, already starting at 200a8000 instead of 200b0000. Further, the interrupt for the controller is configured. Signed-off-by: Roland Stigge <stigge@antcom.de> Tested-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
2012-05-31ARM: LPC32xx: Adjust dts files to gpio dt bindingRoland Stigge1-39/+2
The GPIO devicetree binding in 3.5 doesn't register the various LPC32xx GPIO banks via DT subnodes but always all at once, and changes the gpio referencing to 3 cells (bank, gpio, flags). This patch adjusts the DTS files to this binding that was just accepted to the gpio subsystem. Signed-off-by: Roland Stigge <stigge@antcom.de> Signed-off-by: Olof Johansson <olof@lixom.net>
2012-04-22ARM: LPC32xx: DTS files for device tree conversionRoland Stigge1-0/+292
This patch adds the dts files for the reference machine of LPC32xx: * arch/arm/boot/dts/lpc32xx.dtsi: Include for devices based on LPC32xx * arch/arm/boot/dts/phy3250.dts: Board support for PHYTEC phyCORE-LPC3250 Signed-off-by: Roland Stigge <stigge@antcom.de>
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