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2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner1-12/+1
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-07-03arm: dts: highbank: Add missing OPP properties for CPUsViresh Kumar1-0/+30
The OPP properties, like "operating-points", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can create an OPP table. Add such missing properties. Fix other missing property (clock latency) as well to make it all work. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-11-05ARM: dts: calxeda: move memory-controller node out of ecx-common.dtsiRob Herring1-0/+6
The DDR controller is slightly different in ECX-2000 and ECX-1000, so we need to have different nodes for each platform. Signed-off-by: Rob Herring <rob.herring@calxeda.com> [Device Tree documentation updated.] Signed-off-by: Robert Richter <rric@kernel.org>
2013-02-02cpufreq / highbank: add support for highbank cpufreqMark Langsdorf1-0/+10
Highbank processors depend on the external ECME to perform voltage management based on a requested frequency. Communication between the A9 cores and the ECME happens over the pl320 IPC channel. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Reviewed-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-01-08ARM: dts: fix highbank cpu mpidr valuesRob Herring1-8/+8
With the addition of commit a0ae0240 (ARM: kernel: add device tree init map function), the cpu reg values must match the cpu mpidr register or we'll get warnings. For some reason, the CLUSTERID on highbank is 9, so the reg value needs to be 0x90n to quiet the warnings. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-01-08ARM: dts: add device_type prop to cpu nodes on Calxeda platformsRob Herring1-0/+4
While device_type is considered deprecated, it is still needed for tools like lshw to identify cpu nodes. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2012-10-31ARM: dts: Add Calxeda ECX-2000 supportRob Herring1-216/+3
Separate out common dts pieces from highbank dts and add support for Calxeda ECX-2000 (Midway) SOC. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2012-10-31ARM: highbank: enable coherent DMA for xgmac in dtsRob Herring1-0/+2
Enable the xgmac to use the coherent DMA path in highbank.dts Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2012-10-31ARM: highbank: disable unused sdhci and gpio in dtsRob Herring1-0/+5
These peripherals are not enabled in current systems, so turn them off. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2012-10-03Merge branch 'for-v3.7' of ↵Linus Torvalds1-0/+1
git://git.linaro.org/people/mszyprowski/linux-dma-mapping Pull CMA and DMA-mapping updates from Marek Szyprowski: "This time the pull request is rather small, because the further redesign patches were not ready on time. This pull request consists of the patches which extend ARM DMA-mapping subsystem with support for CPU coherent (ACP) DMA busses. The first client of the new version is HighBank SATA driver. The second part of the pull request includes various cleanup for both CMA common code and ARM DMA-mapping subsystem." Fix up trivial add-add conflict due to the "dma-coherent" DT property being added next to the "calxeda,port-phys" property for the Calxeda AHCI controller. * 'for-v3.7' of git://git.linaro.org/people/mszyprowski/linux-dma-mapping: ARM: dma-mapping: Remove unsed var at arm_coherent_iommu_unmap_page ARM: highbank: add coherent DMA setup ARM: kill off arch_is_coherent ARM: add coherent iommu dma ops ARM: add coherent dma ops ARM: dma-mapping: Refrain noisy console message ARM: dma-mapping: Small logical clean up drivers: dma-contiguous: refactor dma_alloc_from_contiguous()
2012-10-02ARM: highbank: add coherent DMA setupRob Herring1-0/+1
Some highbank DMA masters can support coherent (ACP) or non-coherent DMA. This sets up dma_map_ops for masters which are configured for coherent DMA. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
2012-09-13ata: add platform driver for Calxeda AHCI controllerMark Langsdorf1-0/+17
Calxeda highbank SATA phy has intermittent problems bringing up a link with Gen3 drives. Retrying the phy hard reset can work-around this issue, but each reset also disables spread spectrum support. The reset function also needs to reprogram the phy to enable spread spectrum support. Create a new driver based on ahci_platform to support the Calxeda Highbank SATA controller. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2012-07-30Merge git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-edacLinus Torvalds1-0/+12
Pull EDAC patches from Mauro Carvalho Chehab: - the second part of the EDAC rework: - Add the sysfs nodes that exports the real memory layout, instead of the fake one (needed to properly represent Intel memory controllers since 2002) - convert EDAC MC to use "struct device" instead of creating the sysfs nodes via the kobj API - adds a tracepoint to represent memory errors - some cleanup patches - some fixes at i5000, i5400 and EDAC core - a new EDAC driver for Caldera. * git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-edac: (33 commits) edac i5000, i5400: fix pointer math in i5000_get_mc_regs() edac: allow specifying the error count with fake_inject edac: add support for Calxeda highbank L2 cache ecc edac: add support for Calxeda highbank memory controller edac: create top-level debugfs directory sb_edac: properly handle error count i7core_edac: properly handle error count edac: edac_mc_handle_error(): add an error_count parameter edac: remove arch-specific parameter for the error handler amd64_edac: Don't pass driver name as an error parameter edac_mc: check for allocation failure in edac_mc_alloc() edac: Increase version to 3.0.0 edac_mc: Cleanup per-dimm_info debug messages edac: Convert debugfX to edac_dbg(X, edac: Use more normal debugging macro style edac: Don't add __func__ or __FILE__ for debugf[0-9] msgs Edac: Add ABI Documentation for the new device nodes edac: move documentation ABI to ABI/testing/sysfs-devices-edac i7core_edac: change the mem allocation scheme to make Documentation/kobject.txt happy edac: change the mem allocation scheme to make Documentation/kobject.txt happy ...
2012-07-12clk: add highbank clock supportRob Herring1-1/+90
This adds real clock support to Calxeda Highbank SOC using the common clock infrastructure. Signed-off-by: Rob Herring <rob.herring@calxeda.com> [mturquette@linaro.org: fixed up invalid writes to const struct member] Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-06-27edac: add support for Calxeda highbank L2 cache eccRob Herring1-0/+6
Add support for L2 ECC on Calxeda highbank platform. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2012-06-27edac: add support for Calxeda highbank memory controllerRob Herring1-0/+6
Add support for memory controller on Calxeda Highbank platforms. Highbank platforms support a single 4GB mini-DIMM with 1-bit correction and 2-bit detection. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
2012-04-15ARM: dts: remove blank interrupt-parent propertiesRob Herring1-1/+0
These were incorrectly introduced and can cause problems for of_irq_init. The correct way to define a root controller is no interrupt-parent set at all or the interrupt-parent is set to the root controller itself when inherited from a parent node. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Tested-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2012-03-13ARM: highbank: convert to twd_local_timer_register() interfaceMarc Zyngier1-4/+4
Add support for the new smp_twd runtime registration interface to the highbank platforms, and remove the old compile-time support. The highbank DTS file is updated to match the TWD DT documentation and fixes the timer trigger (rising edge). Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2011-12-05ARM: highbank: add xgmac ethernet devices to dtsRob Herring1-0/+12
Add device nodes for xgmac ethernet block in Calxeda Highbank. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2011-10-31ARM: highbank: add devicetree sourceRob Herring1-0/+198
This adds the devicetree source and documentation for the Calxeda highbank platform. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Jamie Iles <jamie@jamieiles.com> Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
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