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Two trivial overlapping changes conflicts in MPLS and mlx5.
Signed-off-by: David S. Miller <davem@davemloft.net>
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AHCI provides the register PORTS_IMPL to let the software know which port
is supported. The register must be initialized by the bootloader. However
in some cases u-boot doesn't properly initialize this value (if it is not
compiled with SATA support for example or if the SATA initialization fails).
The DTS entry "ports-implemented" can be used to override the value in
PORTS_IMPL.
Without this patch the SATA will not work in the following two cases:
* if there has been a failure to initialize SATA in u-boot.
* if ahci_platform module has been removed and re-inserted. The reason is
that the content of PORTS_IMPL is lost after the module is removed.
I suspect that it's because the controller is reset by the hwmod.
Cc: <stable@vger.kernel.org> # v4.6+
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
[tony@atomide.com: updated comments with what goes wrong]
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Even if no_bd_ram property is described in TI CPSW bindings the support for
it has never been introduced in CPSW driver, so there are no real users of
it. Hence, remove no_bd_ram property from documentation and DT files.
Cc: 'Rob Herring <robh+dt@kernel.org>'
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Commit 55871eb6e2cc ("ARM: dts: dra7: Remove skeleton.dtsi usage")
removed the skeleton.dtsi usage since we want to get rid of it.
But this can cause issues when booting a kernel with a boot-loader
that doesn't create a chosen node if this isn't present in the DTB
since the decompressor relies on a pre-existing chosen node to be
available to insert the command line and merge other ATAGS info.
Fixes: 55871eb6e2cc ("ARM: dts: dra7: Remove skeleton.dtsi usage")
Reported-by: Pali Rohar <pali.rohar@gmail.com>
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Drivers using pinctrl-single,pins have #pinctrl-cells = <1>, while
pinctrl-single,bits need #pinctrl-cells = <2>.
Note that this patch can be optionally applied separately from the
driver changes as the driver supports also the legacy binding without
#pinctrl-cells.
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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This reverts commit f80bc97fd0a9711ef11bdb3e63c2c01115a82c47.
The original commit updated the cpufreq operating points tables for
dra7xx but was merged before the driver making use of the node was
merged, which breaks the existing cpufreq implementation on the system,
so revert the patch until the ti-cpufreq driver is merged.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The skeleton.dtsi file was removed in ARM64 for different reasons as
explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi").
These also applies to ARM and it will also allow to get rid of the
following DTC warnings in the future:
"Node /memory has a reg or ranges property, but no unit name"
The disassembled DTB are almost the same besides an empty chosen
node being removed and nodes reordered, so it should not have
functional changes.
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Current clocks tree definition for CPSW/CPTS doesn't
correspond TRM for dra7/am57 SoCs.
CPTS: has to be sourced from gmac_rft_clk_mux clock
CPSW: DPLL_GMAC -> CLKOUT_M2 -> GMAC_250M_CLK -> 1/2 ->
-> GMAC_MAIN_CLK (125 MHZ)
Hence, correct clock tree for GMAC_MAIN_CLK and use proper
clock for CPTS. This also require updating of CPTS clock
multiplier.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Since DRA7 has multiple PCIe Rootcomplex, add "linux,pci-domain"
property to assign a PCI domain number to each of the host
bridges.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Silicon limitation i845 documents how to cope with false
disconnection condition on USB2 PHY. Reference: AM572x
silicon errata document SPRZ429H, revised January 2016.
Using compatible "ti,dra7x-usb2" enables the recommended
software workaround for this issue. Use it for USB1 PHY.
The workaround is already in place for USB2 PHY.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Olof Johansson:
"Device tree contents continue to be the largest branches we submit.
This time around, some of the contents worth pointing out is:
New SoC platforms:
- Freescale i.MX 7Solo
- Broadcom BCM23550
- Cirrus Logic EP7209 and EP7211 (clps711x platforms)_
- Hisilicon HI3519
- Renesas R8A7792
Some of the other delta that is sticking out, line-count wise:
- Exynos moves of IP blocks under an SoC bus, which causes a large
delta due to indentation changes
- a new Tegra K1 board: Apalis
- a bunch of small updates to many Allwinner platforms; new hardware
support, some cleanup, etc"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (426 commits)
ARM: dts: sun8i: Add dts file for inet86dz board
ARM: dts: sun8i: Add dts file for Polaroid MID2407PXE03 tablet
ARM: dts: sun8i: Use sun8i-reference-design-tablet for ga10h dts
ARM: dts: sun8i: Use sun8i-reference-design-tablet for polaroid mid2809pxe04
ARM: dts: sun8i: reference-design-tablet: Add drivevbus-supply
ARM: dts: Copy sun8i-q8-common.dtsi sun8i-reference-design-tablet.dtsi
ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for utoo p66 dts
ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for dit4350 dts
ARM: dts: sun5i: reference-design-tablet: Remove mention of q8
ARM: dts: sun5i: reference-design-tablet: Set lradc vref to avcc
ARM: dts: sun5i: Rename sun5i-q8-common.dtsi sun5i-reference-design-tablet.dtsi
ARM: dts: sun5i: Move q8 display bits to sun5i-a13-q8-tablet.dts
ARM: dts: sunxi: Rename sunxi-q8-common.dtsi sunxi-reference-design-tablet.dtsi
ARM: dts: at91: Don't build unnecessary dtbs
ARM: dts: at91: sama5d3x: separate motherboard gmac and emac definitions
ARM: dts: at91: at91sam9g25ek: fix isi endpoint node
ARM: dts: at91: move isi definition to at91sam9g25ek
ARM: dts: at91: fix i2c-gpio node name
ARM: dts: at91: vinco: fix regulator name
ARM: dts: at91: ariag25 : fix onewire node
...
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Several cases of overlapping changes, except the packet scheduler
conflicts which deal with the addition of the free list parameter
to qdisc_enqueue().
Signed-off-by: David S. Miller <davem@davemloft.net>
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Add "ti,cpsw-mdio" for am335x/am437x/dra7 SoCs where MDIO is
implemented as part of TI CPSW and, this way, enable PM runtime auto
suspend for Davinci MDIO driver on these paltforms.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Adding dt node for hardware random number generator IP.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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DRA7 SoC has the same SHA IP as OMAP5. Add DT entry for the same.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[t-kristo@ti.com: changed SHA to use EDMA instead of SDMA]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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DRA7 SoC has the same AES IP as OMAP4. Add DT entries for both AES cores.
Signed-off-by: Joel Fernandes <joelf@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[t-kristo@ti.com: squashed in the change to use EDMA, squashed in
support for two AES cores]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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DRA7xx SoCs have a DES3DES IP. Add DT data for the same.
Signed-off-by: Joel Fernandes <joelf@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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There is no reason to hold s/w dependent parameter in device tree.
Even more, there is no reason in this parameter because davinici_cpdma
driver splits pool of descriptors equally between tx and rx channels
anyway.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@linaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
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The unit address of the second PCIe instance
is set to be same as that of the first instance
(copy-paste error).
Fix it.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Correct misspelling, "emda3" -> "edma3".
Reported-by: Adam J Allison <adamj.allison@gmail.com>
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add an operating-points-v2 table with all OPPs available for all silicon
revisions along with necessary data for use by ti-opp driver to selectively
enable the appropriate OPPs at runtime and handle voltage transitions
As we now need to define voltage ranges for each OPP, we define the
minimum and maximum voltage to match the ranges possible for AVS class0
voltage as defined by the DRA7/AM57 Data Manual, with the exception of
using a range for OPP_OD based on historical data to ensure that SoCs
from older lots still continue to boot, even though more optimal voltages
are now the standard. Once an AVS Class0 driver is in place it will be
possible for these OPP voltages to be adjusted to any voltage within the
provided range.
Information from SPRS953, Revised December 2015.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Nearly all of the information in the cpus node, especially for cpu0, is
the same between dra74x and dra72x so move the common information to
the parent dra7.dtsi to avoid duplication of data.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Create a system control module node for the control module portion that
resides under l4_wkup.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Secure variants of DRA7xx and AM57xx SoCs may need to reserve a region
of the SRAM for use by secure software. To account for this, add a child
node to the ocmcram1 node that will act as a placeholder at the start
of the SRAM for the reserved region of memory that may be required
by secure services. The node is added with size 0 so that by default
parts will have the full space available but the bootloader or board dts
file is able to resize the node as needed depending on how much reserved
space is needed, if any, so end users of the ocmcram1 region on HS parts
must be aware that a smaller amount of SRAM than expected may be available.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add all ocmcram nodes to dra7.dtsi using the generic mmio-sram driver.
DRA7xx and AM57xx families of SoCs can contain three ocmcram regions of
SRAM, one of 512kb and also an optional two additional of 1Mb each. Mark
the two additional 1MB regions of SRAM as disabled as only ocmcmram1 is
on all variants of the SoCs, then depending on which specific variant
is in use the ocmcram2 and ocmcram3 nodes can be enabled in the board
dts file if the data manual for that part number indicates the ocmcram
region is available.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Reviewed-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add PWMSS device tree nodes for DRA7 SoC family and add documentation
for dt bindings.
Signed-off-by: Vignesh R <vigneshr@ti.com>
[fcooper@ti.com: Add eCAP and use updated bindings for PWMSS and ePWM]
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add dma channel information to the gpmc.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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GPMC driver provides GPI support for the GPMC_WAIT pins.
Mark it gpio controller capable.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add the DT node for Timer12 present on DRA7 family of
SoCs. Timer12 is present in PD_WKUPAON power domain, and
has the same capabilities as the other timers, except for
the fact that it serves as a secure timer on HS devices
and is clocked only from the secure 32K clock.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The Timers 13 through 16 have been added previously in
disabled state. These timers are common timers that are
present on all DRA7 family of SoCs, so enable these
devices by default like the rest of the DMTimers.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add nodes to represent all McASP ports in the dra7 family.
For system consistency use the eDMA for audio operations. sDMA would be
fine for 4/5/6/7/8 since their DAT port is not through L3 interconnect.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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McASP3 does not support constant addressing mode on the DAT
port, so increment transfers must be used instead. This
restriction is also applicable for McASP1 and McASP2.
This DMA addressing constraint poses a major problem for sDMA
where constant addressing mode is used on the peripheral side.
Unfortunately, using increment transfers in sDMA comes with
important side effects.
The addressing mode used in eDMA is INC, so the silicon limitation
described above has no impact and the McASP3 DAT port can be
safely added by switching to eDMA instead of sDMA.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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DRA7 family has eDMA available along with the sDMA and in some cases it is
better suited for servicing peripherals.
Add the needed nodes for eDMA to be usable:
edma-tpcc, edma-tptc0/1 and the edma-xbar.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Move the sDMA xbar nodes under the L4 interconnect node.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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This patch fixes the following DTC warnings:
"pbias_regulator has a reg or ranges property, but no unit name"
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Arnd Bergmann:
"These are all the updates to device tree files for 32-bit platforms,
plus a couple of related 64-bit updates:
New SoC support:
- Allwinner A83T
- Axis Artpec-6 SoC
- Mediatek MT7623 SoC
- TI Keystone K2G SoC
- ST Microelectronics stm32f469
New board or machine support:
- ARM Juno R2
- Buffalo Linkstation LS-QVL and LS-GL
- Cubietruck plus
- D-Link DIR-885L
- DT support for ARM RealView PB1176 and PB11MPCore
- Google Nexus 7
- Homlet v2
- Itead Ibox
- Lamobo R1
- LG Optimus Black
- Logicpd dm3730
- Raspberry Pi Model A
Other changes include
- Lots of updates for Qualcomm APQ8064, MSM8974 and others
- Improved support for Nokia N900 and other OMAP machines
- Common clk support for lpc32xx
- HDLCD display on ARM
- Improved stm32f429 support
- Improved Renesas device support, r8a779x and others
- Lots of Rockchip updates
- Samsung cleanups
- ADC support for Atmel SAMA5D2
- BCM2835 (Raspberry Pi) improvements
- Broadcom Northstar Plus enhancements
- OMAP GPMC rework
- Several improvements for Atmel SAMA5D2 / Xplained
- Global change to remove inofficial "arm,amba-bus" compatible
string"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (350 commits)
ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus"
ARM: dts: artpec: dual-license on artpec6.dtsi
ARM: dts: ux500: add synaptics RMI4 for Ux500 TVK DT
arm64: dts: juno/vexpress: fix node name unit-address presence warnings
arm64: dts: foundation-v8: add SBSA Generic Watchdog device node
ARM: dts: at91: sama5d2 Xplained: add leds node
ARM: dts: at91: sama5d2 Xplained: add user push button
ARM: dts: at91: sama5d2 Xplained: set pin muxing for usb gadget and usb host
ARM: dts: stm32f429: Enable Ethernet on Eval board
ARM: dts: omap3-sniper: TWL4030 keypad support
Revert "ARM: dts: DRA7: Add dt nodes for PWMSS"
ARM: dts: dm814x: dra62x: Disable wait pin monitoring for NAND
ARM: dts: dm814x: dra62x: Fix NAND device nodes
ARM: dts: stm32f429: Add Ethernet support
ARM: dts: stm32f429: Add system config bank node
ARM: dts: at91: sama5d2: add nand0 and nfc0 nodes
ARM: dts: at91: sama5d2: add dma properties to UART nodes
ARM: dts: at91: sama5d2 Xplained: Correct the macb irq pinctrl node
ARM: dts: exynos: Don't overheat the Odroid XU3-Lite on high load
ARM: dts: exynos: Add cooling levels for Exynos5422/5800 CPUs
...
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Errata id: i877
Description:
------------
The RGMII 1000 Mbps Transmit timing is based on the output clock
(rgmiin_txc) being driven relative to the rising edge of an internal
clock and the output control/data (rgmiin_txctl/txd) being driven relative
to the falling edge of an internal clock source. If the internal clock
source is allowed to be static low (i.e., disabled) for an extended period
of time then when the clock is actually enabled the timing delta between
the rising edge and falling edge can change over the lifetime of the
device. This can result in the device switching characteristics degrading
over time, and eventually failing to meet the Data Manual Delay Time/Skew
specs.
To maintain RGMII 1000 Mbps IO Timings, SW should minimize the
duration that the Ethernet internal clock source is disabled. Note that
the device reset state for the Ethernet clock is "disabled".
Other RGMII modes (10 Mbps, 100Mbps) are not affected
Workaround:
-----------
If the SoC Ethernet interface(s) are used in RGMII mode at 1000 Mbps,
SW should minimize the time the Ethernet internal clock source is disabled
to a maximum of 200 hours in a device life cycle. This is done by enabling
the clock as early as possible in IPL (QNX) or SPL/u-boot (Linux/Android)
by setting the register CM_GMAC_CLKSTCTRL[1:0]CLKTRCTRL = 0x2:SW_WKUP.
So, do not allow to gate the cpsw clocks using ti,no-idle property in
cpsw node assuming 1000 Mbps is being used all the time. If someone does
not need 1000 Mbps and wants to gate clocks to cpsw, this property needs
to be deleted in their respective board files.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
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This reverts commit 5fcc673067a2b577d37f2c5c5439dbb177f7107e.
The binding may need to change pending related hwmod comments,
so reverting as requested by Paul Walmsley <paul@pwsan.com>.
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Add PWMSS device tree nodes for DRA7 SoC family and add documentation
for dt bindings.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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DRA7 SoC has the capability to support DDR memory upto 4GB. In order to
represent this in memory dt node, the address-cells and size cells
should be 2. So, changing the address-cells and size-cells to 2 and
updating the memory nodes accordingly.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.
The GPMC node will provide an interrupt controller for the
NAND IRQs.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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OMAP5 has 3 thermal zones cpu, core and multimedia.
On the other hand DRA7 has 5 thermal zones cpu, gpu, core, dspeve
and iva. Currently cpu, core and multimedia are being added via device tree
and the other 2 are getting added via kernel. Add the missing thermal
domains in device tree so we can create the zones with the appropriate
trip numbers, type and temperatures.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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DWC3's tx-fifo-resize property has been deprecated
because of it being unnecessary to any HW other than
OMAP5 ES1.0.
Signed-off-by: Felipe Balbi <balbi@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add "syscon-phy-power" property and remove the deprecated "ctrl-module"
property from SATA and USB PHY node. Also remove the unused control
module dt nodes.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The USB2 PHY2 has a different register map compared to USB2 PHY1
to power on/off the PHY. In order to handle it, use the new compatible
string "ti,dra7x-usb2-phy2" for the second instance of USB2 PHY.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add "syscon-phy-power" property and "syscon-pcs" property which can
be used to perform the control module initializations and remove
the deprecated "ctrl-module" property from PCIe PHY dt nodes.
Phandle to "sysclk" clock node is also added to the PCIe PHY node
since some of the syscon initializations is based on system clock
frequency.
Since "omap_control_pcie1phy" and "omap_control_pcie2phy" devicetree
nodes are no longer used, remove it.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add new device tree node for the control module register space where
PCIe registers are present.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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