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The AST2600 EVB is not an A1.
Signed-off-by: Joel Stanley <joel@jms.id.au>
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Now that the pinctrl definitions of the ast2600 SoC have been fixed,
see commit 925fbe1f7eb6 ("dt-bindings: pinctrl: aspeed-g6: add FWQSPI
function/group"), it is safe to activate QSPI on the ast2600 evb.
Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Link: https://lore.kernel.org/r/20220603073705.1624351-1-clg@kaod.org
Signed-off-by: Joel Stanley <joel@jms.id.au>
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The AST2600A3 EVB has the following I2C devices:
- ADT7490 at 0x2e
- EEPROM at 0xa0
- LM75 at 0x9a
The bus these devices appear on can be configured by jumpers. The device
tree is configured with the buses given by the default jumper settings.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
Link: https://lore.kernel.org/r/20220623094717.3873328-1-joel@jms.id.au
Signed-off-by: Joel Stanley <joel@jms.id.au>
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The AST2600 EVB board should have dedicated compatible.
Fixes: 2ca5646b5c2f ("ARM: dts: aspeed: Add AST2600 and EVB")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220529104928.79636-5-krzysztof.kozlowski@linaro.org
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Enable the GFX device with a framebuffer memory region.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20220302024930.18758-3-tommy_huang@aspeedtech.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
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Enable Aspeed VHub for HID emulation
Signed-off-by: Howard Chiu <howard_chiu@aspeedtech.com>
Link: https://lore.kernel.org/r/SG2PR06MB23155E8A6193118544A7DBF3E61E9@SG2PR06MB2315.apcprd06.prod.outlook.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
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Enable video engine and reserve memory for it.
Signed-off-by: Howard Chiu <howard_chiu@aspeedtech.com>
Link: https://lore.kernel.org/r/SG2PR06MB23159B914BF7EF937FEDD2B5E61E9@SG2PR06MB2315.apcprd06.prod.outlook.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
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Since mac0/1 and mac2/3 are physically located on different die,
they have different properties by nature, which is mac0/1 has smaller delay step.
The property 'phy-mode' on ast2600 mac0 and mac1 is recommended to set to 'rgmii-rxid'
which enables the RX interface delay from the PHY chip.
Refer page 45 of SDK User Guide v08.00
https://github.com/AspeedTech-BMC/openbmc/releases/download/v08.00/SDK_User_Guide_v08.00.pdf
Fixes: 2ca5646b5c2f ("ARM: dts: aspeed: Add AST2600 and EVB")
Signed-off-by: Howard Chiu <howard_chiu@aspeedtech.com>
Link: https://lore.kernel.org/r/SG2PR06MB23152A548AAE81140B57DD69E6E09@SG2PR06MB2315.apcprd06.prod.outlook.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
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Aspeed AST2600 u-boot requires 600KiB+ flash space. Sharing the same
openbmc-flash-layout-64.dtsi requires to resize the flash partition.
The updated flash layout as follows:
- u-boot: 896 KiB
- u-boot-env: 128 KiB
- kernel: 9MiB
- rofs: 32 MiB
- rwfs: 22 MiB
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20210316085932.2601-1-troy_lee@aspeedtech.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
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Set MMC timing-phase register by adding the phase correction binding in the
device tree.
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20210524073308.9328-3-steven_lee@aspeedtech.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
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AST2600 A2 (or newer) EVB has gpio regulators for toggling signal voltage
between 3.3v and 1.8v, the patch adds sdhci node and gpio regulator in
the dts file and adds comment for describing the reference design.
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20210524073308.9328-2-steven_lee@aspeedtech.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
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Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Link: https://lore.kernel.org/r/20201009024937.11246-4-ryan_chen@aspeedtech.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
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MAC0 was not functional in the AST2600A0 SoC. This has been resolved
with the A1, so allow use of this port on EVBs with the A1 and
subsequent revisions.
A0 EVBs will still boot with this change, but the first Ethernet device
will not be functional.
Signed-off-by: Joel Stanley <joel@jms.id.au>
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Use the first FSI master.
Signed-off-by: Joel Stanley <joel@jms.id.au>
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With the exception of i2c10 and i2c11 which conflict with the pins
for the third and forth MDIO controllers.
i2c0 has an ADT7490 fan controller/thermal monitor device connected. The
devicetree describes an adt74490 on i2c0, however bus that it appears on
depends on jumper settings, so it may not be present on all EVBs. It is
included to assist testing of I2C.
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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The UART has an issue on A0 that can be worked around by using the
Synopsis driver.
Tested-by: Eddie James <eajames@linux.ibm.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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All 2600-evb MACs use RGMII/MDIO.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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The AST2600 u-boot and kernel images have outgrown the OpenBMC layout.
While BMC machines use 128MB SPI NOR chips, we only have 64MB on the EVB
so use a layout that has a smaller region for the ro and rw filesystems.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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Signed-off-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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Enable the eMMC controller and limit it to 52MHz to avoid the host
controller reporting bus error conditions.
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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The AST2600 is a new SoC by ASPEED. It contains a dual core Cortex A7
CPU and shares many periperhals with the existing AST2400 and AST2500.
Link: https://lore.kernel.org/r/20190911165614.31641-1-joel@jms.id.au
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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