starfive-tech/linux.git - StarFive Tech Linux Kernel for VisionFive (JH7110) boards (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2021-08-25	ARC: mm: use SCRATCH_DATA0 register for caching pgdir in ARCv2 only	Vineet Gupta	1	-8/+0
2020-10-06	ARC: [plat-eznps]: Drop support for EZChip NPS platform	Vineet Gupta	1	-27/+0
2019-10-28	ARCv2: mm: TLB Miss optim: SMP builds can cache pgd pointer in mmu scratch reg	Vineet Gupta	1	-2/+2
2019-07-08	ARC: entry: EV_Trap expects r10 (vs. r9) to have exception cause	Vineet Gupta	1	-2/+2
2019-06-19	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	Thomas Gleixner	1	-4/+1
2018-07-09	ARC: [arcompact] entry.S: minor code movement	Vineet Gupta	1	-0/+6
2017-08-29	ARC: [plat-eznps] handle extra aux regs #2: kernel/entry exit	Liav Rehana	1	-0/+24
2016-05-30	Fix typos	Andrea Gelmini	1	-2/+2
2016-05-09	ARC: [plat-eznps] Use dedicated identity auxiliary register.	Noam Camus	1	-0/+6
2016-03-11	ARC: Fix misspellings in comments.	Adam Buchbinder	1	-1/+1
2015-10-17	ARC: [arcompact] entry.S: Improve early return from exception	Vineet Gupta	1	-7/+6
2015-06-19	ARC: intc: split into ARCompact ISA specific, common bits	Vineet Gupta	1	-0/+1
2015-06-19	ARC: entry.S: [arcompact] simplify SWITCH_TO_KERNEL_STK	Vineet Gupta	1	-36/+35
2015-06-19	ARC: entry.S: micro-optimize Trap handler	Vineet Gupta	1	-2/+3
2015-06-19	ARC: entry.S: split into ARCompact ISA specific, common bits	Vineet Gupta	1	-0/+306