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2022-10-17dt-bindings: pinctrl: qcom,msm8953: fix indentation in exampleKrzysztof Kozlowski1-17/+17
Bindings example should be indented with 4-spaces. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-24-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-17dt-bindings: pinctrl: qcom,msm8953: use common TLMM schemaKrzysztof Kozlowski1-39/+7
Reference common Qualcomm TLMM pin controller schema, to bring common properties, other pinctrl schemas and additional checks, like function required only for GPIOs. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-23-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-17dt-bindings: pinctrl: qcom,msm8953: fix matching pin configKrzysztof Kozlowski1-3/+11
The TLMM pin controller follows generic pin-controller bindings, so should have subnodes with '-state' and '-pins'. Otherwise the subnodes (level one and two) are not properly matched. This method also unifies the bindings with other Qualcomm TLMM and LPASS pinctrl bindings. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-22-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-17dt-bindings: pinctrl: qcom,msm8909-tlmm: fix indentation in exampleKrzysztof Kozlowski1-30/+30
Bindings example should be indented with 4-spaces. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-21-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-17dt-bindings: pinctrl: qcom,msm8909-tlmm: do not require function on non-GPIOsKrzysztof Kozlowski1-1/+0
Certain pins, like SDcard related, do not have functions and such should not be required. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-20-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-17dt-bindings: pinctrl: qcom,msm8909-tlmm: fix matching pin configKrzysztof Kozlowski1-3/+4
The TLMM pin controller follows generic pin-controller bindings, so should have subnodes with '-state' and '-pins'. Otherwise the subnodes (level one and two) are not properly matched. This method also unifies the bindings with other Qualcomm TLMM and LPASS pinctrl bindings. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-19-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-17dt-bindings: pinctrl: qcom,msm8226: fix indentation in exampleKrzysztof Kozlowski1-18/+18
Bindings example should be indented with 4-spaces. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-18-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-17dt-bindings: pinctrl: qcom,msm8226: add functions and input-enableKrzysztof Kozlowski1-6/+4
The MSM8226 pinctrl driver supports input-enable, blsp_i2c4, blsp_uart4 and sdc3 functions and DTS already uses it: qcom-msm8226-samsung-s3ve3g.dtb: pinctrl@fd510000: 'blsp1-i2c1', 'blsp1-i2c2', 'blsp1-i2c3', 'blsp1-i2c4', 'blsp1-i2c5' ... qcom-apq8026-lg-lenok.dtb: pinctrl@fd510000: touch-state: 'oneOf' conditional failed, one must be fixed: 'input-enable' does not match any of the regexes: 'pinctrl-[0-9]+' Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-17-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-17dt-bindings: pinctrl: qcom,msm8226: use common TLMM schemaKrzysztof Kozlowski1-33/+7
Reference common Qualcomm TLMM pin controller schema, to bring common properties, other pinctrl schemas and additional checks, like function required only for GPIOs. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-16-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-17dt-bindings: pinctrl: qcom,msm8226: fix matching pin configKrzysztof Kozlowski1-3/+11
The TLMM pin controller follows generic pin-controller bindings, so should have subnodes with '-state' and '-pins'. Otherwise the subnodes (level one and two) are not properly matched. This method also unifies the bindings with other Qualcomm TLMM and LPASS pinctrl bindings. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-15-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-17dt-bindings: pinctrl: qcom,ipq6018: fix indentation in exampleKrzysztof Kozlowski1-17/+17
Bindings example should be indented with 4-spaces. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-14-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-17dt-bindings: pinctrl: qcom,ipq6018: use common TLMM schemaKrzysztof Kozlowski1-38/+7
Reference common Qualcomm TLMM pin controller schema, to bring common properties, other pinctrl schemas and additional checks, like function required only for GPIOs. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-13-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-17dt-bindings: pinctrl: qcom,ipq6018: fix matching pin configKrzysztof Kozlowski1-4/+11
The TLMM pin controller follows generic pin-controller bindings, so should have subnodes with '-state' and '-pins'. Otherwise the subnodes (level one and two) are not properly matched. This method also unifies the bindings with other Qualcomm TLMM and LPASS pinctrl bindings. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-12-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-17dt-bindings: pinctrl: qcom,ipq6018: increase number of pins in pinmuxKrzysztof Kozlowski1-1/+1
One pinxmux node can have more than 4 pins to configure: ['gpio1', 'gpio3', 'gpio4', 'gpio5', 'gpio6', 'gpio7', 'gpio8', 'gpio10', 'gpio11', 'gpio12', 'gpio13', 'gpio14', 'gpio15', 'gpio17'] is too long Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-11-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-17dt-bindings: pinctrl: qcom,ipq6018: correct BLSP6->BLSP0 functionsKrzysztof Kozlowski1-3/+3
The pin controller driver has BLSP functions from 0 to 5, not 1 to 6. Add missing blsp0_i2c, blsp0_spi (already used in ipq6018-cp01-c1) and blsp0_uart. Drop blsp6_i2c and blsp6_spi. This fixes dtbs_check warning: ipq6018-cp01-c1.dtb: pinctrl@1000000: spi-0-state: 'oneOf' conditional failed, one must be fixed: 'bias-pull-down', 'drive-strength', 'function', 'pins' do not match any of the regexes: '-pins$', 'pinctrl-[0-9]+' 'blsp0_spi' is not one of ['adsp_ext', 'alsp_int', ..... Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-10-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-17dt-bindings: pinctrl: qcom,ipq6018: add qpic_pad functionKrzysztof Kozlowski1-3/+3
The IPQ6018 pinctrl driver supports qpic_pad and DTS already uses it: 'qpic_pad' is not one of ['adsp_ext', 'alsp_int', 'atest_bbrx0', ... Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-9-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-17dt-bindings: pinctrl: qcom,tlmm-common: add common check for functionKrzysztof Kozlowski1-4/+16
Certain pins, like SDcard related, do not have functions and such should not be required. Add a check for this in common Qualcomm TLMM pin controller schema. Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221016170035.35014-8-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-17dt-bindings: pinctrl: qcom,sm8250-lpass-lpi: add bias-bus-hold and input-enableKrzysztof Kozlowski1-4/+2
The existing SC7280 LPASS pin controller nodes use bias-bus-hold and input-enable, so allow them. Squash also blank lines for readability. Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220927153429.55365-13-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-17dt-bindings: pinctrl: qcom,sc7280-lpass-lpi: add bias-bus-holdKrzysztof Kozlowski1-4/+1
The existing SC7280 LPASS pin controller nodes use bias-bus-hold, so allow it. Squash also blank lines for readability. Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220927153429.55365-12-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-17dt-bindings: pinctrl: qcom,sm8450-lpass-lpi: fix matching pin configKrzysztof Kozlowski1-2/+34
The LPASS pin controller follows generic pin-controller bindings, so just like TLMM, should have subnodes with '-state' and '-pins'. Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220927153429.55365-11-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-17dt-bindings: pinctrl: qcom,sm8250-lpass-lpi: fix matching pin configKrzysztof Kozlowski1-2/+34
The LPASS pin controller follows generic pin-controller bindings, so just like TLMM, should have subnodes with '-state' and '-pins'. qcom/qrb5165-rb5.dtb: pinctrl@33c0000: wsa-swr-active-pins: 'pins' is a required property Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220927153429.55365-10-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-17dt-bindings: pinctrl: qcom,sc8280xp-lpass-lpi: fix matching pin configKrzysztof Kozlowski1-2/+27
The LPASS pin controller follows generic pin-controller bindings, so just like TLMM, should have subnodes with '-state' and '-pins'. Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220927153429.55365-9-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-17dt-bindings: pinctrl: qcom,sc7280-lpass-lpi: fix matching pin configKrzysztof Kozlowski1-2/+27
The LPASS pin controller follows generic pin-controller bindings, so just like TLMM, should have subnodes with '-state' and '-pins'. Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220927153429.55365-8-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-17dt-bindings: pinctrl: qcom,sm8450-lpass-lpi: fix gpio patternKrzysztof Kozlowski1-1/+1
Fix double ']' in GPIO pattern to properly match "pins" property. Otherwise schema for pins state fails. Fixes: 4faa4e73011d ("dt-bindings: pinctrl: qcom: Add sm8450 lpass lpi pinctrl bindings") Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220927153429.55365-7-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-17dt-bindings: pinctrl: qcom,sc8280xp-lpass-lpi: fix gpio patternKrzysztof Kozlowski1-1/+1
Fix double ']' in GPIO pattern to properly match "pins" property. Otherwise schema for pins state fails. Fixes: 958bb025f5b3 ("dt-bindings: pinctrl: qcom: Add sc8280xp lpass lpi pinctrl bindings") Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220927153429.55365-6-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2022-10-17ASoC: kirkwood: enable Kirkwood driver for Armada 38x platformsMarcin Wojtas1-1/+13
The audio unit of Marvell Armada38x SoC is similar to the ones comprised by other Marvell SoCs (Kirkwood, Dove and Armada 370). Therefore KW audio driver can be used to support it and this commit adds new compatible string to identify Armada 38x variant. Two new memory regions are added: first one for PLL configuration and the second one for choosing one of audio I/O modes (I2S or S/PDIF). For the latter purpose a new optional DT property is added ('spdif-mode'). kirkwood-i2s driver is extended by adding a new init function for Armada 38x flavor and also a routine that enables PLL output (i.e. MCLK) configuration. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Tested-by: Star_Automation <star@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com> Reviewed-by: Lior Amsalem <alior@marvell.com> Tested-by: Lior Amsalem <alior@marvell.com> Signed-off-by: Hezi Shahmoon <hezi@marvell.com> Reviewed-by: Neta Zur Hershkovits <neta@marvell.com> [pali: Fix support for pre-38x SoCs] Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20220926110533.13475-1-pali@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-17ASoC: dt-bindings: fsl_rpmsg: Add a property to assign the rpmsg channelChancel Liu1-2/+34
Add a string property to assign the rpmsg channel this sound card sits on. This property can be omitted if there is only one sound card and it sits on "rpmsg-audio-channel". Signed-off-by: Chancel Liu <chancel.liu@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220930064441.2548505-2-chancel.liu@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-17ASoC: dt-bindings: add schema for WM8961Doug Brown1-0/+40
Create a simple DT schema for the existing Wolfson WM8961 driver so that DT support can be added to the driver. Signed-off-by: Doug Brown <doug@schmorgal.com> Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20221003032414.248326-2-doug@schmorgal.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-17dt-bindings: rockchip: Add Hardkernel ODROID-M1 boardDongjin Kim1-0/+5
Add device tree binding for Hardkernel ODROID-M1 board based on RK3568 SoC. Signed-off-by: Dongjin Kim <tobetter@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Dan Johansen <strit@manjaro.org> Link: https://lore.kernel.org/r/20220930051246.391614-2-aurelien@aurel32.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-10-17dt-bindings: arm: rockchip: add Theobroma Systems PX30-µQ7 (Ringneck) with ↵Quentin Schulz1-0/+5
Haikou Add entry for the Theobroma Systems PX30-µQ7 (Ringneck) with Haikou devkit. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Link: https://lore.kernel.org/r/20220930-upstream-ringneck-v2-2-6671694b6934@theobroma-systems.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-10-17drm/i915/hwmon: Extend power/energy for XEHPSDVDale B Stimson1-1/+6
Extend hwmon power/energy for XEHPSDV especially per gt level energy usage. v2: Update to latest HWMON spec (Ashutosh) v3: Fix review comments (Ashutosh) v4: Fix review comments (Anshuman) v5: s/hwmon_device_register_with_info/ devm_hwmon_device_register_with_info/ (Ashutosh) v6: Change contact to intel-gfx (Rodrigo) GEN12_RPSTAT1 is available for all Gen12+ (Andi) Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221013154526.2105579-8-ashutosh.dixit@intel.com
2022-10-17dt-bindings: pinctrl: qcom: add sdm670 pinctrlRichard Acayan1-0/+127
There is a new driver for the Snapdragon 670 TLMM (Top-Level Mode Multiplexer). Document it. Adapted from qcom,sm6350-pinctrl.yaml. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221014001934.4995-2-mailingradian@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2022-10-17drm/i915/hwmon: Expose power1_max_intervalAshutosh Dixit1-0/+9
Expose power1_max_interval, that is the tau corresponding to PL1, as a custom hwmon attribute. Some bit manipulation is needed because of the format of PKG_PWR_LIM_1_TIME in GT0_PACKAGE_RAPL_LIMIT register (1.x * power(2,y)). v2: Update date and kernel version in Documentation (Badal) v3: Cleaned up hwm_power1_max_interval_store() (Badal) v4: - Fixed review comments (Anshuman) - In hwm_power1_max_interval_store() get PKG_MAX_WIN from pkg_power_sku when it is valid (Ashutosh) - KernelVersion: 6.2, Date: February 2023 in doc (Tvrtko) v5: On some of the DGFX setups it is seen that although pkg_power_sku is valid the field PKG_WIN_MAX is not populated. So it is decided to stick to default value of PKG_WIN_MAX (Ashutosh) v6: Change contact to intel-gfx (Rodrigo) Fixed variable types in hwm_power1_max_interval_store (Andi) Documented PKG_MAX_WIN_DEFAULT (Andi) Removed else in hwm_attributes_visible (Andi) Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221013154526.2105579-7-ashutosh.dixit@intel.com
2022-10-17drm/i915/hwmon: Expose card reactive critical powerAshutosh Dixit1-0/+26
Expose the card reactive critical (I1) power. I1 is exposed as power1_crit in microwatts (typically for client products) or as curr1_crit in milliamperes (typically for server). v2: Add curr1_crit functionality (Ashutosh) v3: Use HWMON_CHANNEL_INFO to define power1_crit, curr1_crit (Badal) v4: Use hwm_ prefix for static functions (Ashutosh) v5: KernelVersion: 6.2, Date: February 2023 in doc (Tvrtko) v6: Change contact to intel-gfx (Rodrigo) Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221013154526.2105579-6-ashutosh.dixit@intel.com
2022-10-17drm/i915/hwmon: Show device level energy usageDale B Stimson1-0/+8
Use i915 HWMON to display device level energy input. v2: Updated the date and kernel version in feature description v3: - Cleaned up hwm_energy function and removed unused function i915_hwmon_energy_status_get (Ashutosh) v4: KernelVersion: 6.2, Date: February 2023 in doc (Tvrtko) v5: Change contact to intel-gfx (Rodrigo) Change return type of hwm_energy to void (Andi) Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by: Riana Tauro <riana.tauro@intel.com> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221013154526.2105579-5-ashutosh.dixit@intel.com
2022-10-17Documentation/x86/boot: Reserve type_of_loader=13 for bareboxAhmad Fatoum1-0/+1
barebox[1], a bootloader for mostly ARM and MIPS embedded systems, can also be built as EFI payload for x86[2] to provide redundant power-fail safe, watchdog-supervised boot up. Since its v2015.09.0 release, it has been booting Linux on x86 with type_of_loader=0xff[3]. Reserve 13, the next free id, so that can be used instead in the future. [1]: https://www.barebox.org/ [2]: https://www.barebox.org/doc/latest/boards/efi.html [3]: https://elixir.bootlin.com/barebox/v2022.09.0/source/common/efi/payload/image.c#L217 Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lore.kernel.org/r/20221002125752.3400831-1-a.fatoum@pengutronix.de
2022-10-17drm/i915/hwmon: Power PL1 limit and TDP settingDale B Stimson1-0/+20
Use i915 HWMON to display/modify dGfx power PL1 limit and TDP setting. v2: - Fix review comments (Ashutosh) - Do not restore power1_max upon module unload/load sequence because on production systems modules are always loaded and not unloaded/reloaded (Ashutosh) - Fix review comments (Jani) - Remove endianness conversion (Ashutosh) v3: Add power1_rated_max (Ashutosh) v4: - Use macro HWMON_CHANNEL_INFO to define power channel (Guenter) - Update the date and kernel version in Documentation (Badal) v5: Use hwm_ prefix for static functions (Ashutosh) v6: Fix review comments (Ashutosh) v7: - Define PCU_PACKAGE_POWER_SKU for DG1,DG2 and move PKG_PKG_TDP to intel_mchbar_regs.h (Anshuman) - KernelVersion: 6.2, Date: February 2023 in doc (Tvrtko) v8: Change contact to intel-gfx (Rodrigo) Minor change to val_sku_unit init (Andi) Cc: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Signed-off-by: Riana Tauro <riana.tauro@intel.com> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221013154526.2105579-4-ashutosh.dixit@intel.com
2022-10-17drm/i915/hwmon: Add HWMON current voltage supportRiana Tauro1-0/+7
Use i915 HWMON subsystem to display current input voltage. v2: - Updated date and kernel version in feature description - Fixed review comments (Ashutosh) v3: Use macro HWMON_CHANNEL_INFO to define hwmon channel (Guenter) v4: - Fixed review comments (Ashutosh) - Use hwm_ prefix for static functions (Ashutosh) v5: Added unit of voltage as millivolts (Ashutosh) v6: KernelVersion: 6.2, Date: February 2023 in doc (Tvrtko) v7: Change contact to intel-gfx (Rodrigo) GEN12_RPSTAT1 is available for all Gen12+ (Andi) Added Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon to MAINTAINERS Cc: Guenter Roeck <linux@roeck-us.net> Cc: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Riana Tauro <riana.tauro@intel.com> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221013154526.2105579-3-ashutosh.dixit@intel.com
2022-10-17dt-bindings: input: touchscreen: Add compatible for Goodix GT7986U chipSheng-Liang Pan1-1/+4
Add a compatible for Goodix touch screen chip GT7986U which is is expected to be fully compatible with a driver written for GT7375P. Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221006185333.v7.3.I52e4b4b20e2eb0ae20f2a9bb198aa6410f04cf16@changeid Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
2022-10-17Merge tag 'random-6.1-rc1-for-linus' of ↵Linus Torvalds1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/crng/random Pull more random number generator updates from Jason Donenfeld: "This time with some large scale treewide cleanups. The intent of this pull is to clean up the way callers fetch random integers. The current rules for doing this right are: - If you want a secure or an insecure random u64, use get_random_u64() - If you want a secure or an insecure random u32, use get_random_u32() The old function prandom_u32() has been deprecated for a while now and is just a wrapper around get_random_u32(). Same for get_random_int(). - If you want a secure or an insecure random u16, use get_random_u16() - If you want a secure or an insecure random u8, use get_random_u8() - If you want secure or insecure random bytes, use get_random_bytes(). The old function prandom_bytes() has been deprecated for a while now and has long been a wrapper around get_random_bytes() - If you want a non-uniform random u32, u16, or u8 bounded by a certain open interval maximum, use prandom_u32_max() I say "non-uniform", because it doesn't do any rejection sampling or divisions. Hence, it stays within the prandom_*() namespace, not the get_random_*() namespace. I'm currently investigating a "uniform" function for 6.2. We'll see what comes of that. By applying these rules uniformly, we get several benefits: - By using prandom_u32_max() with an upper-bound that the compiler can prove at compile-time is ≤65536 or ≤256, internally get_random_u16() or get_random_u8() is used, which wastes fewer batched random bytes, and hence has higher throughput. - By using prandom_u32_max() instead of %, when the upper-bound is not a constant, division is still avoided, because prandom_u32_max() uses a faster multiplication-based trick instead. - By using get_random_u16() or get_random_u8() in cases where the return value is intended to indeed be a u16 or a u8, we waste fewer batched random bytes, and hence have higher throughput. This series was originally done by hand while I was on an airplane without Internet. Later, Kees and I worked on retroactively figuring out what could be done with Coccinelle and what had to be done manually, and then we split things up based on that. So while this touches a lot of files, the actual amount of code that's hand fiddled is comfortably small" * tag 'random-6.1-rc1-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/crng/random: prandom: remove unused functions treewide: use get_random_bytes() when possible treewide: use get_random_u32() when possible treewide: use get_random_{u8,u16}() when possible, part 2 treewide: use get_random_{u8,u16}() when possible, part 1 treewide: use prandom_u32_max() when possible, part 2 treewide: use prandom_u32_max() when possible, part 1
2022-10-14Merge tag 'leds-6.1-rc1' of ↵Linus Torvalds1-18/+21
git://git.kernel.org/pub/scm/linux/kernel/git/pavel/linux-leds Pull LED updates from Pavel Machek: "This is very quiet release for LEDs, pca963 got blinking support and that's pretty much it" * tag 'leds-6.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/pavel/linux-leds: leds: pca963: fix misleading indentation dt-bindings: leds: Document mmc trigger leds: pca963x: fix blink with hw acceleration
2022-10-14Merge tag 'sched-psi-2022-10-14' of ↵Linus Torvalds1-0/+23
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull PSI updates from Ingo Molnar: - Various performance optimizations, resulting in a 4%-9% speedup in the mmtests/config-scheduler-perfpipe micro-benchmark. - New interface to turn PSI on/off on a per cgroup level. * tag 'sched-psi-2022-10-14' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: sched/psi: Per-cgroup PSI accounting disable/re-enable interface sched/psi: Cache parent psi_group to speed up group iteration sched/psi: Consolidate cgroup_psi() sched/psi: Add PSI_IRQ to track IRQ/SOFTIRQ pressure sched/psi: Remove NR_ONCPU task accounting sched/psi: Optimize task switch inside shared cgroups again sched/psi: Move private helpers to sched/stats.h sched/psi: Save percpu memory when !psi_cgroups_enabled sched/psi: Don't create cgroup PSI files when psi_disabled sched/psi: Fix periodic aggregation shut off
2022-10-14Merge tag 'arm64-fixes' of ↵Linus Torvalds1-0/+2
git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 fixes from Catalin Marinas: - Cortex-A55 errata workaround (repeat TLBI) - AMPERE1 added to the Spectre-BHB affected list - MTE fix to avoid setting PG_mte_tagged if no tags have been touched on a page - Fixed typo in the SCTLR_EL1.SPINTMASK bit naming (the commit log has other typos) - perf: return value check in ali_drw_pmu_probe(), ALIBABA_UNCORE_DRW_PMU dependency on ACPI * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: Add AMPERE1 to the Spectre-BHB affected list arm64: mte: Avoid setting PG_mte_tagged if no tags cleared or restored MAINTAINERS: rectify file entry in ALIBABA PMU DRIVER drivers/perf: ALIBABA_UNCORE_DRW_PMU should depend on ACPI drivers/perf: fix return value check in ali_drw_pmu_probe() arm64: errata: Add Cortex-A55 to the repeat tlbi list arm64/sysreg: Fix typo in SCTR_EL1.SPINTMASK
2022-10-14Merge tag 'riscv-for-linus-6.1-mw2' of ↵Linus Torvalds7-22/+65
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull more RISC-V updates from Palmer Dabbelt: - DT updates for the PolarFire SOC - a fix to correct the handling of write-only mappings - m{vetndor,arcd,imp}id is now in /proc/cpuinfo - the SiFive L2 cache controller support has been refactored to also support L3 caches - misc fixes, cleanups and improvements throughout the tree * tag 'riscv-for-linus-6.1-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (42 commits) MAINTAINERS: add RISC-V's patchwork RISC-V: Make port I/O string accessors actually work riscv: enable software resend of irqs RISC-V: Re-enable counter access from userspace riscv: vdso: fix NULL deference in vdso_join_timens() when vfork riscv: Add cache information in AUX vector soc: sifive: ccache: define the macro for the register shifts soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes soc: sifive: ccache: reduce printing on init soc: sifive: ccache: determine the cache level from dts soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache riscv: check for kernel config option in t-head memory types errata riscv: use BIT() marco for cpufeature probing riscv: use BIT() macros in t-head errata init riscv: drop some idefs from CMO initialization riscv: cleanup svpbmt cpufeature probing riscv: Pass -mno-relax only on lld < 15.0.0 RISC-V: Avoid dereferening NULL regs in die() dt-bindings: riscv: add new riscv,isa strings for emulators ...
2022-10-14MAINTAINERS: nfc: s3fwrn5: Drop Krzysztof OpasiakKrzysztof Kozlowski1-1/+0
Emails to Krzysztof Opasiak bounce ("Recipient address rejected: User unknown") so drop his email from maintainers of s3fwrn5 NFC bindings and driver. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-10-13Merge tag 'devicetree-fixes-for-6.1-1' of ↵Linus Torvalds2-5/+4
git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree fixes from Rob Herring: - Fixes for Mediatek MT6370 binding - Merge the DT overlay maintainer entry to the main entry as Pantelis is not active and Frank is taking a step back * tag 'devicetree-fixes-for-6.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: MAINTAINERS: of: collapse overlay entry into main device tree entry dt-bindings: mfd: mt6370: fix the interrupt order of the charger in the example dt-bindings: leds: mt6370: Fix MT6370 LED indicator DT warning
2022-10-13Documentation: ACPI: Prune DSDT override documentation from indexBagas Sanjaya1-1/+0
Commit d206cef03c4827 ("ACPI: docs: Drop useless DSDT override documentation") removes useless DSDT override documentation. However, the commit forgets to prune the documentation entry from table of contents of ACPI admin guide documentation, hence triggers Sphinx warning: Documentation/admin-guide/acpi/index.rst:8: WARNING: toctree contains reference to nonexisting document 'admin-guide/acpi/dsdt-override' Prune the entry to fix the warning. Fixes: d206cef03c4827 ("ACPI: docs: Drop useless DSDT override documentation") Signed-off-by: Bagas Sanjaya <bagasdotme@gmail.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-10-13Merge patch series "Use composable cache instead of L2 cache"Palmer Dabbelt1-5/+23
Zong Li <zong.li@sifive.com> says: Since composable cache may be L3 cache if private L2 cache exists, we should use its original name "composable cache" to prevent confusion. This patchset contains the modification which is related to ccache, such as DT binding and EDAC driver. * b4-shazam-merge: riscv: Add cache information in AUX vector soc: sifive: ccache: define the macro for the register shifts soc: sifive: ccache: use pr_fmt() to remove CCACHE: prefixes soc: sifive: ccache: reduce printing on init soc: sifive: ccache: determine the cache level from dts soc: sifive: ccache: Rename SiFive L2 cache to Composable cache. dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache Link: https://lore.kernel.org/r/20220913061817.22564-1-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-10-13dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cacheZong Li1-5/+23
Since composable cache may be L3 cache if private L2 cache exists, we should use its original name Composable cache to prevent confusion. Signed-off-by: Zong Li <zong.li@sifive.com> Suggested-by: Conor Dooley <conor.dooley@microchip.com> Suggested-by: Ben Dooks <ben.dooks@sifive.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220913061817.22564-2-zong.li@sifive.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2022-10-13Merge tag 'docs-6.1-2' of git://git.lwn.net/linuxLinus Torvalds19-150/+107
Pull documentation fixes from Jonathan Corbet: "A handful of relatively simple documentation fixes, plus a set of patches catching the Chinese translation up with the front-page rework" * tag 'docs-6.1-2' of git://git.lwn.net/linux: Documentation: rtla: Correct command line example docs/zh_CN: add a man-pages link to zh_CN/index.rst docs/zh_CN: Rewrite the Chinese translation front page docs/zh_CN: add zh_CN/arch.rst docs/zh_CN: promote the title of zh_CN/process/index.rst docs/zh_CN: Update the translation of page_owner to 6.0-rc7 docs/zh_CN: Update the translation of ksm to 6.0-rc7 docs/howto: Replace abundoned URL of gmane.org Documentation: ubifs: Fix compression idiom Documentation/mm/page_owner.rst: delete frequently changing experimental data docs/zh_CN: Fix build warning docs: ftrace: Correct access mode
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-03 02:57:20 +0300