Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2019-10-23 | dt-bindings: riscv: Fix CPU schema errors | Rob Herring | 1 | -16/+13 |
2019-08-09 | dt-bindings: riscv: fix the schema compatible string for the HiFive Unleashed... | Paul Walmsley | 1 | -1/+1 |
2019-08-09 | dt-bindings: riscv: remove obsolete cpus.txt | Paul Walmsley | 2 | -162/+12 |
2019-08-09 | dt-bindings: Update the riscv,isa string description | Atish Patra | 1 | -0/+4 |
2019-07-21 | dt-bindings: riscv: Limit cpus schema to only check RiscV 'cpu' nodes | Rob Herring | 1 | -82/+61 |
2019-06-26 | dt-bindings: riscv: resolve 'make dt_binding_check' warnings | Paul Walmsley | 1 | -12/+14 |
2019-06-17 | dt-bindings: riscv: convert cpu binding to json-schema | Paul Walmsley | 1 | -0/+168 |
2019-06-17 | dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540 | Paul Walmsley | 1 | -0/+25 |
2019-05-17 | RISC-V: Add DT documentation for SiFive L2 Cache Controller | Yash Shah | 1 | -0/+51 |
2017-09-26 | dt-bindings: RISC-V CPU Bindings | Palmer Dabbelt | 1 | -0/+162 |