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2022-05-06arm64: dts: renesas: Add initial DTSI for RZ/V2M SoCPhil Edworthy1-0/+93
Details of the SoC can be found here: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220504094456.24386-3-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06Merge tag 'renesas-r9a09g011-dt-binding-defs-tag' into renesas-arm-dt-for-v5.19Geert Uytterhoeven1-0/+352
Renesas RZ/V2M DT Binding Definitions Clock definitions for the Renesas RZ/V2M (R9A09G011) SoC, shared by driver and DT source files.
2022-05-06arm64: dts: renesas: r8a779a0: Update to R-Car Gen4 compatible valuesGeert Uytterhoeven1-30/+44
Despite the name, R-Car V3U is the first member of the R-Car Gen4 family. Hence update the compatible properties in various device nodes to include family-specific compatible values for R-Car Gen4 instead of R-Car Gen3: - DMAC, - (H)SCIF, - I2C, - IPMMU, - WDT. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/73cea9d5e1a6639422c67e4df4285042e31c9fd5.1651497071.git.geert+renesas@glider.be
2022-05-06ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHYHerve Codina1-0/+12
Describe the PCI USB devices that are behind the PCI bridge, adding necessary links to the USB PHY device. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Link: https://lore.kernel.org/r/20220429134143.628428-8-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06ARM: dts: r9a06g032: Add USB PHY DT supportHerve Codina1-0/+6
Define the r9a06g032 generic part of the USB PHY device node. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Link: https://lore.kernel.org/r/20220429134143.628428-7-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06ARM: dts: r9a06g032: Add internal PCI bridge nodeHerve Codina1-0/+29
Add the device node for the r9a06g032 internal PCI bridge device. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Link: https://lore.kernel.org/r/20220429134143.628428-6-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06ARM: dts: r9a06g032: Describe the RTCMiquel Raynal1-0/+13
Describe the SoC RTC which counts time and provides alarm support. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20220429104602.368055-7-miquel.raynal@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06arm64: dts: renesas: Add interrupt-names to CANFD nodesGeert Uytterhoeven12-0/+12
The Renesas R-Car CAN-FD Controller on R-Car Gen3 and RZ/G2 SoCs has two interrupts. Add interrupt-names properties to all CAN-FD device nodes to identify the individual interrupts, so we can make this property a required property in the DT bindings. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/10eef1e20372af4a156b06df8e5124666ec7c6b6.1651512451.git.geert+renesas@glider.be
2022-05-06arm64: dts: renesas: r9a07g043: Add SPI Multi I/O Bus controller nodeBiju Das1-1/+8
Add SPI Multi I/O Bus controller node to R9A07G043 (RZ/G2UL) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220502190155.84496-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06arm64: dts: renesas: r9a07g043: Create thermal zone to support IPABiju Das1-0/+16
Setup a thermal zone driven by SoC temperature sensor. Create passive trip points and bind them to CPUFreq cooling device that supports power extension. Based on the work done by Dien Pham <dien.pham.ry@renesas.com> and others for r8a77990 SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220501112926.47024-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06arm64: dts: renesas: r9a07g043: Add TSU nodeBiju Das1-0/+26
Add TSU node to RZ/G2UL SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220501112926.47024-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06arm64: dts: renesas: r9a07g043: Add OPP tableBiju Das1-0/+28
Add OPP table for RZ/G2UL SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220501112926.47024-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06arm64: dts: renesas: r9a07g043: Add RSPI{0,1,2} nodesBiju Das1-1/+42
Add RSPI{0,1,2} nodes to R9A07G043 (RZ/G2UL) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220501112926.47024-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06arm64: dts: renesas: r9a07g054: Fix external clk node namesBiju Das1-4/+4
Add suffix '-clk' for can and extal clk node names and replace the clk node names audio_clk{1,2} with audio{1,2}-clk as per the device tree specification. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220428133156.18080-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06arm64: dts: renesas: r9a07g044: Fix external clk node namesBiju Das1-4/+4
Add suffix '-clk' for can and extal clk node names and replace the clk node names audio_clk{1,2} with audio{1,2}-clk as per the device tree specification. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220428133156.18080-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06ARM: dts: r9a06g032: Fix the NAND controller nodeMiquel Raynal1-0/+1
Add the missing power-domains property which is mandatory. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20220429105229.368728-3-miquel.raynal@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06ARM: dts: r9a06g032: Fill the UART DMA propertiesMiquel Raynal1-0/+10
UART 0 to 2 do not have DMA support, while UART 3 to 7 do. Fill the "dmas" and "dma-names" properties for each of these nodes. Please mind that these nodes go through the dmamux node which will redirect the requests to the right DMA controller. The first 4 cells of the "dmas" properties will be transferred as-is to the DMA controllers. The last 2 cells are consumed by the dmamux. Which means cell 0 and 4 are almost redundant, one giving the controller request ID and the other the dmamux channel which is a 1:1 translation of the request IDs, shifted by 16 when pointing to the second DMA controller. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20220421095323.101811-11-miquel.raynal@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06ARM: dts: r9a06g032: Describe the DMA routerMiquel Raynal1-0/+10
There is a dmamux on this SoC which allows picking two different sources for a single DMA request. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20220427095653.91804-10-miquel.raynal@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06ARM: dts: r9a06g032: Add the two DMA nodesMiquel Raynal1-0/+28
Describe the two DMA controllers available on this SoC. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20220427095653.91804-9-miquel.raynal@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06arm64: dts: renesas: Remove empty rgb output endpointsLaurent Pinchart18-32/+20
Endpoints node must have a remote-endpoint property, as endpoints only exist to model a link between ports. Drop the empty rgb output endpoints from SoC dtsi files, and declare them in the board dts instead. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Link: https://lore.kernel.org/r/20220424161228.8147-2-laurent.pinchart+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06arm64: dts: renesas: Remove empty lvds endpointsLaurent Pinchart12-30/+0
Endpoints node must have a remote-endpoint property, as endpoints only exist to model a link between ports. Drop the empty lvds endpoints from SoC dtsi files, they should be instead declared in the board dts or in overlays. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Link: https://lore.kernel.org/r/20220424161228.8147-1-laurent.pinchart+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06arm64: dts: renesas: rzg2ul-smarc: Enable USB2.0 supportBiju Das2-46/+11
Enable USB2.0 Host/Device support on RZ/G2UL SMARC EVK by adding usb{0,1} pincontrol entries to the soc-pinctrl dtsi and deleting the nodes which disabled it. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220429072400.23729-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06arm64: dts: renesas: rzg2ul-smarc: Enable AudioBiju Das2-0/+30
Enable Audio on RZ/G2UL SMARC EVK by adding ssi1 pincontrol entries to the soc-pinctrl dtsi and ssi1 and cpu sound_dai nodes to the board dtsi. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220429072400.23729-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06arm64: dts: renesas: rzg2l-smarc: Move ssi0 and cpu sound_dai nodes from ↵Biju Das4-14/+22
common dtsi On RZ/G2{L,LC} SoM module, the wm8978 audio codec is connected to ssi0, whereas on RZ/G2UL it is connected to ssi1. So move ssi0 and cpu sound_dai nodes from common dtsi to board specific dtsi. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220429072400.23729-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06arm64: dts: renesas: Add Renesas White Hawk boards supportYoshihiro Shimoda3-0/+69
Initial support for the Renesas White Hawk CPU and BreakOut boards. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220428135058.597586-4-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06arm64: dts: renesas: Add Renesas R8A779G0 SoC supportYoshihiro Shimoda1-0/+122
Add initial support for the Renesas R8A779G0 (R-Car V4H) SoC. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20220428135058.597586-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05dt-bindings: clock: Add r9a09g011 CPG Clock DefinitionsPhil Edworthy1-0/+352
Define RZ/V2M (R9A09G011) Clock Pulse Generator module clock outputs (CPG_CLK_ON* registers), and reset definitions (CPG_RST_* registers) in Section 48.5 ("Register Description") of the RZ/V2M Hardware User's Manual (Rev. 1.10, Sep. 2021). Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220503115557.53370-3-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-29Merge tag 'renesas-r8a779g0-dt-binding-defs-tag' into renesas-arm-dt-for-v5.19Geert Uytterhoeven2-0/+135
Renesas R-Car V4H DT Binding Definitions Clock and Power Domain definitions for the Renesas R-Car V4H (R8A779G0) SoC, shared by driver and DT source files.
2022-04-29arm64: dts: renesas: rzg2ul-smarc-som: Enable watchdogBiju Das1-0/+10
Enable watchdog{0,2} interfaces on RZ/G2UL SMARC EVK. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-14-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-29arm64: dts: renesas: rzg2ul-smarc-som: Enable OSTMBiju Das1-0/+8
Enable OSTM{1, 2} interfaces on RZ/G2UL SMARC EVK. OSTM0 is reserved for TF-A. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-13-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-29arm64: dts: renesas: rzg2ul-smarc: Enable CANFDBiju Das3-6/+36
Enable CANFD on RZ/G2UL SMARC platform. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-12-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-29arm64: dts: renesas: rzg2ul-smarc: Enable i2c{0,1} and wm8978Biju Das3-18/+18
Enable i2c{0,1} on RZ/G2UL SMARC EVK by deleting respective entries from board dts and adding pincontrol entries to the soc-pinctrl dtsi. Also enable wm8978 audio codec. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-8-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28arm64: dts: renesas: r9a07g043: Fillup the WDT{0,2} stub nodesBiju Das1-2/+22
Fillup the WDT{0,2} stub nodes in RZ/G2UL (R9A07G043) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28arm64: dts: renesas: r9a07g043: Fillup the OSTM{0,1,2} stub nodesBiju Das1-3/+21
Fillup the OSTM{0,1,2} stub nodes in RZ/G2UL (R9A07G043) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28arm64: dts: renesas: r9a07g043: Fillup the CANFD stub nodeBiju Das1-1/+30
Fillup the CANFD stub node in RZ/G2UL (R9A07G043) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28arm64: dts: renesas: r9a07g043: Add USB2.0 supportBiju Das1-8/+82
Add USB2.0 host and device support by filling usb phy control, phy, device and host stub nodes in RZ/G2UL SoC dtsi. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28arm64: dts: renesas: r9a07g043: Add SSI{1,2,3} nodes and fillup the SSI0 ↵Biju Das1-1/+79
stub node Add SSI{1,2,3} nodes and fillup the SSI0 stub node in RZ/G2UL (R9A07G043) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28arm64: dts: renesas: r9a07g043: Add I2C2 node and fillup the I2C{0,1,3} stub ↵Biju Das1-3/+70
nodes Add I2C2 node and fillup the I2C{0,1,3} stub nodes in RZ/G2UL (R9A07G043) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220425170530.200921-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28ARM: dts: r9a06g032: Add missing '#power-domain-cells'Herve Codina1-0/+1
Without '#power-domain-cells' property, power-domains cannot be used. This property is noted required in the device-tree binding. Add '#power-domain-cells' as needed. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Link: https://lore.kernel.org/r/20220422120850.769480-6-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-25dt-bindings: clock: Add r8a779g0 CPG Core Clock DefinitionsYoshihiro Shimoda1-0/+90
Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20220425064201.459633-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-25dt-bindings: power: Add r8a779g0 SYSC power domain definitionsYoshihiro Shimoda1-0/+45
Add power domain indices for R-Car V4H (r8a779g0). Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220425064201.459633-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-19ARM: dts: r9a06g032: Drop "arm,cortex-a7-timer" from timer nodeGeert Uytterhoeven1-2/+1
"make dtbs_check": arch/arm/boot/dts/r9a06g032-rzn1d400-db.dt.yaml: timer: compatible: 'oneOf' conditional failed, one must be fixed: ['arm,cortex-a7-timer', 'arm,armv7-timer'] is too long 'arm,cortex-a7-timer' is not one of ['arm,cortex-a15-timer'] 'arm,cortex-a7-timer' is not one of ['arm,armv7-timer'] 'arm,cortex-a7-timer' is not one of ['arm,armv8-timer'] From schema: Documentation/devicetree/bindings/timer/arm,arch_timer.yaml The Cortex-A7 timer should just declare compatibility with "arm,armv7-timer". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/a8e0cf00a983b4c539cdb1cfad5cc6b10b423c5b.1649680220.git.geert+renesas@glider.be
2022-04-19arm64: dts: renesas: r8a779f0: Add GPIO nodesGeert Uytterhoeven1-0/+60
Add device nodes for the General Purpose Input/Output (GPIO) blocks on the Renesas R-Car S4-8 (R8A779F0) SoC. Note that GPIO blocks 4-7 are not added, as they can only be accessed from the Control Domain. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/7fb68561026fa8bb5d9baf0596560c5c719a38cc.1649086225.git.geert+renesas@glider.be
2022-04-13arm64: dts: renesas: rzg2ul-smarc-som: Enable Ethernet on SMARC platformBiju Das2-1/+98
Enable Ethernet{0,1} interfaces on RZ/G2UL SMARC EVK. Ethernet0 pins are muxed with CAN0, CAN1, SSI1 and RSPI1 pins and Ethernet0 device selection is based on the SW1[3] switch position. Set SW1[3] to position OFF for selecting CAN0, CAN1, SSI1 and RSPI1. Set SW1[3] to position ON for selecting Ethernet0. This patch disables Ethernet0 on RZ/G2UL SMARC platform by default. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402081328.26292-8-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: rzg2ul-smarc-som: Enable eMMC on SMARC platformBiju Das2-0/+112
RZ/G2UL SoM has both 64GB eMMC and microSD connected to SDHI0. Both these interfaces are mutually exclusive and the SD0 device selection is based on SW1[2] on SoM module. Set SW1[2] to position OFF for selecting eMMC Set SW1[2] to position ON for selecting microSD This patch enables eMMC on RZ/G2UL SMARC platform by default. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402081328.26292-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: rzg2ul-smarc: Enable microSD on SMARC platformBiju Das4-11/+63
Enable the microSD card slot connected to SDHI1 on the RZ/G2UL SMARC platform by removing the sdhi1 override which disabled it, and by adding the necessary pinmux required for SDHI1. This patch also adds gpios property to vccq_sdhi1 regulator. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402081328.26292-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: r9a07g043: Add GbEthernet nodesBiju Das1-0/+40
Add Gigabit Ethernet{0,1} nodes to SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402081328.26292-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: r9a07g043: Add SDHI nodesBiju Das1-2/+24
Add SDHI{0, 1} nodes to RZ/G2UL SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402081328.26292-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: rzg2ul-smarc: Add scif0 and audio clk pinsBiju Das2-5/+25
Add scif0 and audio clk pins to soc pinctrl dtsi and drop deleting the pinctrl-0 and pinctrl-names properties for scif0 node so that we now actually make use of these properties for scif0. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402081328.26292-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13arm64: dts: renesas: r9a07g043: Fillup the pinctrl stub nodeBiju Das1-1/+7
Fillup the pinctrl(GPIO) stub node in RZ/G2UL SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402081328.26292-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-26 15:50:59 +0300