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2018-11-18arm64: dts: qcom: qcs404: add prng-ee nodeVinod Koul1-0/+7
RNG hardware in QCS404 features (Execution Environment) EE for HLOS to use, add the node for prng-ee for QCS404. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-18arm64: dts: qcom: qcs404: Add remoteproc nodesBjorn Andersson2-0/+105
Add the TrustZone based remoteproc nodes and their glink edges for adsp, cdsp and wcss. Enable them for EVB common DTS. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-18arm64: dts: qcom: qcs404: Add scm firmware nodeBjorn Andersson1-0/+7
Add the scm firmware node to QCS404 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-18arm64: dts: qcom: pms405: add gpiosVinod Koul1-0/+19
Add the GPIOs present on PMS405 chip. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-18arm64: dts: qcom: pms405: add rtc nodeVinod Koul1-0/+6
RTC is found on PMIC PMS405 and is same as other PMIC used, so add the rtc node with compatible as qcom,pm8941-rtc Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-18arm64: dts: qcom: qcs404: add spmi nodeVinod Koul2-0/+19
PMS405 is used in QCS405-EVB so include that with SPMI nodes Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-18arm64: dts: qcom: pms405: add spmi nodeVinod Koul1-0/+14
Add the pms405 DT file with spmi node. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-18arm64: dts: qcom: qcs404: Add sdcc1 nodeBjorn Andersson2-0/+81
Add the sdcc1 node and enable it for the QCS404-EVB. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-18arm64: dts: qcom: qcs404: Add TLMM pinctrl nodeBjorn Andersson1-0/+14
Add the QCS404 TLMM pinctrl node with its three tiles. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-18arm64: dts: qcom: qcs404: add smp2p nodesVinod Koul1-0/+60
Add the smp2p-adsp, smp2p-cdsp and smp2p-wcss nodes found in QCS404. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-18arm64: dts: qcom: qcs404: Add PMS405 RPM regulatorsBjorn Andersson1-0/+97
Add the RPM regulators found in PMS405 which is used in qcs404-evb Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-18arm64: dts: qcom: qcs404: Add RPM GLINK related nodesBjorn Andersson1-0/+44
Add RPM GLINK node and the RPM message ram, hwspinlock, APCS apps global and smem nodes it depends on. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-18arm64: dts: qcom: qcs404: Add reserved-memory regionsBjorn Andersson1-0/+41
Add the reserved memory regions in QCS404 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-18arm64: dts: qcom: qcs404-evb: add dts files for EVBsVinod Koul4-0/+38
QCS404 has two EVBs, EVB-1000 and EVB-4000. These boards are mostly similar with few differences in the peripherals used. So use a common qcs404-evb.dtsi which contains the common parts and use qcs404-evb-1000.dts and qcs404-evb-4000.dts for diffs Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-18arm64: dts: qcom: qcs404: add base dts filesVinod Koul1-0/+175
Add base dts files for QCS404 chipset along with cpu, timer, gcc and uart2 nodes. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-16ARM: dts: exynos: Clarify comment explaining purpose of Odroid XU3 DTSIKrzysztof Kozlowski2-2/+2
There are two common DTSI files for Exynos5422 Odroid XU3 family of boards. One is shared between all of them (XU3, XU3-Lite, XU4 and HC1) and the second skips HC1. Document this in the files. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2018-11-16ARM: dts: imx6: add thermal sensor and cooling cellsLucas Stach2-0/+4
This allows a board to specify a custom thermal zone configuration involving the SoC internal sensor, CPU and GPU nodes without having to change those nodes. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-11-16ARM: dts: imx6: RDU2: fix eGalax touchscreen nodeLucas Stach1-2/+3
Use the correct compatible for the new protocol used by the firmware on the touch controller, the GPIO wakeup isn't used in that case. Also eGalax touch needs axis swapping, just as with the RMI4 touch. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-11-16ARM: dts: imx6ul: ccimx6ulsom: Fix indentation on iomuxc nodesAlex Gonzalez1-4/+4
This patch corrects indentation problems in the gpmigrp and i2c1grp nodes. Signed-off-by: Alex Gonzalez <alex.gonzalez@digi.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-11-16ARM: dts: imx6ul: ccimx6ulsom: Add support for wireless SOM variantAlex Gonzalez1-0/+64
The wireless variants of the ConnecCore 6UL SOM include a Qualcomm QCA6564 wireless chip with dual WiFi and Bluetooth. Both the ConnectCore 6UL SBC Express and Pro boards fit a wireless SOM. The Wifi is connected through the SDIO interface on usdhc1 and the Bluetooth is connected via uart1. Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Alex Gonzalez <alex.gonzalez@digi.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-11-16ARM: dts: ls1021a: Add the status property disable PCIeXiaowei Bao1-0/+2
Add the status property disable the PCIe, the property will be enable by bootloader. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-11-16ARM: dts: imx6q-bx50v3: user-space watchdog GPIO configurationIan Ray4-28/+16
Leave b{4,6}50v3 GPIO expander pca953x pins P05,P10,P11 unconfigured as they are now used to implement an additional watchdog mechanism in user space. P10,P11 pins remain unused (and therefore hogged) on b850v3. Signed-off-by: Ian Ray <ian.ray@ge.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-11-15arm64: dts: meson-gx: add efuse pclkJerome Brunet2-0/+8
Add the required peripheral clock for the efuse device. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-15ARM: dts: meson8b: mxq: add the /chosen/stdout-path propertyMartin Blumenstingl1-0/+4
Support for this board is currently very limited. To debug any potential issues on this board the "earlycon" kernel parameter can be used (without any arguments). However, this requires the board to define a /chosen/stdout-path property in it's .dts. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-15ARM: dts: meson8: minix-neo-x8: add the /chosen/stdout-path propertyMartin Blumenstingl1-0/+4
Support for this board is currently very limited. To debug any potential issues on this board the "earlycon" kernel parameter can be used (without any arguments). However, this requires the board to define a /chosen/stdout-path property in it's .dts. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-15ARM: dts: meson6: atv1200: add the /chosen/stdout-path propertyMartin Blumenstingl1-0/+4
Support for Meson6 SoCs is currently very limited. It's often unclear why such a device does not boot. To debug this the "earlycon" kernel parameter can be used (without any arguments). However, this requires the board to define a /chosen/stdout-path property in it's .dts. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-15arm64: dts: sdm845: add prng-ee nodeVinod Koul1-0/+8
RNG hardware in SDM845 features (Execution Environment) EE for HLOS to use, add the node for prng-ee for sdm845. Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-15arm64: dts: msm8996: add prng-ee nodeVinod Koul1-0/+7
RNG hardware in 8996 features (Execution Environment) EE for HLOS to use, add the node for prng-ee for msm8996. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-15ARM: dts: rockchip: Fix rk3288-rock2 vcc_flash nameJohn Keeping1-1/+1
There is no functional change from this, but it is confusing to find two copies of vcc_sys and no vcc_flash when looking in /sys/class/regulator/*/name. Signed-off-by: John Keeping <john@metanate.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-11-15arm64: dts: renesas: Add CPU capacity-dmips-mhzGaku Inami2-0/+14
Set the capacity-dmips-mhz for R-Car Gen3 SoCs, that is based on dhrystone. The average in 10 times of dhrystone result as follows: r8a7795 SoC (A57x4 + A53x4) CPU max-freq dhrystone --------------------------------- A57 1500 MHz 11470943 lps/s A53 1200 MHz 4798583 lps/s r8a7796 SoC (A57x2 + A53x4) CPU max-freq dhrystone --------------------------------- A57 1500 MHz 11463526 lps/s A53 1200 MHz 4793276 lps/s Based on above, capacity-dmips-mhz values are calculated as follows: r8a7795 SoC A57 : 1024 / (11470943 / 1500) * (11470943 / 1500) = 1024 A53 : 1024 / (11470943 / 1500) * ( 4798583 / 1200) = 535 r8a7796 SoC A57 : 1024 / (11463526 / 1500) * (11463526 / 1500) = 1024 A53 : 1024 / (11463526 / 1500) * ( 4793276 / 1200) = 535 However, since each CPUs have different max frequencies, the final CPU capacities of A53 are scaled by this difference, the values are as follows. [r8a7795 SoC] $ cat /sys/devices/system/cpu/cpu*/cpu_capacity 1024 <---- CPU capacity of A57 1024 1024 1024 428 <---- CPU capacity of A53 428 428 428 [r8a7796 SoC] $ cat /sys/devices/system/cpu/cpu*/cpu_capacity 1024 <---- CPU capacity of A57 1024 428 <---- CPU capacity of A53 428 428 428 Signed-off-by: Gaku Inami <gaku.inami.xh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-15arm64: dts: renesas: Add CPU topology on R-Car Gen3 SoCsGaku Inami2-0/+58
This patch adds the "cpu-map" into r8a7795/r8a7796 composed of multi-cluster. This definition is used to parse the cpu topology. Signed-off-by: Gaku Inami <gaku.inami.xh@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-15arm64: dts: allwinner: h6: enable USB2 on Pine H64Icenowy Zheng1-0/+27
Pine H64 board has both the USB2 OTG pins and the USB2 host pins on H6 SoC wired out to USB Type-A ports. Enable them. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-11-15arm64: dts: allwinner: h6: add USB Vbus regulator for Pine H64Icenowy Zheng1-0/+10
The 5V output of the USB ports on Pine H64 is controlled via a GPIO. Add the USB Vbus regulator device tree node. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-11-15arm64: dts: allwinner: h6: add USB2-related device nodesIcenowy Zheng1-0/+82
Allwinner H6 has two USB2 ports, one OTG and one host-only. Add device tree nodes related to them. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-11-15dt-bindings: timer: meson6_timer: document the clock inputsMartin Blumenstingl1-0/+4
The Meson Timer IP has two clock inputs: - pclk which is used as "system clock" timebase of Timer E - xtal which is used for the 1us, 10us, 100us and 1ms timebases of Timer A, B, C, D and E The IP block has four internal dividers (XTAL is running at 24MHz): - "xtal div 24" for 1us resolution - "xtal div 240" for 10us resolution - "xtal div 2400" for 100us resolution - "xtal div 24000" for 1ms resolution Suggested-by: Jianxin Pan <jianxin.pan@amlogic.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-15dt-bindings: timer: meson6_timer: document all interruptsMartin Blumenstingl1-2/+5
The meson6_timer IP block supports four timers - each of them has it's own interrupt line. Update the documentation to reflect that all four interrupts should be passed. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-14arm64: dts: qcom: pm8998: Add die temperature channel node to the ADCMatthias Kaehlcke1-0/+5
Add a channel node for the die temperature to the ADC. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-14dt-bindings: iio: vadc: Add unit address to ADC channel node in exampleMatthias Kaehlcke1-1/+5
The node has a reg property, therefore its name should include a unit address. Also change the name from 'usb_id_nopull' to 'adc-chan', which is the preferred name for ADC channel nodes. Include headers for constants used in the example. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-14arm64: dts: sdm845: enable tsens thermal zonesAmit Kucheria1-0/+170
One thermal zone per cpu is defined Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Tested-by: Matthias Kaehlcke <mka@chromium.org> Acked-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-14arm64: dts: msm8916: Add camera thermal zoneAmit Kucheria1-0/+21
Initialise the camera thermal zone to export temperature to userspace. Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Acked-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-14arm64: dts: msm8916: Add gpu thermal zoneAmit Kucheria1-0/+20
Initialise the gpu thermal zone to export temperature to userspace. Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Acked-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-14arm64: dts: msm8916: thermal: Add "qcom,sensors" propertyAmit Kucheria1-0/+1
This new property allows the number of sensors to be configured from DT instead of being hardcoded in platform data. Use it. Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-14arm64: dts: msm8916: thermal: split address space into twoAmit Kucheria1-2/+3
We've earlier added support to split the register address space into TM and SROT regions. Split up the regmap address space into two for msm8916 that has a similar register layout. Since tsens-common.c/init_common() currently only registers one address space, the order is important (TM before SROT). This is OK since the code doesn't really use the SROT functionality yet. Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Acked-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-14Merge tag 'qcom-fixes-for-4.20-rc1' into arm64-for-4.21Andy Gross2-0/+8
Qualcomm ARM64 DT Fixes for 4.20-rc1 * Fix reserved gpio ranges for SDM845 and MSM8998
2018-11-14ARM: dts: msm8974: thermal: Add "qcom,sensors" propertyAmit Kucheria1-0/+1
This new property allows the number of sensors to be configured from DT instead of being hardcoded in platform data. Use it. Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-14ARM: dts: msm8974: thermal: split address space into twoAmit Kucheria1-2/+3
We've earlier added support to split the register address space into TM and SROT regions. Split up the regmap address space into two for msm8974 that has a similar register layout. Since tsens-common.c/init_common() currently only registers one address space, the order is important (TM before SROT). This is OK since the code doesn't really use the SROT functionality yet. Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Acked-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-14MAINTAINERS: Add entry for Qualcomm TSENS thermal driversAmit Kucheria1-0/+7
Create an entry for the TSENS drivers and mark them as maintained Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Acked-by: Rajendra Nayak <rnayak@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
2018-11-14ARM: dts: i.MX25: add the clocks for the EPIT blocksMartin Kaiser1-0/+4
The i.MX25 contains two EPIT (Enhanced Periodic Interrupt Timer) function blocks. Add their ipg and per clocks to the device tree. Signed-off-by: Martin Kaiser <martin@kaiser.cx> Acked-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-11-13ARM: dts: exynos: Add pin configuration for SD write protect on Odroid ↵Anand Moon2-1/+8
XU3/XU4/HC1 Add SD card write-protect pin configuration to be sure that it will be properly pulled down to indicate write access. Suggested-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2018-11-13ARM: dts: exynos: Update maximum frequency for eMMC to 200MHz on Odroid XU3/XU4Anand Moon1-0/+1
Set the eMMC max-frequency to 200MHz for optimal performance on Odroid XU3/XU4 family of boards. Signed-off-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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