| Age | Commit message (Collapse) | Author | Files | Lines |
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The interrupt-parent property is set in sun5i.dtsi, so there's no need to
repeat it.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
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Our main node for all the in-SoC controllers used to have a unit name. The
unit-name, in addition to being actually false, would not match any reg
property, which generates a warning.
Remove it in order to remove those warnings.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
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Using skeleton.dtsi will create a memory node that will generate a warning
in DTC. However, that node will be created by the bootloader, so we can
just remove it entirely in order to remove that warning.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
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Our oscillators clock names have a unit address, but no reg property, which
generates a warning in DTC. Change these names to remove those unit
addresses.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
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The simple-framebuffer nodes have a unit address, but no reg property which
generates a warning when compiling it with DTC.
Change the simple-framebuffer node names so that there is no warnings on
this anymore.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
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Our HDMI output endpoint on the A10 DTSI has a warning under DTC: "graph
node has single child node 'endpoint', #address-cells/#size-cells are not
necessary". Fix this by removing those properties.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
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Fix the 'unnecessary #address-cells/#size-cells without "ranges" or child
"reg" property' DTC warning for the gpio-keys DT node on A10 boards.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
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This pull request adds a compatible string to the DT necessary for the
firmware and VCHI driver to coordinate on using the correct cache line
size for the platform.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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The thermal controller implementation on Tegra194 is very similar to the
implementation on Tegra186. Add a compatible string for the new
generation.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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The lradc's analog reference voltage is set to 3.0 volt in the
hardware. This is more or less set in copper for at least lradc0. Set the
property in the dts to ensure the lradc is referenced properly.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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This patch enables audio via the SoC's internal audio codec. All
relevant device nodes are enabled, and the routing is set to match
the board design. MIC1 is routed to an onboard microphone, with MBIAS
providing power. MIC2 and HP are routed to the 3.5mm headset TRRS jack.
No phantom power is provided to the headset microphone.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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This patch adds the thermal device node and the thermal-zone for
the R8A77990 SoC.
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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This patch enables I2C DMA.
NOTE: I2C7 DMA is not supported by R-Car Gen3 Hardware User's Manual
Rev.0.80E.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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The Pinebook has a headphone jack tied to the HP headphone output of
the SoC, and internal speakers connected to the LINEOUT of the SoC,
through a standalone amplifier.
This commit enables I2S, digital and analog parts of audio codec on
Pinebook, along with a device node for the external amplifier.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
[wens@csie.org: dropped headphone_amp; added headphone amp regulator supply;
fixed speaker_amp node name and sound-name-prefix name]
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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This commit enables I2S, digital and analog parts of audiocodec on
Pine64 and SoPine boards.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
[wens@csie.org: Dropped headphone_amp; added headphone amp regulator supply]
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Add nodes for i2s, digital and analog parts of audiocodec on A64.
The routing paths listed are entries connecting the digital and analog
side of the audio codec together. Due to how device tree works, these
must be copied over to each board device tree, in addition to any board
level routes.
The oversampling rate is set to 128, so that when playing back 192 kHz
audio samples, the MCLK runs at the same rate as the module clock, at
24.576 MHz.
The user manual suggests using different oversampling rates for different
sample rates, but that's not possible without a platform-specific machine
driver.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
[wens@csie.org: Lowered oversampling rate to 128; expanded commit message]
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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This patch adds CMT{0|1|2|3} device nodes for r8a7796 SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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rsnd driver supports SSIU now, let's use it.
Then, BUSIF DMA settings on rcar_sound,ssi (= rxu, txu) are
no longer needed.
To avoid git merge timing issue / git bisect issue,
this patch doesn't remove it so far, but will be removed in
the future.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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This patch adds I2C-DVFS device node for the R8A77990 SoC.
v2
* Drop aliases update as in upstream it is not required to configure the
BD9571 PMIC for DDR backup, nor is the use of i2c are aliases desired.
* Do not describe the device as compatible with "renesas,rcar-gen3-iic" or
"renesas,rmobile-iic" fallback compat strings. The absence of automatic
transmission registers leads us to declare the r8a77990 IIC controller as
incompatible.
v2.1
* Reduced register range to reflect documentation
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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This patch adds CAN0,1 and CANFD device nodes for the r8a77990 SoC
and enables CANFD connected to CN10 on the E3 Ebisu board using the
R8A77990 SoC.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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DWC2 hardware module integrated in Samsung SoCs requires some quirks to
operate properly, so use Samsung SoC specific compatible to notify driver
to apply respective fixes.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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The T3/R40/V40 using the same sdk and config file in allwinner
sdk, it seem they are the same SOC just with different name, so
compatible with R40.
The t3-cqa3t-bv3 based on Allwinner T3 SoC, it has various connectors,
leds, buttons, and sell on:
https://item.taobao.com/item.htm?spm=2013.1.w4023-4203040713.25.62704cce7UCgLS&id=557154455330
It features:
- X-Powers AXP221s PMIC connected to i2c0
- 1/2 GB DDR3 DRAM
- 8 GB eMMC
- 2x USB 2.0 hosts
- 1x USB 2.0 OTG
- 2 LVDS connectors
- 24 bit RGB LCD connector
- HDMI output
- DVP camera interface (support 500w cmos camera)
- GPIO connectors
- 5 TTL uarts and 2 RS232 uarts
- 1 RS485 connector
- support i2c capacitive tp and usb infrared tp
- boot control, reset and user buttons
- 3.5mm headphone and 3.5mm mic jack
- 100M RJ45
- micro SD card slot
- DC power jack
- RCT power slot
- 1 CVBS TVIN
- 1 CVBS TVOUT
- 2 customer leds
- 1 buzzer
- 1 minipcie
- I2C output
- SPI output
- PCM output
- wifi and bt connector reserved.
Board info can find here:
https://github.com/Axl-zhang/Allwinner-V40-T3-R40-manual
Signed-off-by: Hao Zhang <hao5781286@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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Add Allwinner SoC T3 document and fix format.
Signed-off-by: Hao Zhang <hao5781286@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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This patch adds CAN{0,1} and CANFD controller nodes for the R8A77965 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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The Orange Pi Lite 2 and Orange Pi One Plus both have two LEDs, one red
and one green. These are driven directly by GPIO lines in an active high
arrangement. The red LED is labeled "power", so it is set to be on by
default.
Note that the default drive current for the GPIO lines makes the LEDs
very bright.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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The Orange Pi Lite 2 and Orange Pi One Plus share the same design for
their USB 2.0 ports. VBUS is directly tied to the board wide 5V rail,
which is also directly tied to the DC jack. There is no current limiting
in this design.
This patch enables all the USB 2.0 related device nodes, and sets the
VBUS regulator supplies and OTG ID detection GPIO.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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The Orange Pi Lite 2 and Orange Pi One Plus share the same design for
their USB 2.0 ports. VBUS is directly tied to the board wide 5V rail,
which is also directly tied to the DC jack. There is no current limiting
in this design. This 5V rail also supplies the various inputs to the
PMIC.
This patch adds a board wide 5V regulator and sets it as the input to
the PMIC inputs.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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The SoC-specific compatible should come before the fallback compatible
string when multiple compatible strings are present, but the sequence is
wrong currently on H6 EMAC node (A64 fallback before H6 compatible).
Fix the sequence.
Fixes: c8ced5516d23 ("arm64: allwinner: h6: add EMAC device nodes")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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Add support for Allwinner A64 has Mali-400MP2.
All interrupt lines are mentioned in the manual so used the same.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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Allwinner A64 has Mali-400MP2, so document the relevant compatible
as "allwinner,sun50i-a64-mali" along with reset line.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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Add sleep state for beeper pins. Without this there was a power
increase during the suspend and standby states on V3_3D domain.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add pinctrl settings so that gpio0 wake from suspend will be supported
using buttons SW4 and SW7. Also, add pinctrl configuration for 0x954,
spi0_d0, which is an unused pin brought out to a header on the board
that in it's default state also connects to the gpio used for wakeup,
gpio0_3, which affects the state of the pin and prevents a working
wakeup unless we set the mux to a different state.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Currently uart0 uses pinctrl config set by bootloader so
create default state that can be restored after a suspend
event.
Also, modify uart0 pinctrl to include RTS and CTS pins as by
default these are not in a mode for optimal power savings.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The pins used by debugss are not configued by default, place pulldowns
on the pins for maximum power savings during sleep.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
[t-kristo@ti.com: converted to use AM4372_IOPAD macro]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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There are several pins on this EVM that are not in use but they can
still draw power if misconfigured. Create a pinctrl entry for these pins
and configure each one for optimal power savings.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
[t-kristo@ti.com: converted to use AM4372_IOPAD macro]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add pinctrl data for ddr_vtt_toggle pin so that it is configured
for proper state during DeepSleep0. The pin should enter DS0 off mode
and hold the line low so VTT regulator is kept off while suspended.
It is also important for the PULLUP to be set on this pin so that
on removal of isolation, the VTT line is pulled high as a requirement
for bringing the DDR3 out of self-refresh.
This toggling is dependent on the IO isolation controlled by the
wkup_m3. Without placing the IOs into isolation the DS0 states set for
the pin will not be latched into effect during suspend.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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As long as the kernel cmdline has "earlycon" in it, this allows
seeing debug messages earlier and does not require DEBUG_LL to
be enabled.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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When compiling the kernel with Clang, the following warning appears:
arch/arm/boot/dts/omap3-gta04.dtsi:385:56: warning: '/*' within block comment [-Wcomment]
/* OMAP3_CORE1_IOPAD(0x2194, PIN_INPUT | MUX_MODE0) /* mcbsp_clks.mcbsp_clks */
^
1 warning generated.
Fixes: 3c10507a39e8 ("ARM: dts: omap3-gta04: add mcbsp (audio subsystem) pinmux")
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
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The EEPROM under I2C2 was put by mistake in the dts.
Remove it as it is not really present on the real hardware.
Fixes: ceef0396f367 ("ARM: dts: imx: add ZII RDU1 board")
Reported-by: Chris Healy <cphealy@gmail.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Chris Healy <cphealy@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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This patch adds PCI express channel 0 device node to the R8A77990 SoC
and enables PCIEC0 PCI express controller on the Ebisu board.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.
Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip
points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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PMS405 also features PON block, so add PON and PWRKEY nodes
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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We can use BAM DAM for serial UART data transfers, so add it
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Add the BAM DMA instance found in BLSP1 node of the QCS404
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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