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2021-03-11ARM: dts: stm32: Add Engicam i.Core STM32MP1 EDIMM2.2 Starter KitJagan Teki2-0/+48
Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board. Genaral features: - LCD 7" C.Touch - microSD slot - Ethernet 1Gb - Wifi/BT - 2x LVDS Full HD interfaces - 3x USB 2.0 - 1x USB 3.0 - HDMI Out - Mini PCIe - MIPI CSI - 2x CAN - Audio Out i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam. i.Core STM32MP1 needs to mount on top of this Evaluation board for creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-03-11dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 EDIMM2.2 Starter KitJagan Teki1-1/+3
i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam. EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive Evaluation Board from Engicam. i.Core STM32MP1 needs to mount on top of this Evaluation board for creating complete i.Core STM32MP1 EDIMM2.2 Starter Kit. Add bindings for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-03-11ARM: dts: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0Jagan Teki2-0/+48
Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier board. Genaral features: - Ethernet 10/100 - Wifi/BT - USB Type A/OTG - Audio Out - CAN - LVDS panel connector i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam. i.Core STM32MP1 needs to mount on top of this Carrier board for creating complete i.Core STM32MP1 C.TOUCH 2.0 board. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-03-11ARM: dts: stm32: Add Engicam i.Core STM32MP1 SoMJagan Teki1-0/+196
i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam. General features: - STM32MP157A - Up to 1GB DDR3L - 4GB eMMC - 10/100 Ethernet - USB 2.0 Host/OTG - I2S - MIPI DSI to LVDS - rest of STM32MP157A features i.Core STM32MP1 needs to mount on top of Engicam baseboards for creating complete platform solutions. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-03-11dt-bindings: arm: stm32: Add Engicam i.Core STM32MP1 C.TOUCH 2.0Jagan Teki1-0/+6
i.Core STM32MP1 is an EDIMM SoM based on STM32MP157A from Engicam. C.TOUCH 2.0 is a general purpose carrier board with capacitive touch interface support. i.Core STM32MP1 needs to mount on top of this Carrier board for creating complete i.Core STM32MP1 C.TOUCH 2.0 board. Add bindings for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-03-11ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OFJagan Teki2-0/+155
7" OF is a capacitive touch 7" Open Frame panel solutions with - 7" AUO B101AW03 LVDS panel - EDT, FT5526 Touch MicroGEA STM32MP1 is a STM32MP157A based Micro SoM. MicroDev 2.0 is a general purpose miniature carrier board with CAN, LTE and LVDS panel interfaces. MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0 7" Open Frame Solution board. Add support for it. Signed-off-by: Matteo Lisi <matteo.lisi@engicam.com> Signed-off-by: Francesco Utel <francesco.utel@engicam.com> Signed-off-by: Mirko Ardinghi <mirko.ardinghi@engicam.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-03-11dt-bindings: arm: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 7" OFJagan Teki1-1/+3
MicroGEA STM32MP1 is a STM32MP157A based Micro SoM. MicroDev 2.0 is a general purpose miniature carrier board with CAN, LTE and LVDS panel interfaces. 7" OF is a capacitive touch 7" Open Frame panel solutions. MicroGEA STM32MP1 needs to mount on top of MicroDev 2.0 board with pluged 7" OF for creating complete MicroGEA STM32MP1 MicroDev 2.0 7" Open Frame Solution board. Add bindings for it. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-03-11ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0 boardJagan Teki2-0/+56
MicroDev 2.0 is a general purpose miniature carrier board with CAN, LTE and LVDS panel interfaces. Genaral features: - Ethernet 10/100 - USB Type A - Audio Out - microSD - LVDS panel connector - Wifi/BT (option) - UMTS LTE with sim connector (option) MicroGEA STM32MP1 is a STM32MP157A based Micro SoM. MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board. Add support for it. Signed-off-by: Matteo Lisi <matteo.lisi@engicam.com> Signed-off-by: Francesco Utel <francesco.utel@engicam.com> Signed-off-by: Mirko Ardinghi <mirko.ardinghi@engicam.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-03-11ARM: dts: stm32: Add Engicam MicroGEA STM32MP1 SoMJagan Teki1-0/+148
MicroGEA STM32MP1 is a STM32MP157A based Micro SoM. General features: - STM32MP157AAC - Up to 1GB DDR3L-800 - 512MB Nand flash - I2S MicroGEA STM32MP1 needs to mount on top of Engicam MicroDev carrier boards for creating complete platform solutions. Add support for it. Signed-off-by: Matteo Lisi <matteo.lisi@engicam.com> Signed-off-by: Francesco Utel <francesco.utel@engicam.com> Signed-off-by: Mirko Ardinghi <mirko.ardinghi@engicam.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-03-11dt-bindings: arm: stm32: Add Engicam MicroGEA STM32MP1 MicroDev 2.0Jagan Teki1-0/+7
MicroGEA STM32MP1 is a STM32MP157A based Micro SOM. MicroDev 2.0 is a general purpose miniature carrier board with CAN, LTE and LVDS panel interfaces. MicroGEA STM32MP1 needs to mount on top of this MicroDev 2.0 board for creating complete MicroGEA STM32MP1 MicroDev 2.0 Carrier board. Add bindings for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-03-11ARM: dts: stm32: fix usart 2 & 3 pinconf to wake up with flow controlValentin CARON - foss1-3/+18
Modify usart 2 & 3 pins to allow wake up from low power mode while the hardware flow control is activated. UART RTS pin need to stay configure in idle mode to receive characters in order to wake up. Fixes: 842ed898a757 ("ARM: dts: stm32: add usart2, usart3 and uart7 pins in stm32mp15-pinctrl") Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-03-10arm64: dts: broadcom: bcm4908: fix switch parent node nameRafał Miłecki1-1/+1
Ethernet switch and MDIO are grouped using "simple-bus". It's not allowed to use "ethernet-switch" node name as it isn't a switch. Replace it with "bus". Fixes: 527a3ac9bdf8 ("arm64: dts: broadcom: bcm4908: describe internal switch") Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-03-10arm64: dts: broadcom: bcm4908: describe firmware partitionsRafał Miłecki2-1/+12
BCM4908 bootloader supports multiple firmware partitions and has its own bindings defined for them. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-03-10arm64: dts: broadcom: bcm4908: add remaining Netgear R8000P LEDsRafał Miłecki1-1/+49
There are a few more GPIO connected LEDs there didn't get described initially. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-03-10arm64: dts: mediatek: mt8183: evb: Add domain supply for mfgHsin-Yi Wang1-0/+4
Add domain supply node for mt8183-evb Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Link: https://lore.kernel.org/r/20210201093049.87285-1-hsinyi@chromium.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-03-10Merge tags 'genpd-dts-dra7', 'genpd-dts-omap4' and 'genpd-dts-omap5' into ↵Tony Lindgren5-167/+321
omap-for-v5.13/dts-genpd Merge together genpd related dts changes to provide base for dropping the legacy data to prevent merge conflicts and to send dts changes separately.
2021-03-10ARM: dts: Configure simple-pm-bus for omap5 l3Tony Lindgren1-1/+5
We can now probe interconnects with device tree only configuration using simple-pm-bus and genpd. Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure simple-pm-bus for omap5 l4_cfgTony Lindgren1-8/+11
We can now probe interconnects with device tree only configuration using simple-pm-bus and genpd. Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure simple-pm-bus for omap5 l4_perTony Lindgren1-3/+6
We can now probe interconnects with device tree only configuration using simple-pm-bus and genpd. Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure simple-pm-bus for omap5 l4_wkupTony Lindgren1-4/+7
We can now probe interconnects with device tree only configuration using simple-pm-bus and genpd. Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Move omap5 l3-noc to a separate nodeTony Lindgren1-6/+10
In preparation for probing l3 with simple-pm-bus and genpd, we must move l3 noc to a separate node. This is to prevent omap_l3_noc.c driver from claiming the whole l3 instance before simple-pm-bus has a chance to probe. Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Move omap5 mmio-sram out of l3 interconnectTony Lindgren1-5/+9
We need mmio-sram early for omap4_sram_init() for IO barrier init, and will be moving l3 interconnect to probe with simple-pm-bus that probes at module_init() time. So let's move mmio-sram out of l3 to prepare for that. Otherwise we will get the following after probing the interconnects with simple-pm-bus: omap4_sram_init:Unable to get sram pool needed to handle errata I688 Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure interconnect target module for omap5 sataTony Lindgren2-15/+25
We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" peroperty to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Note that the old sysc register offset is wrong, the real offset is at 0x1100 as listed in TRM for SATA_SYSCONFIG register. Looks like we've been happily using sata on the bootloader configured sysconfig register and nobody noticed. Also the old register range for SATAMAC_wrapper registers is wrong at 7 while it should be 8. But that too seems harmless. There is also an L3 parent interconnect range that we don't seem to be using. That can be added as needed later on. Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure interconnect target module for omap5 gpmcTony Lindgren1-16/+33
We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" property to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure interconnect target module for omap5 mpuTony Lindgren1-13/+15
We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure interconnect target module for omap5 emifTony Lindgren1-20/+42
We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" property to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure interconnect target module for omap5 dmmTony Lindgren1-4/+17
We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" property to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Prepare for simple-pm-bus for omap4 l3Tony Lindgren1-0/+4
Let's configure omap4 l3 for power-domain and clocks in preparation for starting to use simple-pm-bus. We will flip over to using simple-pm-bus later on after dropping the legacy data for all the devices on l3 interconnect. Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure simple-pm-bus for omap4 l4_cfgTony Lindgren1-8/+11
We can now probe interconnects with device tree only configuration using simple-pm-bus and genpd. Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure simple-pm-bus for omap4 l4_perTony Lindgren1-3/+6
We can now probe interconnects with device tree only configuration using simple-pm-bus and genpd. Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure simple-pm-bus for omap4 l4_wkupTony Lindgren1-4/+7
We can now probe interconnects with device tree only configuration using simple-pm-bus and genpd. Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Move omap4 l3-noc to a separate nodeTony Lindgren1-6/+10
In preparation for probing l3 with simple-pm-bus and genpd, we must move l3 noc to a separate node. This is to prevent omap_l3_noc.c driver from claiming the whole l3 instance before simple-pm-bus has a chance to probe. Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Move omap4 mmio-sram out of l3 interconnectTony Lindgren1-5/+9
We need mmio-sram early for omap4_sram_init() for IO barrier init, and will be moving l3 interconnect to probe with simple-pm-bus that probes at module_init() time. So let's move mmio-sram out of l3 to prepare for that. Otherwise we will get the following after probing the interconnects with simple-pm-bus: omap4_sram_init:Unable to get sram pool needed to handle errata I688 Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure interconnect target module for omap4 mpuTony Lindgren1-13/+15
We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure interconnect target module for omap4 debugssTony Lindgren2-18/+27
We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" property to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure interconnect target module for omap4 emifTony Lindgren1-18/+40
We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" property to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure interconnect target module for omap4 dmmTony Lindgren1-4/+17
We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" property to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Let's also use GIC_SPI and IRQ_TYPE_LEVEL_HIGH defines while at it. Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure power-domain for omap4 dts issTony Lindgren1-0/+1
Configure power-domain for omap4 dts iss in preparation to probing devices with simple-pm-bus and genpd. Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure power-domain for omap4 gfxTony Lindgren1-0/+1
Configure power-domain for omap4 dts gfx in preparation to probing devices with simple-pm-bus and genpd. Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure simple-pm-bus for dra7 l3Tony Lindgren1-2/+4
We can now probe interconnects with device tree only configuration using simple-pm-bus and genpd. Tested-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure simple-pm-bus for dra7 l4_cfgTony Lindgren1-4/+7
We can now probe interconnects with device tree only configuration using simple-pm-bus and genpd. Tested-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure simple-pm-bus for dra7 l4_per3Tony Lindgren1-2/+5
We can now probe interconnects with device tree only configuration using simple-pm-bus and genpd. Tested-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure simple-pm-bus for dra7 l4_per2Tony Lindgren1-2/+5
We can now probe interconnects with device tree only configuration using simple-pm-bus and genpd. Tested-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure simple-pm-bus for dra7 l4_per1Tony Lindgren1-3/+6
We can now probe interconnects with device tree only configuration using simple-pm-bus and genpd. Tested-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure simple-pm-bus for dra7 l4_wkupTony Lindgren1-5/+8
We can now probe interconnects with device tree only configuration using simple-pm-bus and genpd. Tested-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure interconnect target module for dra7 dmmTony Lindgren1-4/+17
We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" peroperty to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Tested-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure interconnect target module for dra7 mpuTony Lindgren1-12/+15
We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Tested-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure interconnect target module for dra7 sataTony Lindgren2-15/+26
We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" peroperty to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Note that the old sysc register offset is wrong, the real offset is at 0x1100 as listed in TRM for SATA_SYSCONFIG register. Looks like we've been happily using sata on the bootloader configured sysconfig register and nobody noticed. Also the old register range for SATAMAC_wrapper registers is wrong at 7 while it should be 8. But that too seems harmless. There is also an L3 parent interconnect range that we don't seem to be using. That can be added as needed later on. Tested-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Configure interconnect target module for dra7 qspiTony Lindgren1-12/+29
We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" peroperty to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Cc: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-10ARM: dts: Move dra7 l3 noc to a separate nodeTony Lindgren1-5/+9
In order to prepare for probing l3 with genpd, we need to move l3 noc into a separate node for l3 interconnect to have it's own regs, and to avoid it claiming more than it needs for the io regions. Tested-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-01 09:07:25 +0300