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2021-03-25arm64: dts: rockchip: add new watchdog compatible to rk3308.dtsiJohan Jonker1-1/+1
The watchdog compatible strings are suppose to be SoC orientated. In the more recently added Rockchip rk3308.dtsi file only the fallback string "snps,dw-wdt" is used, so add the new compatible string: "rockchip,rk3308-wdt", "snps,dw-wdt" make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20201218120534.13788-5-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-03-25arm64: dts: rockchip: add new watchdog compatible to px30.dtsiJohan Jonker1-1/+1
The watchdog compatible strings are suppose to be SoC orientated. In the more recently added Rockchip px30.dtsi file only the fallback string "snps,dw-wdt" is used, so add the new compatible string: "rockchip,px30-wdt", "snps,dw-wdt" make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20201218120534.13788-4-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-03-24arm64: dts: rockchip: enable dwc3 usb for A95X Z2Johan Jonker1-0/+5
Enable dwc3 usb for A95X Z2. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20210209192350.7130-8-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-03-24arm64: dts: rockchip: add rk3328 dwc3 usb controller nodeCameron Nemo1-0/+19
RK3328 SoCs have one USB 3.0 OTG controller which uses DWC_USB3 core's general architecture. It can act as static xHCI host controller, static device controller, USB 3.0/2.0 OTG basing on ID of USB3.0 PHY. Signed-off-by: William Wu <william.wu@rock-chips.com> Signed-off-by: Cameron Nemo <cnemo@tutanota.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20210209192350.7130-7-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-03-24ARM: dts: motorola-cpcap-mapphone: Prepare for dtbs_check parsingSebastian Reichel1-31/+28
'<&gpio1 parameters &gpio2 parameters>' and '<&gpio1 parameters>, <&gpio2 parameters>' result in the same DTB, but second format has better source code readability. Also 'dtbs_check' currently uses this format to determine the amount of items specified, so using this syntax is needed to successfully verify the devicetree source against a DT schema format. Cc: linux-omap@vger.kernel.org Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-24ARM: dts: am33xx-l4: fix tscadc@0 node indentationDario Binacchi1-14/+14
Fix the broken indentation of tscadc@0 node. Signed-off-by: Dario Binacchi <dariobin@libero.it> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-24ARM: dts: omap3-echo: Add ath6kl nodeAndré Hentschel1-0/+7
Add ath6kl node. Signed-off-by: André Hentschel <nerv@dawncrow.de> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-24ARM: dts: omap3-echo: Update LED configurationAndré Hentschel1-140/+329
Update LED configuration. Signed-off-by: André Hentschel <nerv@dawncrow.de> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-24ARM: dts: am335x-pocketbeagle: unique gpio-line-namesDrew Fustini1-70/+70
Based on linux-gpio discussion [1], it is best practice to make the gpio-line-names unique. Generic names like "[ethernet]" are replaced with the name of the unique signal on the AM3358 SoC ball corresponding to the gpio line. "[NC]" is also renamed to the standard "NC" name to represent "not connected". [1] https://lore.kernel.org/linux-gpio/20201216195357.GA2583366@x1/ Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Signed-off-by: Drew Fustini <drew@beagleboard.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
2021-03-24ARM: tegra: Specify tps65911 as wakeup sourceDmitry Osipenko6-0/+6
Specify TPS65911 as wakeup source on Tegra devices in order to allow its RTC to wake up system from suspend by default instead of requiring wakeup to be enabled manually via sysfs. Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30 Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30 Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-03-24ARM: tegra: Specify memory suspend OPP in device-treeDmitry Osipenko3-0/+9
Specify memory suspend OPP in a device-tree, just for consistency. Now memory will always suspend on the same frequency. Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30 Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30 Tested-by: Dmitry Osipenko <digetx@gmail.com> # A500 T20 and Nexus7 T30 Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-03-24ARM: tegra: Specify CPU suspend OPP in device-treeDmitry Osipenko2-0/+5
Specify CPU suspend OPP in a device-tree, just for consistency. Now CPU will always suspend on the same frequency. Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30 Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30 Tested-by: Dmitry Osipenko <digetx@gmail.com> # A500 T20 and Nexus7 T30 Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-03-24ARM: tegra: ouya: Specify all CPU cores as cooling devicesDmitry Osipenko1-4/+11
If CPU0 is unplugged the cooling device can not rebind to CPU1. And if CPU0 is plugged in again, the cooling device may fail to initialize. If the CPUs are mapped with the physical CPU0 to Linux numbering CPU1, the cooling device mapping will fail. Hence specify all CPU cores as a cooling devices in the device-tree. Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Matt Merhar <mattmerhar@protonmail.com> Suggested-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-03-24ARM: tegra: nexus7: Specify all CPU cores as cooling devicesDmitry Osipenko1-4/+10
If CPU0 is unplugged the cooling device can not rebind to CPU1. And if CPU0 is plugged in again, the cooling device may fail to initialize. If the CPUs are mapped with the physical CPU0 to Linux numbering CPU1, the cooling device mapping will fail. Hence specify all CPU cores as a cooling devices in the device-tree. Suggested-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-03-24ARM: tegra: acer-a500: Rename avdd to vdda of touchscreen nodeDmitry Osipenko1-1/+1
Rename avdd supply to vdda of the touchscreen node. The old supply name was incorrect. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-03-24ARM: tegra: acer-a500: Specify all CPU cores as cooling devicesDmitry Osipenko1-2/+4
If CPU0 is unplugged the cooling device can not rebind to CPU1. And if CPU0 is plugged in again, the cooling device may fail to initialize. If the CPUs are mapped with the physical CPU0 to Linux numbering CPU1, the cooling device mapping will fail. Hence specify all CPU cores as a cooling devices in the device-tree. Suggested-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-03-24ARM: tegra: acer-a500: Reduce thermal throttling hysteresis to 0.2CDmitry Osipenko1-1/+1
The 2C hysteresis is a bit too high, although CPU never gets hot on A500. Nevertheless, let's reduce thermal throttling hysteresis to 0.2C, which is a much more reasonable value. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-03-24ARM: tegra: acer-a500: Enable core voltage scalingDmitry Osipenko1-2/+2
Allow lower core voltages on Acer A500. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-03-24ARM: tegra: paz00: Enable full voltage scaling ranges for CPU and Core domainsDmitry Osipenko1-7/+7
Enable full voltage scaling ranges for CPU and Core power domains. Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-03-24ARM: tegra: cardhu: Support CPU thermal throttlingDmitry Osipenko1-1/+42
Enable CPU thermal throttling on Tegra30 Cardhu board. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-03-24ARM: tegra: cardhu: Support CPU frequency and voltage scaling on all board ↵Dmitry Osipenko2-51/+37
variants Enable CPU frequency and voltage scaling on all Tegra30 Cardhu board variants. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-03-24ARM: tegra: ventana: Support CPU thermal throttlingDmitry Osipenko1-2/+39
Enable CPU thermal throttling on Tegra20 Ventana board. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-03-24ARM: tegra: ventana: Support CPU and Core voltage scalingDmitry Osipenko1-9/+28
Support CPU and Core voltage scaling on Tegra20 Ventana board. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-03-24dt-bindings: phy: tegra-xusb: Add nvidia,pmc propJC Kuo1-0/+1
This commit describes the "nvidia,pmc" property for Tegra210 tegra-xusb PHY driver. It is a phandle and specifier referring to the Tegra210 pmc@7000e400 node. Signed-off-by: JC Kuo <jckuo@nvidia.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-03-24arm64: dts: renesas: r8a77961: Add VIN and CSI-2 device nodesNiklas Söderlund1-10/+304
Add device nodes for VIN and CSI-2 to R-Car M3-W+ r8a77961 device tree. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: LUU HOAI <hoai.luu.ub@renesas.com> Link: https://lore.kernel.org/r/20210312131020.1747344-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-03-24ARM: dts: koelsch: Configure pull-up for SOFT_SW GPIO keysGeert Uytterhoeven1-0/+8
The GPIO pins connected to the 4 Software Switches ("SOFT_SW", SW2) do not have external pull-up resistors, but rely on internal pull-ups being enabled. Fortunately this is satisfied by the initial state of these pins. Make this explicit by enabling bias-pull-up, to remove the dependency on initial state and/or boot loader configuration. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210303132941.3938516-1-geert+renesas@glider.be
2021-03-24ARM: dts: sun8i: h3: beelink-x2: Add power buttonJernej Skrabec1-0/+11
Beelink X2 has power button. Add node for it. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210323204341.28825-1-jernej.skrabec@siol.net
2021-03-23arm64: tegra: Fix mmc0 alias for Jetson Xavier NXJon Hunter3-1/+8
There are two variants of the Jetson Xavier NX platform; one has an eMMC and one as a micro SD-card slot. The SDHCI controller used by each variant is different, however, the current device-tree for both Xavier NX boards have the same SDHCI controller defined as 'mmc0' in the device-tree alias node. Fix this by correcting the 'mmc0' alias for the SD-card variant. Fixes: 3f9efbbe57bc ("arm64: tegra: Add support for Jetson Xavier NX") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-03-23arm64: tegra: Set fw_devlink=on for Jetson TX2Jon Hunter1-1/+1
Commit 5d25c476f252 ("Revert "arm64: tegra: Disable the ACONNECT for Jetson TX2"") re-enabled the Tegra ADMA and ACONNECT drivers to support audio on Jetson TX2. However, this revert was dependent upon commit e590474768f1 ("driver core: Set fw_devlink=on by default") and without this commit, enabling the ACONNECT is causing resume from system suspend to fail on Jetson TX2. Resume fails because the ACONNECT driver is being resumed before the BPMP driver, and the ACONNECT driver is attempting to power on a power-domain that is provided by the BPMP. Commit e590474768f1 ("driver core: Set fw_devlink=on by default") has since been temporarily reverted while some issues are being investigated. This is causing resume from system suspend on Jetson TX2 to fail again. Rather than disable the ACONNECT driver again, fix this by setting fw_devlink is set to 'on' for Jetson TX2 in the bootargs specified in device-tree. Fixes: 5d25c476f252 ("Revert arm64: tegra: Disable the ACONNECT for Jetson TX2") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-03-23arm64: tegra: Add unit-address for ACONNECT on Tegra186Thierry Reding2-2/+2
The ACONNECT device tree node has a unit-address on all other SoC generations and there's really no reason not to have it on Tegra186. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-03-23Merge tag 'renesas-arm-dt-for-v5.13-tag1' of ↵Arnd Bergmann55-506/+619
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt Renesas ARM DT updates for v5.13 - OV7725 camera support for the iWave RainboW Qseven board (G21D), and its camera expansion board, - Add mmc aliases to fix /dev/mmcblkN order, - HDMI Display support for the R-Car Starter Kit Pro with R-Car M3-W+, - Support for running upstream kernels on the RZA2MEVB board, using the SDRAM present on the sub-board, - I2C EEPROM support for the Falcon development board, - Timer, thermal sensor, and CAN support for the R-Car V3U SoC. - Miscellaneous fixes and improvements. * tag 'renesas-arm-dt-for-v5.13-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: dts: renesas: r8a77980: Fix vin4-7 endpoint binding arm64: dts: renesas: r8a77961: Add CAN nodes arm64: dts: renesas: r8a779a0: Add CMT support arm64: dts: renesas: r8a779a0: Add thermal support arm64: dts: renesas: r8a779a0: Add TMU support arm64: dts: renesas: falcon: Add Ethernet sub-board arm64: dts: renesas: falcon: Add CSI/DSI sub-board arm64: dts: renesas: falcon: Add I2C EEPROM nodes ARM: dts: rza2mevb: Upstream Linux requires SDRAM arm64: dts: renesas: Consolidate Salvator-X(S) HDMI0 handling arm64: dts: renesas: Add mmc aliases into board dts files arm64: dts: renesas: r8a77961-ulcb: add HDMI Display support ARM: dts: renesas: Add mmc aliases into R-Car Gen2 board dts files arm64: dts: renesas: Group tuples in pin control properties arm64: dts: renesas: Group tuples in playback and capture properties ARM: dts: renesas: Group tuples in pin control properties ARM: dts: renesas: Group tuples in playback and capture properties ARM: dts: renesas: Group tuples in APMU cpus properties ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Add support for 8-bit ov7725 sensors ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Separate out ov5640 nodes Link: https://lore.kernel.org/r/20210319085146.2709844-3-geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-03-22arm64: dts: ti: k3-am642: reserve gpio in mcu domain for firmware usageAswath Govindraju2-0/+10
The gpio0 subsystem present in MCU domain might be used by firmware and is not pinned out in evm/sk. Therefore, reserve it for MCU firmware. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210319051950.17549-3-a-govindraju@ti.com
2021-03-22arm64: dts: ti: k3-am64: Add GPIO DT nodesAswath Govindraju2-0/+72
Add device tree nodes for GPIO modules and interrupt controller in main and mcu domains. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210319051950.17549-2-a-govindraju@ti.com
2021-03-22arm64: dts: renesas: falcon: Move AVB0 to main DTSGeert Uytterhoeven2-34/+37
The Ethernet PHY for the first AVB instance is located on the Falcon BreakOut board. Hence move its description from the DTS file that describes the CPU board to the main Falcon DTS file. Fixes: e8ac55a5e70a9522 ("arm64: dts: renesas: falcon: Add Ethernet-AVB0 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210316154705.2433528-4-geert+renesas@glider.be
2021-03-22arm64: dts: renesas: falcon: Move watchdog config to CPU board DTSGeert Uytterhoeven2-5/+5
The 32 kHz oscillator driving the R-Car V3U watchdog is located on the Falcon CPU board. Hence move the watchdog configuration from the main Falcon DTS file to the DTS file that describes the CPU board. Fixes: d207dc500bbcf8c6 ("arm64: dts: renesas: falcon: Enable watchdog timer") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210316154705.2433528-3-geert+renesas@glider.be
2021-03-22arm64: dts: renesas: falcon: Move console config to CPU board DTSGeert Uytterhoeven2-5/+8
The serial console is located on the Falcon CPU board. Hence move serial console configuration from the main Falcon DTS file to the DTS file that describes the CPU board. Fixes: 63070d7c2270e8de ("arm64: dts: renesas: Add Renesas Falcon boards support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20210316154705.2433528-2-geert+renesas@glider.be
2021-03-22rockchip: rk3399: Add support for FriendlyARM NanoPi R4STianling Shen2-0/+134
This adds support for the NanoPi R4S from FriendlyArm. Rockchip RK3399 SoC 1GB DDR3 or 4GB LPDDR4 RAM Gigabit Ethernet (WAN) Gigabit Ethernet (PCIe) (LAN) USB 3.0 Port x 2 MicroSD slot Reset button WAN - LAN - SYS LED Co-developed-by: Jensen Huang <jensenhuang@friendlyarm.com> Signed-off-by: Jensen Huang <jensenhuang@friendlyarm.com> [minor adjustments] Co-developed-by: Marty Jones <mj8263788@gmail.com> Signed-off-by: Marty Jones <mj8263788@gmail.com> [further adjustments, fixed format issues] Signed-off-by: Tianling Shen <cnsztl@gmail.com> Link: https://lore.kernel.org/r/20210319051627.814-2-cnsztl@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-03-22dt-bindings: Add doc for FriendlyARM NanoPi R4STianling Shen1-0/+1
Add devicetree binding documentation for the FriendlyARM NanoPi R4S. Signed-off-by: Tianling Shen <cnsztl@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210319051627.814-1-cnsztl@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-03-21arm64: dts: rockchip: add phandle to timer0 on rk3368Heiko Stuebner1-1/+1
While the kernel doesn't care s0 much right now, bootloaders like u-boot need to refine the node on their side, so to make life easier for everyone add the timer0 phandle for timer0. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20210209103408.2302218-1-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-03-21arm64: dts: rockchip: add infrared receiver node to rockpro64Thomas Schneider1-0/+13
This adds the RockPro64’s infrared receiver to its dtsi. The configuration is almost the same as on rk3328-rock64, except for the GPIO pins, and thus adapted from there. Signed-off-by: Thomas Schneider <qsx@chaotikum.eu> Link: https://lore.kernel.org/r/20210310122821.126408-1-qsx@chaotikum.eu Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-03-21arm64: dts: rockchip: drop separate opp table on rk3399-pumaHeiko Stuebner1-51/+0
We're using OPPs with a range now, so the fact that the cpu regulator on puma can't provide the needed 5mV steps requested in the minimal voltage values can be handled automatically by the opp framework. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20210225133322.3420724-3-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-03-21arm64: dts: rockchip: used range'd gpu opps on rk3399Heiko Stuebner1-6/+6
Similar to the cpu opps, also use opps with a range on the gpu. (min, preferred, max). The voltage just needs to be higher than the minimum and this allows the regulator more freedom if it can't provide the exact voltage specified, but just say 5mV higher, as can be seen on rk3399-puma which fails to scale panfrost voltages nearly completely. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20210225133322.3420724-2-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-03-21arm64: dts: rockchip: synchronize rk3399 opps with vendor kernelHeiko Stuebner1-16/+16
The vendor-kernel did increase the minimum voltage for some low frequency opps to 825mV citing stability reasons. So do that in mainline as well and also use the ranged notation the vendor-kernel switched to, to give a bit more flexibility for different regulator setups. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Link: https://lore.kernel.org/r/20210225133322.3420724-1-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-03-21arm64: dts: rockchip: Add gpu opp nodes to px30 dtsiMaciej Matuszczyk1-0/+22
This matches the values in the vendor kernel. Signed-off-by: Maciej Matuszczyk <maccraft123mc@gmail.com> [added tiny commit description] Link: https://lore.kernel.org/r/20210225081943.127714-1-maccraft123mc@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-03-19arm64: dts: exynos: white-space cleanupsKrzysztof Kozlowski1-1/+1
Fixup white-space issue: WARNING: please, no spaces at the start of a line Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20210315124313.114842-3-krzysztof.kozlowski@canonical.com
2021-03-19ARM: dts: exynos: white-space cleanupsKrzysztof Kozlowski4-40/+41
Fixups some white-space issues. Checkpatch reported: WARNING: Block comments should align the * on each line WARNING: please, no spaces at the start of a line ERROR: code indent should use tabs where possible Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20210315124313.114842-2-krzysztof.kozlowski@canonical.com
2021-03-19ARM: dts: exynos: replace deprecated NTC/Murata compatiblesKrzysztof Kozlowski2-4/+4
The compatibles with "ntc" vendor prefix become deprecated and "murata" should be used. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20210315124313.114842-1-krzysztof.kozlowski@canonical.com
2021-03-18arm64: dts: qcom: qrb5165-rb5: switch into using GPIO for SPI0 CSDmitry Baryshkov1-2/+3
On the GENI SPI controller is is not very efficient if the chip select line is controlled by the QUP itself (see 37dd4b777942 ("arm64: dts: qcom: sc7180: Provide pinconf for SPI to use GPIO for CS") for the details). Configure SPI0 CS pin as a GPIO. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210210133458.1201066-5-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-18arm64: dts: qcom: sm8250: add pinctrl for SPI using GPIO as a CSDmitry Baryshkov1-0/+100
GENI SPI controller shows several issues if it manages the CS on its own (see 37dd4b777942 ("arm64: dts: qcom: sc7180: Provide pinconf for SPI to use GPIO for CS")) for the details. Provide pinctrl entries for SPI controllers using the same CS pin but in GPIO mode. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210210133458.1201066-4-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-18arm64: dts: qcom: sm8250: further split of spi pinctrl configDmitry Baryshkov2-81/+148
Split "default" device tree nodes into common "data-clk" nodes and "cs" nodes which might differ from board to board depending on how the slave chips are wired. Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210210133458.1201066-3-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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