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2013-08-16ARM: imx6: change some clocks to fixup clocksLiu Ying4-22/+50
All the clocks controlled by the register 'CCM Serial Clock Multiplexer Register 1' should be fixup clocks. This patch changes those clocks from basic multiplexer or divider clocks to fixup clocks. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-16ARM: imx: add common clock support for fixup muxLiu Ying3-1/+112
One register may have several fields to control some clocks. It is possible that the read/write values of some fields may map to different real functional values, so writing to the other fields in the same register may break a working clock tree. A real case is the aclk_podf field in the register 'CCM Serial Clock Multiplexer Register 1' of i.MX6Q/SDL SoC. This patch introduces a fixup hook for multiplexer clock which is called before writing a value to clock registers to support this kind of multiplexer clocks. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-16ARM: imx: add common clock support for fixup divLiu Ying3-1/+135
One register may have several fields to control some clocks. It is possible that the read/write values of some fields may map to different real functional values, so writing to the other fields in the same register may break a working clock tree. A real case is the aclk_podf field in the register 'CCM Serial Clock Multiplexer Register 1' of i.MX6Q/SDL SoC. This patch introduces a fixup hook for divider clock which is called before writing a value to clock registers to support this kind of divider clocks. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-16ARM: imx: Select MIGHT_HAVE_CACHE_L2X0Fabio Estevam1-0/+1
Select MIGHT_HAVE_CACHE_L2X0 for armv6 and armv7 i.MX SoCs. By selecting MIGHT_HAVE_CACHE_L2X0, the user still has the possibility to disable CACHE_L2X0 selection via menuconfig. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-16ARM: imx: fix imx_init_l2cache storage classVincent Stehlé1-1/+1
This fixes the following compilation error: arch/arm/mach-imx/system.c:101:123: error: static declaration of ‘imx_init_l2cache’ follows non-static declaration In file included from arch/arm/mach-imx/system.c:32:0: arch/arm/mach-imx/common.h:165:13: note: previous declaration of ‘imx_init_l2cache’ was here arch/arm/mach-imx/system.c:101:123: warning: ‘imx_init_l2cache’ defined but not used [-Wunused-function] Signed-off-by: Vincent Stehlé <vincent.stehle@freescale.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-16ARM: imx_v6_v7_defconfig: enable WEIM driverHuang Shijie1-0/+2
enable the weim driver. Since the NOR is connected to the WEIM for imx6q{dl}-sabreauto, we also enable the MTD_PHYSMAP_OF module. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-16ARM: imx: use imx specific L2 init function on imx6slShawn Guo1-2/+1
The optimized L2 prefect and power setting done in imx_init_l2cache() can also benefit imx6sl, so let's call the function on imx6sl as well. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
2013-08-16ARM: imx: let L2 initialization be a common functionShawn Guo3-36/+40
Move imx6q L2 initialization function imx6q_init_l2cache() into system.c, and rename it imx_init_l2cache(), so that other platforms other than imx6q can also use the function. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
2013-08-16ARM: imx_v4_v5_defconfig: Select CONFIG_MACH_IMX25_DTFabio Estevam1-0/+1
Allow booting a mx25 dt kernel by default. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-16ARM: imx_v6_v7_defconfig: Enable VPU driverFabio Estevam1-0/+3
Let VPU driver be selected by default. VPU driver requires a SRAM pool, so select CONFIG_SRAM as well. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-16ARM i.MX6DL: parent LDB DI clocks to PLL5 on i.MX6S/DLPhilipp Zabel1-1/+1
i.MX6S/DL have the Video PLL post dividers fixed already in revision 1.0 Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-16ARM: imx_v6_v7_defconfig: Enable LVDS Display BridgeFabio Estevam1-0/+1
Let IMX_LDB driver be built by default. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-16ARM: imx_v6_v7_defconfig: Enable FSL_LPUART supportFabio Estevam1-0/+2
Enable the FSL_LPUART driver as it is used by the VF610 family. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-16ARM i.MX6Q: Use ENET_CLK_SEL defines in imx6q_1588_initPhilipp Zabel1-1/+4
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-16ARM: imx_v6_v7_defconfig: Select CONFIG_NOP_USB_XCEIV by defaultFabio Estevam1-0/+1
In order to get USB functionality on mx5 boards, we need to select CONFIG_NOP_USB_XCEIV option, so let's enable it by default. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-16ARM: i.MX6: add ethernet phy fixup for KSZ9031Sascha Hauer1-0/+23
The KSZ9031 is used on the i.MX6 based Data Modul eDM-QMX6 board. It needs the same fixup to the rx/tx delays as other i.MX6 boards. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-16ARM: i.MX6: add ethernet phy fixup for AR8031Sascha Hauer1-0/+27
The AR8031 is used on the i.MX6 based sabreSD, sabreauto and wandboard. All need the same fixup, so add it for all i.MX6. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-16ARM: i.MX6: call ksz9021 phy fixup for all i.MX6 boardsSascha Hauer1-4/+6
In current U-Boot the sabrelite, nitrogen6x and titanium all need the same fixup for the ksz9021 phy. Instead of limiting the fixup to a single board apply them for all. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-16drivers: bus: imx-weim: Add support for i.MX1/21/25/27/31/35/50/51/53Alexander Shiyan3-23/+66
This patch adds WEIM support for all i.MX CPUs supported by the kernel. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-16drivers: bus: imx-weim: Add missing platform_driver.owner fieldAlexander Shiyan1-2/+3
Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-16drivers: bus: imx-weim: use module_platform_driver_probe()Alexander Shiyan1-5/+5
Driver should be called only once at startup, so code converted to using module_platform_driver_probe(). Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-16drivers: bus: imx-weim: Simplify error pathAlexander Shiyan1-14/+8
Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-16drivers: bus: imx-weim: Remove private driver dataAlexander Shiyan1-27/+14
Driver uses only probe function so no reason to keep variables in private driver data. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-15ARM: vexpress/MCPM: fix cache disable sequence when CONFIG_FRAME_POINTER=yNicolas Pitre2-8/+24
If CONFIG_FRAME_POINTER=y we get the following error: arch/arm/mach-vexpress/tc2_pm.c: In function 'tc2_pm_down': arch/arm/mach-vexpress/tc2_pm.c:200:1: error: fp cannot be used in asm here Let's fix that by explicitly preserving r11 on the stack and removing it from the clobber list. Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Reviewed-by: Dave Martin <Dave.Martin@arm.com> Signed-off-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-08-14Merge tag 'renesas-soc2-for-v3.12' of ↵Olof Johansson7-9/+55
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc From Simon Horman: Second Round of Renesas ARM based SoC updates for v3.12 * Increased clock coverage for r8a7740 and r8a7790 SoCs * tag 'renesas-soc2-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a7740: Add TPU clock entry for DT platforms ARM: shmobile: r8a7790: clocks for Ether support ARM: shmobile: r8a7740: Fix TPU clock name ARM: shmobile: Insert align directives before 4 bytes data ARM: shmobile: Force ARM mode to compile reset vector for secondary CPUs ARM: shmobile: fix compile error when CONFIG_THUMB2_KERNEL=y ARM: shmobile: Update romImage to relocate appended DTB Signed-off-by: Olof Johansson <olof@lixom.net>
2013-08-14Merge tag 'renesas-soc-for-v3.12' of ↵Olof Johansson34-501/+851
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc From Simon Horman: Renesas ARM based SoC updates for v3.12 * Setup arch timer based on MD pins on r8a7790 SoC * Thermal driver support for r8a7790 SoC * Make arch timer optional for r8a7790 and r8a73a4 SoCs * CMT10 clock event for r8a7790 and r8a73a4 SoCs * Increased clock coverage for r8a73a4 SoC * MMCIF DMA definitions for r8a7740 SoC * Disconnect SMP code from clocks on emev2 SoC * tag 'renesas-soc-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (49 commits) ARM: shmobile: Setup r8a7790 arch timer based on MD pins ARM: shmobile: Introduce r8a7790_read_mode_pins() ARM: shmobile: r8a7740: add MMCIF DMA definitions ARM: shmobile: Disconnect EMEV2 SMP code from clocks ARM: shmobile: Make r8a73a4 Arch timer optional ARM: shmobile: Add r8a73a4 CMT10 clock event ARM: shmobile: Make r8a7790 Arch timer optional ARM: shmobile: Add r8a7790 CMT00 clock event ARM: shmobile: Sort r8a7790 MSTP entries ARM: shmobile: r8a73a4: add clocks for I2C controllers ARM: shmobile: r8a73a4: add Z2 clock support ARM: shmobile: r8a73a4: safeguard against wrong clk_set_rate() uses ARM: shmobile: r8a73a4: implement CPU clock scaling for CPUFreq ARM: shmobile: r8a73a4: wait for completion when kicking the clock ARM: shmobile: r8a7790: add thermal driver support ARM: shmobile: r8a7790: add clocks for thermal ARM: shmobile: Add SMSC ethernet chip to KZM9D DT reference ARM: shmobile: KZM9D DT reference implementation ARM: shmobile: r8a7790: add MMCIF and SDHI DT templates ARM: shmobile: r8a73a4: add MMCIF and SDHI DT templates ... Signed-off-by: Olof Johansson <olof@lixom.net>
2013-08-14ARM: prima2: pm: drop redundant postcore_initcallBarry Song1-8/+8
This will delete some redundant calling of sirfsoc_of_pwrc_init() and sirfsoc_memc_init() for non-CSR platforms if we use multi-platform. Cc: Srinivas Kandagatla <srinivas.kandagatla@st.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-08-14ARM: prima2: pm: enable rtc alarm0 and alarm1 as wakeup sourceXianglong Du1-1/+4
This patch also enables RTC alarm as wakeup source after system suspends. Signed-off-by: Xianglong Du <Xianglong.Du@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-08-14Merge tag 'dra7-core-support-minus-dt' of git://github.com/rrnayak/linux ↵Tony Lindgren15-10/+86
into omap-for-v3.12/soc DRA7xx based SoC core support
2013-08-14Merge tag 'tc2-pm' of git://git.linaro.org/people/pawelmoll/linux into next/socOlof Johansson8-21/+633
From Pawel Moll and Nicolas Pitre: - Fixes to the existing Vexpress DCSCB backend. - Lorenzo's minimal SPC driver required by the TC2 MCPM backend. - The MCPM backend enabling SMP secondary boot and CPU hotplug on the VExpress TC2 big.LITTLE platform. - MCPM suspend method to the TC2 backend allowing basic CPU idle/suspend. The cpuidle driver that hooks into this will be submitted separately. * tag 'tc2-pm' of git://git.linaro.org/people/pawelmoll/linux: ARM: vexpress/TC2: implement PM suspend method ARM: vexpress/TC2: basic PM support ARM: vexpress: Add SCC to V2P-CA15_A7's device tree ARM: vexpress/TC2: add Serial Power Controller (SPC) support ARM: vexpress/dcscb: fix cache disabling sequences Signed-off-by: Olof Johansson <olof@lixom.net>
2013-08-13ARM: tegra: disable LP2 cpuidle state if PCIe is enabledStephen Warren5-0/+47
Tegra20 HW appears to have a bug such that PCIe device interrupts, whether they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around this, simply disable LP2 if any PCIe devices with interrupts are present. Detect this via the IRQ domain map operation. This is slightly over-conservative; if a device with an interrupt is present but the driver does not actually use them, LP2 will still be disabled. However, this is a reasonable trade-off which enables a simpler workaround. Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com>
2013-08-13MAINTAINERS: Add myself as Tegra PCIe maintainerThierry Reding1-0/+7
I'll be taking on maintainership of the Tegra PCIe driver since it's now moved out of arch/arm/mach-tegra. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-13PCI: tegra: set up PADS_REFCLK_CFG1Stephen Warren1-5/+24
The registers PADS_REFCLK_CFG are an array of 16-bit data, one entry per PCIe root port. For Tegra30, we therefore need to write a 3rd entry in this array. Doing so makes the mini-PCIe slot on Beaver operate correctly. While we're at it, add some #defines to partially document the fields within these 16-bit values. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-13PCI: tegra: Add Tegra 30 PCIe supportJay Agarwal2-34/+179
Introduce a data structure to parameterize the driver according to SoC generation, add Tegra30 specific code and update the device tree binding document for Tegra30 support. Signed-off-by: Jay Agarwal <jagarwal@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-13PCI: tegra: Move PCIe driver to drivers/pci/hostThierry Reding11-1018/+1703
Move the PCIe driver from arch/arm/mach-tegra into the drivers/pci/host directory. The motivation is to collect various host controller drivers in the same location in order to facilitate refactoring. The Tegra PCIe driver has been largely rewritten, both in order to turn it into a proper platform driver and to add MSI (based on code by Krishna Kishore <kthota@nvidia.com>) as well as device tree support. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> [swarren, split DT changes into a separate patch in another branch] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-13Merge tag 'msi-3.12-2' into for-3.12/socStephen Warren22-81/+185
pci msi changes for v3.12 (round 2) - fix build breakage for s390 allyesconfig due to !HAVE_GENERIC_HARDIRQS
2013-08-13PCI: msi: add default MSI operations for !HAVE_GENERIC_HARDIRQS platformsThomas Petazzoni1-0/+16
Some platforms (e.g S390) don't use the generic hardirqs code and therefore do not defined HAVE_GENERIC_HARDIRQS. This prevents using the irq_set_chip_data() and irq_get_chip_data() functions that are used for the default implementations of the MSI operations. So, when CONFIG_GENERIC_HARDIRQS is not enabled, provide another default implementation of the MSI operations, that simply errors out. The architecture is responsible for implementing those operations (which is the case on S390), and cannot use the msi_chip infrastructure. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2013-08-13ARM: DRA7: Add the build support in omap2plusR Sricharan3-2/+11
Now that all the needed pieces for DRA7 based SoCs' is present, enable the build support in omap2plus_defconfig Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
2013-08-13ARM: DRA7: hwmod: Reuse the soc_ops used for OMAP4/5Rajendra Nayak1-1/+1
The soc_ops for dra7xx devices can be completed reused from the ones used for omap4 and omap5 devices. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com>
2013-08-13ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs'R Sricharan3-2/+20
The DRA7xx is a high-performance, infotainment application device, based on enhanced OMAP architecture integrated on a 28-nm technology. Since DRA7 is a platform supported only using DT, the cpu detection is based on the compatibles passed from DT blobs as suggested here http://lists.infradead.org/pipermail/linux-arm-kernel/2013-July/187712.html Suggested-by: Felipe Balbi <balbi@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
2013-08-13ARM: DRA7: Kconfig: Make ARCH_NR_GPIO default to 512R Sricharan1-1/+1
DRA7xx has 8 GPIO banks so that there are 32x8 = 256 GPIOs. In order for the gpiolib to detect and initialize these and other TWL GPIOs, ARCH_NR_GPIO is set to 512 using the kconfig default for DRA7. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
2013-08-13ARM: DRA7: board-generic: Add basic DT supportR Sricharan2-0/+21
Describe minimal DT boot machine details for DRA7xx based SoC's. DRA7xx family is based on dual core ARM CORTEX A15 using GIC as the interrupt controller. The PRCM and timer infrastructure is reused from OMAP5 and so are the io descriptor tables. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
2013-08-13ARM: DRA7: Resue the clocksource, clockevent supportR Sricharan2-2/+3
All of OMAP5 timer support for clocksource and clockevent is completely reused across DRA7. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
2013-08-13ARM: DRA7: Reuse io tables and add a new .init_earlyR Sricharan3-2/+23
The IO descriptor tables for DRA7 are a complete reuse from OMAP5. A new dra7xx_init_early() does the base address inits. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
2013-08-13ARM: DRA7: Reuse all of PRCM and MPUSS SMP infraR Sricharan1-0/+6
The PRCM and MPUSS parts of DRA7 devices are quite identical to OMAP5 so as to reuse all the existing infrastructure around it. Makefile updates to do just that. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
2013-08-12ARM: tegra: add LP1 suspend support for Tegra114Joseph Lo4-15/+141
The LP1 suspend mode will power off the CPU, clock gated the PLLs and put SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The sequence when LP1 suspending: * tunning off L1 data cache and the MMU * storing some EMC registers, DPD (deep power down) status, clk source of mselect and SCLK burst policy * putting SDRAM into self-refresh * switching CPU to CLK_M (12MHz OSC) * tunning off PLLM, PLLP, PLLA, PLLC and PLLX * switching SCLK to CLK_S (32KHz OSC) * shutting off the CPU rail The sequence of LP1 resuming: * re-enabling PLLM, PLLP, PLLA, PLLC and PLLX * restoring the clk source of mselect and SCLK burst policy * setting up CCLK burst policy to PLLX * restoring DPD status and some EMC registers * resuming SDRAM to normal mode * jumping to the "tegra_resume" from PMC_SCRATCH41 Due to the SDRAM will be put into self-refresh mode, the low level procedures of LP1 suspending and resuming should be copied to TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before restoring the CPU context when resuming, the SDRAM needs to be switched back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy be restored. Then jumping to "tegra_resume" that was expected to be stored in PMC_SCRATCH41 to restore CPU context and back to kernel. Based on the work by: Bo Yan <byan@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12ARM: tegra: add LP1 suspend support for Tegra20Joseph Lo5-0/+341
The LP1 suspend mode will power off the CPU, clock gated the PLLs and put SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The sequence when LP1 suspending: * tunning off L1 data cache and the MMU * putting SDRAM into self-refresh * storing some EMC registers and SCLK burst policy * switching CPU to CLK_M (12MHz OSC) * switching SCLK to CLK_S (32KHz OSC) * tunning off PLLM, PLLP and PLLC * shutting off the CPU rail The sequence of LP1 resuming: * re-enabling PLLM, PLLP, and PLLC * restoring some EMC registers and SCLK burst policy * setting up CCLK burst policy to PLLP * resuming SDRAM to normal mode * jumping to the "tegra_resume" from PMC_SCRATCH41 Due to the SDRAM will be put into self-refresh mode, the low level procedures of LP1 suspending and resuming should be copied to TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before restoring the CPU context when resuming, the SDRAM needs to be switched back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy be restored, CCLK burst policy be set in PLLP. Then jumping to "tegra_resume" that was expected to be stored in PMC_SCRATCH41 to restore CPU context and back to kernel. Based on the work by: Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12ARM: tegra: add LP1 suspend support for Tegra30Joseph Lo7-4/+560
The LP1 suspend mode will power off the CPU, clock gated the PLLs and put SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The sequence when LP1 suspending: * tunning off L1 data cache and the MMU * storing some EMC registers, DPD (deep power down) status, clk source of mselect and SCLK burst policy * putting SDRAM into self-refresh * switching CPU to CLK_M (12MHz OSC) * tunning off PLLM, PLLP, PLLA, PLLC and PLLX * switching SCLK to CLK_S (32KHz OSC) * shutting off the CPU rail The sequence of LP1 resuming: * re-enabling PLLM, PLLP, PLLA, PLLC and PLLX * restoring the clk source of mselect and SCLK burst policy * setting up CCLK burst policy to PLLX * restoring DPD status and some EMC registers * resuming SDRAM to normal mode * jumping to the "tegra_resume" from PMC_SCRATCH41 Due to the SDRAM will be put into self-refresh mode, the low level procedures of LP1 suspending and resuming should be copied to TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before restoring the CPU context when resuming, the SDRAM needs to be switched back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy be restored, CCLK burst policy be set in PLLX. Then jumping to "tegra_resume" that was expected to be stored in PMC_SCRATCH41 to restore CPU context and back to kernel. Based on the work by: Scott Williams <scwilliams@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12ARM: tegra: add common LP1 suspend supportJoseph Lo5-5/+140
The LP1 suspending mode on Tegra means CPU rail off, devices and PLLs are clock gated and SDRAM in self-refresh mode. That means the low level LP1 suspending and resuming code couldn't be run on DRAM and the CPU must switch to the always on clock domain (a.k.a. CLK_M 12MHz oscillator). And the system clock (SCLK) would be switched to CLK_S, a 32KHz oscillator. The LP1 low level handling code need to be moved to IRAM area first. And marking the LP1 mask for indicating the Tegra device is in LP1. The CPU power timer needs to be re-calculated based on 32KHz that was originally based on PCLK. When resuming from LP1, the LP1 reset handler will resume PLLs and then put DRAM to normal mode. Then jumping to the "tegra_resume" that will restore full context before back to kernel. The "tegra_resume" handler was expected to be found in PMC_SCRATCH41 register. This is common LP1 procedures for Tegra, so we do these jobs mainly in this patch: * moving LP1 low level handling code to IRAM * marking LP1 mask * copying the physical address of "tegra_resume" to PMC_SCRATCH41 * re-calculate the CPU power timer based on 32KHz Signed-off-by: Joseph Lo <josephl@nvidia.com> [swarren, replaced IRAM_CODE macro with IO_ADDRESS(TEGRA_IRAM_CODE_AREA)] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12clk: tegra114: add LP1 suspend/resume supportJoseph Lo1-0/+12
When the system suspends to LP1, the CPU clock source is switched to CLK_M (12MHz Oscillator) during suspend/resume flow. The CPU clock source is controlled by the CCLKG_BURST_POLICY register, and hence this register must be restored during LP1 resume. Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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