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2023-12-11dt-bindings: display: mediatek: ethdr: Add compatible for MT8188Hsiao Chien Sung1-1/+5
Add compatible name for MediaTek MT8188 ETHDR. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11dt-bindings: thermal: convert Mediatek Thermal to the json-schemaRafał Miłecki2-52/+99
This helps validating DTS files. Introduced changes: 1. Improved title 2. Simplified description (dropped "This describes the device tree...") 3. Dropped undocumented "reset-names" from example Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11arm64: dts: mt8183: Add jacuzzi pico/pico6 boardHsin-Yi Wang3-0/+147
pico is also known as Acer Chromebook Spin 311. Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> [Angelo: Fixed blank lines at the end for pico.dts] Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11dt-bindings: arm64: mediatek: Add mt8183-kukui-jacuzzi-picoHsin-Yi Wang1-0/+7
Add pico (sku1) and pico6 (sku2). Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11arm64: dts: mt8183: Add jacuzzi makomo boardHsin-Yi Wang3-0/+50
makomo is also known as Lenovo 100e Chromebook 2nd Gen MTK 2. Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11dt-bindings: arm64: mediatek: Add mt8183-kukui-jacuzzi-makomoHsin-Yi Wang1-0/+7
Add makomo sku0 and sku1 which uses different audio codec. Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11arm64: dts: mt8183: Add kukui katsu boardHsin-Yi Wang6-13/+115
katsu is also known as ASUS Chromebook Detachable CZ1. Let katsu and kakadu set its own touchscreen and panel compatible. Remove these setting from the common dtsi for readability. Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11dt-bindings: arm64: mediatek: Add mt8183-kukui-katsuHsin-Yi Wang1-0/+7
Add katsu sku32 and sku38 which uses different audio codec. Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11arm64: dts: mediatek: Move MT6358 PMIC interrupts to MT8183 boardsAngeloGioacchino Del Regno4-1/+12
MT6358 is a PMIC that is typically used on MT8183 boards, and it has its own dtsi file, declaring interrupts-extended on its node. The interrupt pin of that PMIC is connected to a SoC GPIO and that is therefore not only SoC-specific, but board-specific: this means that the interrupt-extended property does not belong to the PMIC dtsi file, but to board files using that PMIC. For correctness, transfer the interrupts-extended property from the PMIC-specific mt6358.dtsi to board files. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11arm64: dts: mediatek: Use interrupts-extended where possibleAngeloGioacchino Del Regno4-10/+5
As already done for MT8173 and MT8183 devicetrees, change all instances of interrupt-parent + interrupts to one line as interrupts-extended where possible across all remaining device trees to both simplify and reduce code size. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11arm64: dts: mediatek: mt8173: Use interrupts-extended where possibleAngeloGioacchino Del Regno3-24/+12
Change all instances of interrupt-parent + interrupts to one line as interrupts-extended where possible across all MT8173 DTs to both simplify and reduce code size. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11arm64: dts: mediatek: mt8183: Use interrupts-extended where possibleAngeloGioacchino Del Regno10-22/+11
Change all instances of interrupt-parent + interrupts to one line as interrupts-extended where possible across all MT8183 DTs to both simplify and reduce code size. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11dt-bindings: soc: mediatek: add mt8186 and mt8195 svs dt-bindingsMark Tseng1-0/+2
Support more SoC svs compatible in dt-bindings. 1. MT8186 2. MT8195 Signed-off-by: Mark Tseng <chun-jen.tseng@mediatek.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11dt-bindings: arm: mediatek: mmsys: Add VPPSYS compatible for MT8188yu-chang.lee2-2/+2
For MT8188, VPPSYS0 and VPPSYS1 are 2 display pipes with hardware differences in power domains, clocks and subsystem counts, which should be probed from mtk-mmsys driver to populate device by platform_device_register_data then start its own clock driver. Signed-off-by: yu-chang.lee <yu-chang.lee@mediatek.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zonesBalsam CHIHI1-0/+454
Add thermal nodes and thermal zones for the mt8192. The mt8192 SoC has several hotspots around the CPUs. Specify the targeted temperature threshold to apply the mitigation and define the associated cooling devices. Signed-off-by: Balsam CHIHI <bchihi@baylibre.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> [bero@baylibre.com: cosmetic changes, reduce lvts_ap size] Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2023-12-11arm64: dts: mediatek: mt8183: Add decoderYunfei Dong1-0/+30
Add node for the hardware decoder present on the MT8183 SoC. Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com> Signed-off-by: Qianqian Yan <qianqian.yan@mediatek.com> Signed-off-by: Frederic Chen <frederic.chen@mediatek.com> Signed-off-by: Alexandre Courbot <acourbot@chromium.org> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230630151436.155586-8-nfraprado@collabora.com
2023-12-11arm64: dts: mediatek: mt8173: Drop VDEC_SYS reg from decoderNícolas F. R. A. Prado1-3/+5
Remove the VDEC_SYS register space from the decoder, so that the node address becomes that of VDEC_MISC, solving the long-standing conflicting addresses between this node and the vdecsys clock-controller node: arch/arm64/boot/dts/mediatek/mt8173.dtsi:1365.38-1369.5: Warning (unique_unit_address_if_enabled): /soc/clock-controller@16000000: duplicate unit-address (also used in node /soc/vcodec@16000000) The driver makes use of this register space, however, so also add a phandle to the VDEC_SYS syscon to maintain functionality. Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230630151436.155586-7-nfraprado@collabora.com
2023-12-11arm64: dts: mediatek: cherry: Add platform thermal configurationAngeloGioacchino Del Regno1-0/+105
This platform has three auxiliary NTC thermistors, connected to the SoC's ADC pins. Enable the auxadc in order to be able to read the ADC values, add a generic-adc-thermal LUT for each and finally assign them to the SoC's thermal zones. Tested-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230424112523.1436926-2-angelogioacchino.delregno@collabora.com
2023-12-11Merge branch 'for-v6.8/samsung-bindings-compatibles' into next/dt64Krzysztof Kozlowski4-5/+505
2023-12-11arm64: dts: exynos: add minimal support for exynosautov920 sadk boardJaewon Kim2-1/+90
ExynosAutov920 SADK is ExynosAutov920 SoC based SADK(Samsung Automotive Development Kit) board. It has 16GB(8GB + 8GB) LPDDR5 RAM and 256GB (128GB + 128GB) UFS. This is minimal support board device-tree. * Serial console * GPIO Key * PWM FAN Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Link: https://lore.kernel.org/r/20231208074527.50840-3-jaewon02.kim@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-12-11arm64: dts: exynos: add initial support for exynosautov920 SoCJaewon Kim2-0/+1578
Samsung ExynosAutov920 is ARMv8-based automotive-oriented SoC. It has AE(Automotive Enhanced) IPs for safety. * Cortex-A78AE 10-cores * GIC-600AE This is minimal support for ExynosAutov920 SoC. * Enumerate all pinctrl nodes * Enable Chip-Id * Serial0 for console * PWM Since the clock driver is not yet implemented, it is supported as fixed-clock. Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Link: https://lore.kernel.org/r/20231208074527.50840-2-jaewon02.kim@samsung.com [krzysztof: Re-order nodes to match coding style: UFS reset pins, gpg/gpp in peric0 and peric1, all nodes in the soc@0; drop fallback compatibles from wakeup-interrupt-controller] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-12-11dt-bindings: samsung: exynos-sysreg: combine exynosautov920 with other enumKrzysztof Kozlowski1-5/+2
No need to create a new enum every time we bring-up new SoC. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Jaewon Kim <jaewon02.kim@samsung.com> Link: https://lore.kernel.org/r/20231210134834.43943-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-12-10dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to ↵Peter Griffin1-0/+3
GS101 GS101 has three different SYSREG controllers, add dedicated compatibles for them to the documentation. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20231209233106.147416-4-peter.griffin@linaro.org [krzysztof: move Google entries to existing enum] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-12-10dt-bindings: clock: Add Google gs101 clock management unit bindingsPeter Griffin2-0/+498
Provide dt-schema documentation for Google gs101 SoC clock controller. Currently this adds support for cmu_top, cmu_misc and cmu_apm. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231209233106.147416-3-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-12-10dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatiblePeter Griffin1-0/+2
Add gs101-pmu compatible to the bindings documentation. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20231209233106.147416-2-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-12-09arm64: dts: qcom: qcm6490-fairphone-fp5: Enable WiFiLuca Weiss1-0/+5
Now that the WPSS remoteproc is enabled, enable wifi so we can use it. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20231208-sc7280-remoteprocs-v3-11-6aa394d33edf@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-09arm64: dts: qcom: qcm6490-fairphone-fp5: Enable various remoteprocsLuca Weiss1-0/+20
Enable the ADSP, CDSP, MPSS and WPSS that are found on the SoC. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20231208-sc7280-remoteprocs-v3-10-6aa394d33edf@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-09arm64: dts: qcom: sc7280: Add CDSP nodeLuca Weiss4-0/+151
Add the node for the ADSP found on the SC7280 SoC, using standard Qualcomm firmware. Remove the reserved-memory node from sc7280-chrome-common since CDSP is currently not used there. Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20231208-sc7280-remoteprocs-v3-9-6aa394d33edf@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-09arm64: dts: qcom: sc7280: Add ADSP nodeLuca Weiss5-10/+76
Add the node for the ADSP found on the SC7280 SoC, using standard Qualcomm firmware. Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20231208-sc7280-remoteprocs-v3-8-6aa394d33edf@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-09arm64: dts: qcom: sc7280: Use WPSS PAS instead of PILLuca Weiss2-13/+21
The wpss-pil driver wants to manage too many resources that cannot be touched with standard Qualcomm firmware. Use the compatible from the PAS driver and move the ChromeOS-specific bits to sc7280-chrome-common.dtsi. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20231208-sc7280-remoteprocs-v3-7-6aa394d33edf@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-09arm64: dts: qcom: qcm6490-fairphone-fp5: Enable UFSLuca Weiss1-2/+25
Enable the UFS phy and controller so that we can access the internal storage of the phone. At the same time we need to bump the minimum voltage used for UFS VCC, otherwise it doesn't initialize properly. The 2.952V is taken from the vcc-voltage-level property downstream. See also the following link for more information about the VCCQ/VCCQ2: https://gerrit-public.fairphone.software/plugins/gitiles/kernel/msm-extra/devicetree/+/1590a3739e7dc29d2597307881553236d492f188/fp5/yupik-idp-pm7250b.dtsi#207 Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231002-fp5-ufs-v2-1-e2d7de522134@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-09arm64: dts: qcom: msm8953: Set initial address for memoryLuca Weiss1-2/+2
The dtbs_check really doesn't like having memory without reg set. The base address depends on the amount of RAM you have: <= 2.00 GiB RAM: 0x80000000 = 3.00 GiB RAM: 0x40000000 = 3.75 GiB RAM: 0x10000000 (more does not fit into the 32-bit physical address space) So, let's pick one of the values, 0x10000000 which is used on devices with 3.75 GiB RAM. Since the bootloader will update it to what's present on the device it doesn't matter too much. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Link: https://lore.kernel.org/r/20231125-msm8953-misc-fixes-v2-1-df86655841d9@z3ntu.xyz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-09ARM: dts: qcom: msm8226: Add GPULuca Weiss1-0/+40
The msm8226 SoC contains an Adreno 305B. Add a node to configure it. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Link: https://lore.kernel.org/r/20231130-msm8226-gpu-v1-3-6bb2f1b29e49@z3ntu.xyz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-09ARM: dts: qcom: Disable pm8941 & pm8226 smbb charger by defaultBryant Mairs11-0/+26
Some platforms don't use the built-in charging hardware (e.g. milletwifi). As this is an optional peripheral, default it to off. Keep it enabled for all other boards that use smbb. Signed-off-by: Bryant Mairs <bryant@mai.rs> Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231203-smbb-pm8941-pm8226-v1-1-9ad75909604b@z3ntu.xyz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-09arm64: dts: qcom: sc7280: Add UFS nodes for sc7280 IDP boardNitin Rawat1-0/+19
Add UFS host controller and PHY nodes for sc7280 IDP board. Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20231205-sc7280-ufs-v6-3-ad6ca7796de7@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-09arm64: dts: qcom: sc7280: Add UFS nodes for sc7280 socNitin Rawat1-1/+72
Add UFS host controller and PHY nodes for sc7280 soc. Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> [luca: various cleanups and additions as written in the cover letter] Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20231205-sc7280-ufs-v6-2-ad6ca7796de7@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-08ARM: dts: samsung: exynos4210-i9100: Add accelerometer nodePaul Cercueil1-0/+17
Add a Device Tree node for the ST Microelectronics "K3D" accelerometer chip found in the Galaxy S2. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20231206221556.15348-4-paul@crapouillou.net [krzysztof: fix alphabetical placement of i2c_1] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-12-08ARM: dts: samsung: exynos4210-i9100: Add node for touch keysPaul Cercueil1-1/+22
Add a Device Tree node to support the LED-backed "menu" and "back" keys. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20231206221556.15348-3-paul@crapouillou.net Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-12-08ARM: dts: samsung: exynos4210-i9100: Unconditionally enable LDO12Paul Cercueil1-0/+8
The kernel hangs for a good 12 seconds without any info being printed to dmesg, very early in the boot process, if this regulator is not enabled. Force-enable it to work around this issue, until we know more about the underlying problem. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Fixes: 8620cc2f99b7 ("ARM: dts: exynos: Add devicetree file for the Galaxy S2") Cc: stable@vger.kernel.org # v5.8+ Link: https://lore.kernel.org/r/20231206221556.15348-2-paul@crapouillou.net Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-12-08ARM: dts: microchip: sama5d27_wlsom1_ek: Remove mmc-ddr-3_3v property from ↵Mihai Sain1-1/+0
sdmmc0 node On board the sdmmc0 interface is wired to a SD Card socket. According with mmc-controller bindings, the mmc-ddr-3_3v property is used for eMMC devices to enable high-speed DDR mode (3.3V I/O). Remove the mmc-ddr-3_3v property from sdmmc0 node. Signed-off-by: Mihai Sain <mihai.sain@microchip.com> Link: https://lore.kernel.org/r/20231204072537.2991-1-mihai.sain@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2023-12-08arm64: dts: qcom: sm8650: Add DisplayPort device nodesNeil Armstrong1-2/+118
Declare the displayport controller present on the Qualcomm SM8650 SoC and connected to the USB3/DP Combo PHY. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231208-topic-sm8650-upstream-dp-v2-1-69dab3d074e4@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-08arm64: dts: qcom: pm8550: drop PWM address/size cellsKrzysztof Kozlowski1-3/+0
The address/size cells in PWM node are needed only if individual LEDs are listed. If multi-led is used, then this leads to dtc W=1 warnings: pm8550.dtsi:65.19-73.5: Warning (avoid_unnecessary_addr_size): /soc@0/spmi@c400000/pmic@1/pwm: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231208124332.48636-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-08arm64: dts: hisilicon: hikey970-pmic: clean up SPMI nodeJohan Hovold1-2/+1
Clean up the SPMI node by dropping the redundant status property and moving the 'reg' property after 'compatible' for consistency. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2023-12-08arm64: dts: hisilicon: hikey970-pmic: fix regulator cells propertiesJohan Hovold1-3/+0
The Hi6421 PMIC regulator child nodes do not have unit addresses so drop the incorrect '#address-cells' and '#size-cells' properties. Fixes: 6219b20e1ecd ("arm64: dts: hisilicon: Add support for Hikey 970 PMIC") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2023-12-08dt-bindings: hisilicon: Merge hi3620-clock into hisilicon,sysctrl bindingRob Herring2-20/+17
The hi3620-clock binding is simple and always a child of the "hisilicon,sysctrl" node, so just add it into the hisilicon,sysctrl binding and drop the old txt binding. Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2023-12-08arm64: dts: qcom: x1e80100: Add Compute Reference DeviceAbel Vesa2-0/+427
Add basic support for X1E80100 CRD board dts, which allows it to boot to a shell. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231205062403.14848-5-quic_sibis@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-08arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dtsRajendra Nayak3-0/+3929
Add base dtsi and QCP board (Qualcomm Compute Platform) dts file for X1E80100 SoC, describing the CPUs, GCC and RPMHCC clock controllers, geni UART, interrupt controller, TLMM, reserved memory, interconnects, SMMU and LLCC nodes. Co-developed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20231205062403.14848-4-quic_sibis@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-08dt-bindings: arm: qcom: Document X1E80100 SoC and boardsRajendra Nayak1-0/+8
Document the X1E80100 SoC binding and also the boards using it. Also document the new board id qcp (Qualcomm Compute Platform). Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231205062403.14848-3-quic_sibis@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-08dt-bindings: arm: cpus: Add qcom,oryon compatibleRajendra Nayak1-0/+1
Oryon is the custom ARM CPU core implementation used in Qualcomm's X1E80100 SoC, document it. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Link: https://lore.kernel.org/r/20231205062403.14848-2-quic_sibis@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-08Merge branch 'icc-x1e80100' of ↵Bjorn Andersson2-0/+290
https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into arm64-for-6.8 Merge the X1E80100 interconnect binding to get access to the interconnect port constants.
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-01 02:11:09 +0300