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2023-12-14arm64: dts: imx8mn-var-som-symphony: Describe the USB-C connectorFabio Estevam1-3/+8
Describe the PTN5150 USB-C connector to improve the devicetree description and fix the following dt-schema warning: imx8mn-var-som-symphony.dtb: typec@3d: 'port' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/extcon/extcon-ptn5150.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-14arm64: dts: imx8mp-tqma8mpql-mba8mpxl: Fix USB connector descriptionFabio Estevam1-7/+19
The USB connector should not be placed under the dwc3 node. Move the USB connector out of the SoC level and use port to describe the connection to the dwc3 controller. This fixes the following dt-schema warning: imx8mp-tqma8mpql-mba8mpxl.dtb: usb@38100000: Unevaluated properties are not allowed ('connector' was unexpected) from schema $id: http://devicetree.org/schemas/usb/snps,dwc3.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-14arm64: dts: imx8mp-venice: Fix USB connector descriptionFabio Estevam4-28/+76
The USB connector should not be placed under the dwc3 node. Move the USB connector out of the SoC level and use port to describe the connection to the dwc3 controller. This fixes the following dt-schema warning: imx8mp-venice-gw72xx-2x.dtb: usb@38100000: Unevaluated properties are not allowed ('connector' was unexpected) from schema $id: http://devicetree.org/schemas/usb/snps,dwc3.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-14arm64: dts: imx8mp-verdin: Fix USB connector descriptionFabio Estevam1-9/+21
The USB connector should not be placed under the dwc3 node. Move the USB connector out of the SoC level and use port to describe the connection to the dwc3 controller. This fixes the following dt-schema warning: imx8mp-verdin-wifi-mallow.dtb: usb@32f10100: usb@38100000: Unevaluated properties are not allowed ('connector' was unexpected) from schema $id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-14arm64: dts: imx8dxl-ss-conn: Move clk_dummy out of USB nodeFabio Estevam1-7/+7
The clk_dummy is not part of the usbotg2 block, so move it to the root node to fix the following dt-schema warning: imx8dxl-evk.dtb: usb@5b0e0000: Unevaluated properties are not allowed ('clock-dummy' was unexpected) from schema $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-14arm64: dts: imx8mn-evk: Move port under USB connectorFabio Estevam1-6/+6
Per nxp,ptn5110.yaml, 'port' should be placed under 'connector'. Do as requested to fix the following dt-schema warning: imx8mn-evk.dtb: tcpc@50: 'port' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/usb/nxp,ptn5110.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-14arm64: dts: imx8mm-evk: Move port under USB connectorFabio Estevam1-6/+6
Per nxp,ptn5110.yaml, 'port' should be placed under 'connector'. Do as requested to fix the following dt-schema warning: imx8mm-evkb.dtb: tcpc@50: 'port' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/usb/nxp,ptn5110.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-14arm64: dts: freescale: introduce dimonoff-gateway-evk boardHugo Villeneuve2-0/+161
The Dimonoff gateway EVK board is based on a Variscite VAR-SOM-NANO, with a NXP MX8MN nano CPU and also based on a Symphony mx8mn EVK. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-14dt-bindings: arm: fsl: add Dimonoff gateway EVK boardHugo Villeneuve1-0/+1
Add DT compatible string for Dimonoff gateway EVK board based on a Variscite VAR-SOM-NANO with a NXP MX8MN nano CPU. Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-14dt-bindings: vendor-prefixes: add dimonoffHugo Villeneuve1-0/+2
Add vendor prefix for Dimonoff, which provides IoT smart solutions and custom engineering services. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-14arm64: dts: imx8m*-tqma8m*: Add chassis-typeAlexander Stein4-0/+4
Device tree specification 0.4 defines an optional, but recommended 'chassis-type' property. Add it to TQMa8M* based board files. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-14arm64: dts: imx8mn-beacon: Support overdrive modeAdam Ford1-0/+2
The SoC is configured to operate in overdrive mode, so it is safe to include imx8mn-overdrive to run the GPU faster. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-14arm64: dts: imx8mn: Enable Overdrive modeAdam Ford1-0/+18
The i.MX8M Nano supports and overdrive mode if the SoC is given the proper voltage. Add imx8mn-overdrive.dtsi file which can be included by boards who support the voltage necessary to handle the faster clocks. This increases the GPU clocks from 400MHz to 600MHz. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-14arm64: dts: imx8mm-beacon: Enable overdrive modeAdam Ford1-0/+2
The SoC runs at a high enough voltage to support overdrive mode, so include the imx8mm-overdrive.dtsi file to increase the VPU and GPU clocks to their overdrive speeds. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-14arm64: dts: imx8mm: Add optional overdrive DTSIAdam Ford1-0/+29
For boards who run their SoC at a higher voltage than nominal, the boards can run several clocks at an overdrive rate for better performance. Add an optional DTSI file which can be included by various boards to run in overdrive mode. This raises the GPU PLL to 1000MHz, and the VPU PLL to 700MHz while moving VPU_G1 and VPU_H1 to the SYS_PLL3_OUT which runs at 750MHz. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-14arm64: dts: imx8mm: Reduce GPU to nominal speedAdam Ford1-2/+2
When the GPU nodes were added, the GPU_PLL_OUT was configured for 1000MHz, but this requires the SoC to run in overdrive mode which requires an elevated voltage operating point. Since this may run some boards out of spec, the default clock should be set to 800MHz for nominal operating mode. Boards that run at the higher voltage can update their clocks accordingly. Fixes: 4523be8e46be ("arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core") Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-14arm64: dts: imx93: Fix the micfil clock-names entriesFabio Estevam1-4/+2
fsl,micfil.yaml defines the clock-names in the following sequence: clock-names: items: - const: ipg_clk - const: ipg_clk_app - const: pll8k - const: pll11k - const: clkext3 minItems: 2 imx93.dtsi currently misses the 'pll11k' entry and jump to 'clkext3'. This leads to the following dt-schema warning: imx93-11x11-evk.dtb: micfil@44520000: clock-names:3: 'pll11k' was expected from schema $id: http://devicetree.org/schemas/sound/fsl,micfil.yaml# Fix the warning by describing the clocks up to 'pll8k' as 'clkext3' is assigned to a dummy clock. Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-14ARM: dts: imx23/28: Fix the DMA controller node nameFabio Estevam2-2/+2
Per fsl,mxs-dma.yaml, the node name should be 'dma-controller'. Change it to fix the following dt-schema warning. imx28-apf28.dtb: dma-apbx@80024000: $nodename:0: 'dma-apbx@80024000' does not match '^dma-controller(@.*)?$' from schema $id: http://devicetree.org/schemas/dma/fsl,mxs-dma.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-14ARM: dts: imx23-sansa: Use preferred i2c-gpios propertiesFabio Estevam1-8/+4
The 'gpios' property to describe the SDA and SCL GPIOs is considered deprecated according to i2c-gpio.yaml. Switch to the preferred 'sda-gpios' and 'scl-gpios' properties. This fixes the following schema warnings: imx23-sansa.dtb: i2c-0: 'sda-gpios' is a required property from schema $id: http://devicetree.org/schemas/i2c/i2c-gpio.yaml# imx23-sansa.dtb: i2c-0: 'scl-gpios' is a required property from schema $id: http://devicetree.org/schemas/i2c/i2c-gpio.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-14ARM: dts: imx27-apf27dev: Fix LED nameFabio Estevam1-1/+1
Per leds-gpio.yaml, the led names should start with 'led'. Change it to fix the following dt-schema warning: imx27-apf27dev.dtb: leds: 'user' does not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/leds/leds-gpio.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-14ARM: dts: imx25/27: Pass timing0Fabio Estevam8-8/+8
Per display-timings.yaml, the 'timing' pattern should be used to describe the display timings. Change it accordingly to fix the following dt-schema warning: imx27-apf27dev.dtb: display-timings: '800x480' does not match any of the regexes: '^timing', 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/display/panel/display-timings.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-14ARM: dts: imx25: Fix the iim compatible stringFabio Estevam1-1/+1
Per imx-iim.yaml, the compatible string should only contain a single entry. Use it as "fsl,imx25-iim" to fix the following dt-schema warning: imx25-karo-tx25.dtb: efuse@53ff0000: compatible: ['fsl,imx25-iim', 'fsl,imx27-iim'] is too long from schema $id: http://devicetree.org/schemas/nvmem/imx-iim.yaml# Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2023-12-13MAINTAINERS: add entry for Google Tensor SoCPeter Griffin1-0/+10
Add maintainers entry for the Google tensor SoC based platforms. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20231211162331.435900-17-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-12-13arm64: dts: exynos: google: Add initial Oriole/pixel 6 board supportPeter Griffin3-0/+111
Add initial board support for the Pixel 6 phone code named Oriole. This has been tested with a minimal busybox initramfs and boots to a shell. Tested-by: Will McVicker <willmcvicker@google.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20231211162331.435900-16-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-12-13arm64: dts: exynos: google: Add initial Google gs101 SoC supportPeter Griffin3-0/+1755
Google gs101 SoC is a ARMv8 mobile SoC found in the Pixel 6 (oriole), Pixel 6a (bluejay) and Pixel 6 pro (raven) mobile phones. It features: * 4xA55 Little cluster * 2xA76 Mid cluster * 2xX1 Big cluster This commit adds the basic device tree for gs101 (SoC). Further platform support will be added over time. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Tested-by: Will McVicker <willmcvicker@google.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20231211162331.435900-15-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-12-13dt-bindings: arm: google: Add bindings for Google ARM platformsPeter Griffin1-0/+53
This introduces bindings and dt-schema for the Google Tensor SoCs. Currently just gs101 and pixel 6 are supported. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20231211162331.435900-3-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2023-12-13arm64: dts: renesas: white-hawk-cpu: Fix missing serial console pin controlGeert Uytterhoeven1-0/+3
The pin control description for the serial console was added, but not enabled, due to missing pinctrl properties in the serial port device node. Fixes: 7a8d590de8132853 ("arm64: dts: renesas: white-hawk-cpu: Add serial port pin control") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/8a51516581cd71ecbfa174af9c7cebad1fc83c5b.1702459865.git.geert+renesas@glider.be
2023-12-13arm64: dts: renesas: rzg3s-smarc-som: Enable the Ethernet interfacesClaudiu Beznea1-1/+140
The RZ/G3S Smarc Module has Ethernet PHYs (KSZ9131) connected to each Ethernet IP. For this, add proper DT descriptions to enable Ethernet communication through these PHYs. The interface b/w PHYs and MACs is RGMII. The skew settings were set to zero as based on phy-mode (rgmii-id) the KSZ9131 driver enables internal DLL, which adds a 2ns delay b/w clocks (TX/RX) and data signals. Different pin settings were applied to TXC and TX_CTL compared with the rest of the RGMII pins to comply with requirements for these pins imposed by HW manual of RZ/G3S (see chapters "Ether Ch0 Voltage Mode Control Register (ETH0_POC)", "Ether Ch1 Voltage Mode Control Register (ETH1_POC)", for power source selection, "Ether MII/RGMII Mode Control Register (ETH_MODE)" for output-enable and "Input Enable Control Register (IEN_m)" for input-enable configurations). Also enable the Ethernet interfaces by selecting SW_CONFIG3 = SW_ON. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231207070700.4156557-12-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-12-13arm64: dts: renesas: rzg3s-smarc-som: Use switches' names to select on-board ↵Claudiu Beznea1-13/+21
functionalities The intention of the SW_SD0_DEV_SEL and SW_SD2_EN macros was to reflect the state of the SW_CONFIG individual switches available on the RZ/G3S Smarc Module, and at the same time to have a descriptive name for the switches themselves. Each individual switch is associated with a signal name, which might be active-low or not on the board. Using signal names instead of SW_CONFIG switch names may be confusing for a user who just playes with switches to select individual functionalities, but also for an advanced user who looks at the schematics. To avoid even further confusion, use the switches' names here and instantiate them with an ON/OFF state. This should be simpler, even though the name of the switches is not that intuitive. The switches' names documentation reflects the switches' purposes. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231207070700.4156557-11-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-12-13arm64: dts: renesas: r9a08g045: Add Ethernet nodesClaudiu Beznea1-0/+38
Add the Ethernet nodes available on RZ/G3S (R9A08G045). Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231207070700.4156557-10-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-12-13arm64: dts: renesas: r9a08g045: Add IA55 interrupt controller nodeClaudiu Beznea1-0/+68
Add IA55 interrupt controller node and set it as interrupt parent for pin controller. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231120111820.87398-10-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-12-13arm64: zynqmp: Add missing destination mailbox compatibleMichal Simek1-0/+1
The commit 81186dc16101 ("dt-bindings: zynqmp: add destination mailbox compatible") make compatible string for child nodes mandatory that's why add it. Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-12-13arm64: zynqmp: Fix clock node name in kv260 cardsMichal Simek2-12/+12
node name shouldn't use '_' that's why convert it to '-'. Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-12-13arm64: zynqmp: Move fixed clock to / for kv260Michal Simek2-29/+29
fixed clock nodes can't be on the bus because they are missing reg property. That's why move them to root. And because it is root it is good to have it as the first node in a file. Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-12-13dt-bindings: soc: Add new board description for MicroBlaze VMichal Simek1-0/+5
MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP. It is hardware compatible with classic MicroBlaze processor. Processor can be used with standard AMD/Xilinx IPs including interrupt controller and timer. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-12-13dt-bindings: soc: xilinx: Move xilinx.yaml from arm to socMichal Simek2-1/+2
All Xilinx boards can hosts also soft core CPUs like MicroBlaze or MicroBlaze V (RISC-V ISA) that's why move boards description from arm folder to soc folder. Similar change was done for Renesas by commit c27ce08b806d ("dt-bindings: soc: renesas: Move renesas.yaml from arm to soc"). Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-12-13arm64: xilinx: Remove address/size-cells from gem nodesMichal Simek1-8/+0
Some boards are using one mdio bus which holds multiple phys and also boards are using mdio node for bus description. That's why there are cases where address/size-cells are unnecessary which is also reported by make W=1 dtbs. That's why remove them from zynqmp.dtsi and let board DTSes to handle it based on used description. Error log: /axi/ethernet@ff0e0000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/7252203d52af3ca8867764c8514affc4828e530d.1695040866.git.michal.simek@amd.com
2023-12-13arm64: xilinx: Remove address/size-cells from flash nodeMichal Simek1-2/+0
Partitions are described via fixed-partitions that's why there is no need to have address/size-cells in flash node. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/c4447028f914e77b8c28640dc458b8409198ee30.1695040866.git.michal.simek@amd.com
2023-12-13arm64: xilinx: Put ethernet phys to mdio nodeMichal Simek5-23/+43
All zynqmp boards have been already described via mdio node that's why also convert zc1751. With using mdio node there is an option to add reset property for the whole mdio bus. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/dc228a27579b48f3e768fcb439d118b4a0f0ef5b.1695040866.git.michal.simek@amd.com
2023-12-13arm64: xilinx: Remove mt25qu512a compatible string from SOMMichal Simek1-1/+1
mt25qu512a is not documented in DT binding that's why remove it. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/a1e975f5785dfb6eb04e8d5905dcaa7467ccd585.1695040866.git.michal.simek@amd.com
2023-12-13arm64: xilinx: Use lower case for partition addressMichal Simek1-2/+2
Lower case should be used for register address. Issue is reported as: flash@0: partitions: Unevaluated properties are not allowed ('partition@22A0000' was unexpected) Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/a96ac9a32a363b04958157548f290d480c21590c.1695040866.git.michal.simek@amd.com
2023-12-13arm64: xilinx: Do not use '_' in DT node namesMichal Simek2-5/+5
Character '_' not recommended in node name. Use '-' instead. Pretty much run seds below for node names. s/zynqmp_ipi/zynqmp-ipi/ s/nvmem_firmware/nvmem-firmware/ s/soc_revision/soc-revision/ s/si5335_/si5335-/ Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/5137958580c85a35cf6aadd1c33a2f6bcf81a9e5.1695040866.git.michal.simek@amd.com
2023-12-13arm64: dts: xilinx: Apply overlays to base dtbsRob Herring1-5/+4
DT overlays in tree need to be applied to a base DTB to validate they apply, to run schema checks on them, and to catch any errors at compile time. Defining the "-dtbs" variable is not enough as the combined DT must be added to dtbs-y. zynqmp-sck-kr-g-revA.dtso and zynqmp-sck-kr-g-revB.dtso don't exist, so drop them. Signed-off-by: Rob Herring <robh@kernel.org> Fixes: 45fe0dc4ea2e ("arm64: xilinx: Use zynqmp prefix for SOM dt overlays") Link: https://lore.kernel.org/r/20230911214751.2202913-1-robh@kernel.org Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-12-13riscv: dts: starfive: Enable SDIO wifi on JH7100 boardsEmil Renner Berthing1-0/+60
Add pinctrl and MMC controller nodes for the Broadcom wifi controller on the BeagleV Starlight and StarFive VisionFive V1 boards. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-12-13riscv: dts: starfive: Enable SD-card on JH7100 boardsEmil Renner Berthing1-0/+47
Add pinctrl and MMC device tree nodes for the SD-card on the BeagleV Starlight and StarFive VisionFive V1 boards. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-12-13riscv: dts: starfive: Add JH7100 MMC nodesEmil Renner Berthing1-0/+26
Add device tree nodes for the Synopsis MMC controllers on the StarFive JH7100 SoC. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-12-13riscv: dts: starfive: Add pool for coherent DMA memory on JH7100 boardsEmil Renner Berthing1-0/+24
The StarFive JH7100 SoC has non-coherent device DMAs, but most drivers expect to be able to allocate coherent memory for DMA descriptors and such. However on the JH7100 DDR memory appears twice in the physical memory map, once cached and once uncached: 0x00_8000_0000 - 0x08_7fff_ffff : Off chip DDR memory, cached 0x10_0000_0000 - 0x17_ffff_ffff : Off chip DDR memory, uncached To use this uncached region we create a global DMA memory pool there and reserve the corresponding area in the cached region. However the uncached region is fully above the 32bit address limit, so add a dma-ranges map so the DMA address used for peripherals is still in the regular cached region below the limit. Link: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-12-13riscv: dts: starfive: Add JH7100 cache controllerEmil Renner Berthing1-0/+13
The StarFive JH7100 SoC also features the SiFive L2 cache controller, so add the device tree nodes for it. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-12-13riscv: dts: starfive: Mark the JH7100 as having non-coherent DMAsEmil Renner Berthing1-0/+1
The StarFive JH7100 SoC has non-coherent device DMAs, so mark the soc bus as such. Link: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Cache%20Coherence%20V1.0.pdf Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-12-13riscv: dts: starfive: Group tuples in interrupt propertiesGeert Uytterhoeven1-4/+4
To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped. Fix this by grouping the tuples of "interrupts-extended" properties using angle brackets. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-29 20:14:04 +0300