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2015-01-15ARM: at91: dts: sama5d3: change name of pinctrl_isi_{power,reset}Josh Wu1-3/+3
For sama5d3xmb board, the pins: pinctrl_isi_{power,reset} is used to power-down or reset camera sensor. So we should let camera sensor instead of ISI to configure the pins. This patch will change pinctrl name from pinctrl_isi_{power,reset} to pinctrl_sensor_{power,reset}. And remove these two pinctrl from ISI's DT node. We will add these two pinctrl to sensor's DT node. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2015-01-15ARM: at91: dts: sama5d3: move the isi mck pin to mbBo Shen2-5/+5
The mck is decided by the board design, move it to mb related dtsi file. Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2015-01-15ARM: at91: dts: sama5d3: add missing pins of isiBo Shen1-0/+6
The ISI has 12 data lines, add the missing two data lines. Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2015-01-15ARM: at91: dts: sama5d3: split isi pinctrlBo Shen2-4/+9
As the ISI has 12 data lines, however we only use 8 data lines with sensor module. So, split the data line into two groups which make it can be choosed depends on the hardware design. Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2015-01-15ARM: at91: dts: sama5d3: add isi clockJosh Wu1-0/+2
Add ISI peripheral clock in sama5d3.dtsi. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2015-01-15ARM: at91/dt: ethernut5: use at91sam9xe.dtsiAlexandre Belloni1-1/+1
The ethernut5 is actually based on an at91sam9xe, use the correct dts include. Cc: Martin Reimann <martin.reimann@egnite.de> Cc: Tim Schendekehl <tim.schendekehl@egnite.de> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2015-01-15ARM: at91/dt: Add a dtsi for at91sam9xeAlexandre Belloni2-0/+61
at91sam9xe is slightly different from at91sam9260, in particular it has a different SRAM size and location. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2015-01-15ARM: at91/dt: add SRAM nodesAlexandre Belloni11-2/+64
Add nodes for the SRAM available on atmel SoCs For the at91sam9260 and the at91sam9g20, address mirroring is used to create a single contiguous SRAM range instead of declaring two separate banks. Also remove leftover TODOs in the sam9g45 file Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> [nicolas.ferre@atmel.com: correct at91sam9rl sram size => 0x10000] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2015-01-15ARM: at91/dt: at91rm9200ek: enable RTCAlexandre Belloni1-0/+4
Enable the RTC on the at91rm9200ek. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2015-01-15ARM: at91/dt: rm9200: add RTC nodeAlexandre Belloni1-0/+7
Add a node for the RTC available on at91rm9200. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2015-01-15ARM: at91/dt: at91sam9n12: Add RTC nodeAlexandre Belloni1-0/+7
Add node for the RTC available on the at91sam9n12. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2015-01-15ARM: at91: sama5d4: Add SFRAlexandre Belloni1-0/+5
The sama4d4 has Special Function Registers that allow to manage DDR, OHCI, EBI and AIC interrupt redirection. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> [nicolas.ferre@atmel.com: reg size: 0x60] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2015-01-15ARM: at91: sama5d3: Add SFRAlexandre Belloni1-0/+5
The sama5d3 has Special Function Registers that allow to manage OHCI, EBI and the UTMI clock. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> [nicolas.ferre@atmel.com: reg size: 0x60] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2015-01-15ARM: at91: Add Special Function Registers binding documentationAlexandre Belloni1-0/+16
The special function registers gather some registers that allow to tweak features provided by IPs controlled through another register range. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> [nicolas.ferre@atmel.com: reg size: 0x60] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2015-01-15ARM: at91/dt: sam9263: Fix typo: ac91_clk -> ac97_clkAlexander Stein1-1/+1
That clock should be called ac97_clk. Signed-off-by: Alexander Stein <alexanders83@web.de> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2015-01-15ARM: at91/dt: sama5d3: enable D2 as the heartbeat LEDJosh Wu1-0/+1
This D2 led is available for all sama5d3x-ek board. So make it a heartbeat LED. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2015-01-15Merge tag 'mvebu-dt-3.20' of git://git.infradead.org/linux-mvebu into next/dtOlof Johansson13-20/+830
Merge "mvebu: dt for v3.20" from Andrew Lunn: mvebu dt changes for v3.20 (part #1) - Add Armada 388 General Purpose Development Board support - Add Device Tree description of the Armada 388 SoC - Document the Device Tree binding for the Armada 388 SoC - a38x: Add missing labels - a38x: Add more pinctrl functions - Add Armada 385 Access Point Development Board support - Add a number of pinctrl functions - A38x: Remove redundant pinctrl informations - a38x: Fix node names - Add support for Seagate BlackArmor NAS220 - kirkwood: enable phy driver for SATA controller on 88f6192 - gpio_poweroff support for Iomega ix2-200 - Use all remaining MTD space foor rootfs of Iomega ix2-200 * tag 'mvebu-dt-3.20' of git://git.infradead.org/linux-mvebu: ARM: mvebu: Add Armada 388 General Purpose Development Board support ARM: mvebu: Add Device Tree description of the Armada 388 SoC ARM: mvebu: Document the Device Tree binding for the Armada 388 SoC ARM: mvebu: a38x: Add missing labels ARM: mvebu: a38x: Add more pinctrl functions ARM: mvebu: Add Armada 385 Access Point Development Board support ARM: mvebu: Add a number of pinctrl functions ARM: mvebu: A38x: Remove redundant pinctrl informations ARM: mvebu: a38x: Fix node names Kirkwood: add support for Seagate BlackArmor NAS220 ARM: dts: kirkwood: enable phy driver for SATA controller on 88f6192 ARM: dts: add gpio_poweroff support for Iomega ix2-200 ARM: dts: use all remaining MTD space foor rootfs of Iomega ix2-200 Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Olof Johansson <olof@lixom.net>
2015-01-15ARM: shmobile: sh73a0 dtsi: Add memory-controller nodesGeert Uytterhoeven1-0/+16
Add device nodes for the two SDRAM Bus State Controllers. The SBSCs are located in the A4BC0 resp. A4BC1 PM domains, which must not be powered down, else the system will crash. References to the A4BC0 and A4BC1 PM domains will be added later. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-01-15ARM: shmobile: r8a7740 dtsi: Add memory-controller nodeGeert Uytterhoeven1-0/+6
Add a device node for the DDR3 Bus State Controller (DBSC3). The DBSC3 is located in the A4S PM domain, which must not be powered down, else the system will crash. This has no visible effect for now, as A4S was never turned off anyway because its child PM domain A3SM contains the CPU core. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-01-15ARM: shmobile: r8a73a4 dtsi: Add memory-controller nodesGeert Uytterhoeven1-0/+10
Add device nodes for the two DDR Bus State Controllers (DBSC). The DBSCs are located in the A3BC PM domain, which must not be powered down, else the system will crash. A reference to the A3BC PM domain will be added later. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-01-15ARM: shmobile: Add DT bindings for Renesas memory controllersGeert Uytterhoeven1-0/+44
Add DT bindings for Renesas R-Mobile and SH-Mobile memory controllers. Currently memory controller device nodes are used only to reference PM domains, and prevent these PM domains from being powered down, which would crash the system. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-01-14ARM: dts: Configure regulators for suspend on exynos Peach boardsJavier Martinez Canillas2-0/+162
The regulator core now has support to choose if a regulator has to be enabled or disabled during system suspend and also supports changing the regulator operating mode during runtime and when the system enters into sleep mode. To lower power during suspend, configure the regulators state using the same configuration found in the ChromeOS 3.8 kernel Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Kukjin Kim <kgene@kernel.org>
2015-01-14ARM: dts: Set Peach boards USB WebCam regulators to always onJavier Martinez Canillas2-0/+2
The Exynos5420 Peach Pit and Exynos5800 Peach Pi boards have a built-in Silicon Motion USB UVC WebCam whose power supply is the tps65090 fet5 regulator. Since the camera uses the generic USB Video Class driver and this does not grab a regulator, mark the regulator as always on so the USB device is enumerated and usable. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Kukjin Kim <kgene@kernel.org>
2015-01-14ARM: dts: Add lid GPIO key device node for Peach boardsJavier Martinez Canillas2-2/+35
The Exynos5420 Peach Pit and Exynos5800 Peach Pi boards have both a power and lid GPIO keys but only the former was defined in the DTS. Add DTS snippets for the lid GPIO key too. These were taken from the downstream ChromeOS 3.8 kernel tree. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Kukjin Kim <kgene@kernel.org>
2015-01-14ARM: dts: Add power and lid GPIO keys pinctrl for exynos5250-snowJavier Martinez Canillas1-0/+16
The Exynos5250 Snow Chromebook has GPIO keys for power and lid so the SoC I/O pins have to be configured in external interrupt mode. Currently, this is working without setting the pinctrl lines but is better to set it explicitly instead of relying on the previous state of the I/O pins. The DTS snippets were taken from the downstream ChromeOS tree. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Kukjin Kim <kgene@kernel.org>
2015-01-14Merge tag 'v3.20-next-dts' of https://github.com/mbgg/linux-mediatek into ↵Olof Johansson9-11/+185
next/dt Merge "ARM: mediatek: DT changes for v3.20 (round 1)" from Matthias Brugger: This adds support for the mediatek sysirq and the uarts for the following SoCs: - mt8135 - mt8127 - mt6598 For mt6592 only the sysirq support was added. * tag 'v3.20-next-dts' of https://github.com/mbgg/linux-mediatek: ARM: mediatek: dts: Add uart to Aquaris5 ARM: mediatek: dts: Add uart to mt6589 dt-bindings: add mt6592 compatible string for mediatek sysirq ARM: mediatek: Add sysirq device node to mt6592 dtsi ARM: mediatek: dts: Add UART dts for MT8127 and MT8135 boards DTS: serial: Add bindings document for the Mediatek UARTs ARM: mediatek: add UART dts for mt8127 and mt8135 ARM: mediatek: Add sysirq in mt6589/mt8135/mt8127 dtsi Signed-off-by: Olof Johansson <olof@lixom.net>
2015-01-13ARM: dts: omap3-gta04: Add handling for tv outputMarek Belisko1-0/+49
Add handling for gta04 tv out chain: venc -> opa362 -> svideo Use invert-polarity in venc node because opa362 is doing polarity inversion also. Signed-off-by: Marek Belisko <marek@goldelico.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-01-13ARM: dts: cm-t3x: add NAND supportDmitry Lifshitz5-10/+70
CM-T3517, CM-T3530 and CM-T3730 features NAND storage chip connected to GPMC bus. Add GPMC DT entry into the root DT file omap3-cm-t3x.dtsi, common for all three modules. NAND timings are calculated to be safe for CM-T3x devices as it works now in non DT boot (in this case the timings are updated by U-Boot). Update GPMC ranges in boards DT files to include all connected devices. Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2015-01-13ARM: dts: add init dts file for CSR atlas7 SoCZhiwu Song4-0/+928
CSR atlas7 uses Network on Chip(NoC) bus architecture, there are dozens of MARCOs, in each MARCO, there are dozens of hardware modules. Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com> Signed-off-by: Hao Liu <Hao.Liu@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2015-01-13ARM: dts: vfxxx: Add SNVS nodeSanchayan Maity2-0/+18
Add device tree node for the Secure Non-Volatile Storage (SNVS) on the VF610 platform. The SNVS block also has a Real Time Counter (RTC). Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-01-13Merge branch 'imx/soc' into imx/dtShawn Guo14-20/+193
2015-01-13ARM: imx: clk-vf610: Add clock for SNVSSanchayan Maity2-1/+4
Add support for clock gating of the SNVS peripheral. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-01-13ARM: imx: clk-vf610: Add clock for UART4 and UART5Bhuvanchandra DV1-0/+2
Add support for clock gating of UART4 and UART5. We use these UART's in a (not yet mainlined) device tree. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2015-01-13ARM: shmobile: r8a7791: add SRC interrupt number on DTSIKuninori Morimoto1-10/+10
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-01-13ARM: shmobile: r8a7790: add SRC interrupt number on DTSIKuninori Morimoto1-10/+10
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-01-13ARM: shmobile: r8a7791: fix MSTP8 input clocksSergei Shtylyov1-1/+1
I made a mistake when rebasing Andrey Gusakov's patch adding MLB+ clock to the R8A7791 device tree, inserting <&hp_clk> into the "clocks" property of the MSTP8 node at a wrong position, so that the input clocks for MLB+ and IPMMU-SGX got swapped... Fixes: 7408d3061d2f ("ARM: shmobile: r8a7791: add MLB+ clock") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-01-13ARM: shmobile: r8a7740 dtsi: Add PM domain supportGeert Uytterhoeven1-0/+99
Add a device node for the System Controller, with subnodes that represent the hardware power area hierarchy. Hook up all devices to their respective PM domains. Add a minimal device node for the Coresight-ETM hardware block, and hook it up to the D4 PM domain, so the R-Mobile System Controller driver can keep the domain powered, until the new Coresight code handles runtime PM. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-01-13PM / Domains: Add DT bindings for the R-Mobile System ControllerGeert Uytterhoeven1-0/+98
The Renesas R-Mobile System Controller provides a.o. power management support, following the generic PM domain bindings in Documentation/devicetree/bindings/power/power_domain.txt. For now this supports the R-Mobile A1 (r8a7740) only, but it should be sufficiently generic to handle other members of the SH-Mobile/R-Mobile family in the future. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-01-13ARM: shmobile: r8a7791: tidyup #sound-dai-cells settingsKuninori Morimoto2-1/+7
Renesas sound driver needs #sound-dai-cells settings, but, this usage is a little bit confusable. It came from ALSA SoC historical reasons. The sound DAI naming method is different between Single/Multi DAI in the ALSA framework, and it is used for sound card matching. And this #sound-dai-cells has relationship to it. Current SoC dtsi has #sound-dai-cells = <1> as default settings (= it is assuming that board/platform has multi DAI), and board/platform side needs to overwrite it if board/platform was single DAI. This style is more confusable for users. This patch removes SoC side default settings, and force to set it by board/platform side. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-01-13ARM: shmobile: r8a7790: tidyup #sound-dai-cells settingsKuninori Morimoto2-1/+7
Renesas sound driver needs #sound-dai-cells settings, but, this usage is a little bit confusable. It came from ALSA SoC historical reasons. The sound DAI naming method is different between Single/Multi DAI in the ALSA framework, and it is used for sound card matching. And this #sound-dai-cells has relationship to it. Current SoC dtsi has #sound-dai-cells = <1> as default settings (= it is assuming that board/platform has multi DAI), and board/platform side needs to overwrite it if board/platform was single DAI. This style is more confusable for users. This patch removes SoC side default settings, and force to set it by board/platform side. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-01-13ARM: shmobile: r8a7791 dtsi: Drop "renesas,rcar_sound" compatible valueGeert Uytterhoeven1-1/+1
The "renesas,rcar_sound" compatible property value was never processed nor documented. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-01-13ARM: shmobile: r8a7790 dtsi: Drop "renesas,rcar_sound" compatible valueGeert Uytterhoeven1-1/+1
The "renesas,rcar_sound" compatible property value was never processed nor documented. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-01-13Merge tag 'berlin-dt-for-3.20-1' of ↵Olof Johansson3-3/+16
git://git.infradead.org/users/hesselba/linux-berlin into next/dt Merge "ARM: berlin: DT changes for v3.20 (round 1)" from Sebastian Hesselbarth: Berlin DT changes for v3.20 (round 1) - add PMU nodes for BG2Q and BG2CD - add PPI CPU masks for TWD timer interrupts * tag 'berlin-dt-for-3.20-1' of git://git.infradead.org/users/hesselba/linux-berlin: ARM: dts: berlin: add PPI cpu mask to twd timer interrupts ARM: dts: berlin: add pmu node for BG2Q and BG2CD Signed-off-by: Olof Johansson <olof@lixom.net>
2015-01-13ARM: dts: Only build dtb if associated Arch and/or SoC is enabledPeter Robinson1-73/+142
A number of arches (EXYNOS/IMX/TEGRA) are separated out into finer grained definitions whether it be sub ARCH or SOC definitions. The device tree blobs should only be built if the specific option is enabled that supports that device or it might be that there's an expectation that the device is supported when in actual fact it's not. This ensures only the relevant bits are built. Also standardised the line break between the arch/soc definitions and the dtbs to be on separate lines for better consistency as per feedback. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Shawn Guo <shawn.guo@freescale.com> [olof: Fixed stray \ in one of the IMX rules] Signed-off-by: Olof Johansson <olof@lixom.net>
2015-01-13Merge tag 'renesas-dt-for-v3.20' of ↵Olof Johansson13-81/+333
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt Merge "Renesas ARM Based SoC DT Updates for v3.20" from Simon Horman: * Use clock-indices instead of deprecated renesas,clock-indices * Prepare for r8a73a4 multiplatform support * Increase clock coverage for r8a779[014] * Correct r8a7779 clock usage * Correct LAN9220 VDDVARIO voltage on ape6evm * Correct QSPI SPI-Flash mode of lager and koelsch * Correct flash partition label and size on koelsch * Correct mask for GIC PPI interrupts on r8a779[14] * Correct BSC bus range on ape6evm-reference * tag 'renesas-dt-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (30 commits) ARM: shmobile: r8a7791: add MLB+ clock ARM: shmobile: r8a7790: add MLB+ clock ARM: shmobile: ape6evm: Fix LAN9220 VDDVARIO voltage ARM: shmobile: r8a73a4: Add r8a73a4-ape6evm.dtb to ARCH_SHMOBILE_MULTI ARM: shmobile: ape6evm: Add keypad to the device tree ARM: shmobile: ape6evm: Add LEDs to the device tree ARM: shmobile: ape6evm: synchronize dts with reference platform ARM: shmobile: ape6evm: fix compatible string for Ethernet controller ARM: shmobile: r8a7794: Add MMCIF clock to device tree ARM: shmobile: r8a7794: Add SDHI clocks to device tree ARM: shmobile: r8a7794: Add I2C clocks to device tree ARM: shmobile: r8a7779: Add TWD device to DTS ARM: shmobile: r8a7779: Use MSTP for SCIF clocks ARM: shmobile: r8a7779: Use R8A7779_CLK_P as SCIF parent clock ARM: shmobile: r8a7794: Add QSPI clock to device tree ARM: shmobile: lager: Fix QSPI mode of SPI-Flash into mode3 ARM: shmobile: r8a7794: Add SYS-DMAC clocks to device tree ARM: shmobile: r8a7791: Add IPMMU-SGX clock to device tree ARM: shmobile: koelsch: Fix QSPI mode of SPI-Flash into mode3 ARM: shmobile: r8a7794: Add USBDMAC[01] clocks to device tree ... Signed-off-by: Olof Johansson <olof@lixom.net>
2015-01-13Merge tag 'renesas-dt-cleanups-for-v3.20' of ↵Olof Johansson7-17/+17
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt Merge "Renesas ARM Based SoC DT Cleanups for v3.20" from Simon Horman: * Replace status value "ok" with "okay" * tag 'renesas-dt-cleanups-for-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: kzm9g-reference dts: Replace status value "ok" by "okay" ARM: shmobile: alt dts: Replace status value "ok" by "okay" ARM: shmobile: koelsch dts: Replace status value "ok" by "okay" ARM: shmobile: henninger dts: Replace status value "ok" by "okay" ARM: shmobile: lager dts: Replace status value "ok" by "okay" ARM: shmobile: armadillo800eva dts: Replace status value "ok" by "okay" ARM: shmobile: genmai dts: Replace status value "ok" by "okay" Signed-off-by: Olof Johansson <olof@lixom.net>
2015-01-12clk: rockchip: add clock IDs for the PVTM clocksHuang Lin1-0/+2
Process-Voltage-Temperature Monitor has two clocks, PVTM_CORE and PVTM_GPU. Signed-off-by: Huang Lin <hl@rock-chips.com> Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-01-12clk: rockchip: add clock ID for usbphy480m_srcKever Yang1-0/+1
There are 3 different parent clock from different usbphy, all of them are fixed 480MHz, it is not able to auto select by clock core to the 2nd and the 3rd parent. For different use case for different board, we may need to select different usbphy clock out as parent manually. Add the clock ID for it so that we can use in dts. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-01-12Documentation: dt-bindings: add exynos-chipid binding informationPankaj Dubey1-0/+12
Exynos SoC's DT files are using Chipid device nodes, but it's binding information is missing. This patch adds exynos-chipid binding information. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
2015-01-12ARM: dts: add Panel device support for exynos3250-rinatoInki Dae1-0/+59
This patch adds MIPI-DSI and MIPI-DSI based S6E63J0X03 AMOLED panel device nodes for Exynos3250 Rinato board. Signed-off-by: Inki Dae <inki.dae@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
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