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2018-03-13arm64: dts: renesas: r8a77965: Add #pwm-cells propertyJacopo Mondi1-0/+1
Add "#pwm-cells" property to "pwm@e6e31000" device node. This silences the following DTC compiler warning: Warning (pwms_property): Missing property '#pwm-cells' in node /soc/pwm@e6e31000 or bad phandle (referred from /backlight:pwms[0]) Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-13arm64: dts: renesas: r8a77965: Add #phy-cells propertyJacopo Mondi1-0/+1
Add "#phy-cells" property to "usb-phy@e65ee000" device node. This silences the following DTC compiler warning: Warning (phys_property): Missing property '#phy-cells' in node /soc/usb-phy@e65ee000 or bad phandle (referred from /soc/usb@ee020000:phys[0]) Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-13arm64: dts: renesas: r8a77965: Remove stale reg propertyJacopo Mondi1-1/+0
Remove "reg" property from cache-controller-0 device node as it does not have any unit address. This silences the following DTC compiler warning: Warning (unit_address_vs_reg): Node /cpus/cache-controller-0 has a reg or ranges property, but no unit name Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-13arm64: dts: renesas: r8a77965: Add #address-cells and #size-cellsJacopo Mondi1-0/+25
Add "#address-cells" and "#size-cells" properties to all place-holder nodes that have children nodes defined by salvator-x[s].dtsi device tree. This silences the following DTC compiler warnings: Warning (reg_format): "reg" property in /soc/.. has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) Warning (avoid_default_addr_size): Relying on default #address-cells value for /soc/... Warning (avoid_default_addr_size): Relying on default #size-cells value for /soc/... Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-13arm64: dts: renesas: r8a77965: Add "reg" propertiesJacopo Mondi1-0/+51
Add "reg" properties to place-holder nodes with unit address defined for R-Car M3-N SoC. This silences the following DTC compiler warning: Warning (unit_address_vs_reg): Node /soc/... has a unit name, but no reg property Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-13arm64: dts: renesas: r8a77965: Add GPIO nodesJacopo Mondi1-8/+96
Add GPIO nodes to r8a77965 SoC device tree file. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-13arm64: dts: renesas: r8a77965: Add SCIF device nodesJacopo Mondi1-6/+79
Add SCIF[0-5] device nodes for M3-N (r8a77965) SoC. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-13arm64: dts: renesas: r8a77965: Add dmac device nodsJacopo Mondi1-3/+93
Add dmac[0-2] device nodes for R-Car M3-N (r8a77965) SoC. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-13arm64: dts: renesas: Add R-Car Salvator-x M3-N supportJacopo Mondi2-0/+22
Add basic support for R-Car Salvator-X M3-N (R8A77965) board. Based on original work from: Takeshi Kihara <takeshi.kihara.df@renesas.com> Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-13arm64: dts: renesas: initial R8A77965 SoC device treeJacopo Mondi1-0/+490
Basic support for the Gen 3 R-Car M3-N SoC. Based on original work from: Takeshi Kihara <takeshi.kihara.df@renesas.com> Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-13arm64: add Renesas R8A77965 supportJacopo Mondi1-0/+6
Add configuration option for the R-Car M3-N (R8A77965) SoC. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-13arm64: dts: renesas: r8a7795: Update OPPs to support CA53 dfsDien Pham1-0/+10
Describe frequencies, other than the default for CA53 cores. This is a pre-requisite for using providing alternative frequencies for use with CPUFreq with these cores. Signed-off-by: Dien Pham <dien.pham.ry@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-13arm64: dts: renesas: r8a7796: Update OPPs to support CA53 dfsDien Pham1-0/+16
Describe frequencies, other than the default for CA53 cores. This is a pre-requisite for using providing alternative frequencies for use with CPUFreq with these cores. Signed-off-by: Dien Pham <dien.pham.ry@renesas.com> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-03-13ARM: dts: NSP: Switch to port 8 for CPU portFlorian Fainelli5-15/+15
Now that we have added support for pre-pended Broadcom tags with commit 11606039604c ("net: dsa: b53: Support prepended Broadcom tags") we can switch all the Northstar Plus reference boards to use port 8 for the CPU port. This allows us to prepare room for supporting the Flow Accelerator 2 NAPT offload, and frees up port 5 to be made fully configurable for the modes that it supports: internal, SGMII, RGMII etc. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-03-12ARM: bcm2835: Add the DPI hardware to the device tree.Eric Anholt1-0/+11
It's currently marked disabled, as it's not useful without a panel associated with it and the GPIO pins routed to ALT2. Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
2018-03-12ARM: dts: Keystone: add ECC error handler supportMurali Karicheri2-0/+13
Add emif node for keystone2 devices, which is used for ECC support. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> [t-kristo@ti.com: made emif enabled by default for all keystone2 devices] Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-03-12ARM: dts: keystone-k2g: add watchdog supportTero Kristo1-0/+7
Add a watchdog node for keystone-k2g, with the corresponding clock and power domain handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-03-12Merge tag 'at91-ab-4.17-dt' of ↵Arnd Bergmann10-24/+57
ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/abelloni/linux into next/dt Pull "AT91 DT for 4.17" from Alexandre Belloni: Not much this cycle, mainly changes on the Axentia boards from Peter and a cleanup from Bartosz: - use 'atmel' as at24 manufacturer - device addition and fixes for axentia boards - fix sama5d4 pinctrl compatible * tag 'at91-ab-4.17-dt' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/abelloni/linux: ARM: dts: at91: use 'atmel' as at24 manufacturer for at91sam9263ek ARM: dts: at91: use 'atmel' as at24 manufacturer for at91-sama5d2_ptc_ek ARM: dts: at91: use 'atmel' as at24 manufacturer for at91sam9g20ek ARM: dts: at91: use 'atmel' as at24 manufacturer for at91sam9260ek ARM: dts: at91: use 'atmel' as at24 manufacturer for sama5d34ek ARM: dts: at91: sama5d4: fix pinctrl compatible string ARM: dts: at91: tse850: make the sound dai cell count explicit ARM: dts: at91: nattis: add lvds-encoder ARM: dts: at91: nattis: use up-to-date mtd partitions ARM: dts: at91: tse850: use the correct compatible for the eeprom ARM: dts: at91: nattis: use the correct compatible for the eeprom ARM: dts: at91: sam9rl: Properly assign copyright
2018-03-12Merge tag 'mvebu-dt64-4.17-1' of git://git.infradead.org/linux-mvebu into ↵Arnd Bergmann23-880/+172
next/dt Pull "mvebu dt64 for 4.17 (part 1)" from Gregory CLEMENT: - convert to the SPDX-License-Identifier - add missing clocks (for the registers) on some of the peripherals - use the new nand driver - add more uart for Armada 7K/8K SoCs * tag 'mvebu-dt64-4.17-1' of git://git.infradead.org/linux-mvebu: ARM64: dts: marvell: armada-cp110: Add apb_pclk clock for the uart nodes arm64: dts: marvell: use reworked NAND controller driver on Armada 8K arm64: dts: marvell: use reworked NAND controller driver on Armada 7K ARM64: dts: marvell: armada-cp110: Add registers clock for sata node arm64: dts: marvell: armada-8080-db: use SPDX-License-Identifier arm64: dts: marvell: armada-8040-mcbin: use SPDX-License-Identifier arm64: dts: marvell: armada-8040-db: use SPDX-License-Identifier arm64: dts: marvell: armada-7040-db: use SPDX-License-Identifier arm64: dts: marvell: armada-3720-espressobin: use SPDX-License-Identifier arm64: dts: marvell: armada-3720-db: use SPDX-License-Identifier arm64: dts: marvell: use SPDX-License-Identifier for Armada SoCs arm64: dts: marvell: mcbin: fix board name typo arm64: dts: marvell: mcbin: enable uart headers arm64: dts: marvell: add CP110 uart peripherals ARM64: dts: marvell: armada-cp110: Add registers clock for I2C nodes ARM64: dts: marvell: armada-cp110: Add registers clock for SPI nodes
2018-03-12Merge tag 'mvebu-dt-4.17-1' of git://git.infradead.org/linux-mvebu into next/dtArnd Bergmann6-10/+7
Pull "mvebu dt for 4.17 (part 1)" from Gregory CLEMENT: Most of them are small fixes or cleanup. Only the change on the clearfog will have a noticeable effect allowing to use the i2c at an higher frequency. * tag 'mvebu-dt-4.17-1' of git://git.infradead.org/linux-mvebu: ARM: dts: armada388-clearfog: increase speed of i2c0 to 400kHz arm: dts: kirkwood: fix error in #sound-dai-cells size ARM: dts: kirkwood: Fix "debounce-interval" property misspelling ARM: dts: armada: netgear-rn*: fix rtc node name
2018-03-12Merge tag 'hisi-arm64-dt-for-4.17' of git://github.com/hisilicon/linux-hisi ↵Arnd Bergmann5-30/+103
into next/dt Pull "ARM64: DT: Hisilicon SoC DT updates for 4.17" from Wei Xu: - Add XGE CPLD control support for hip07 SoC - Disable the SMMU on hip06 and hip07 SoCs becuase of the hardware limitation - Enable HS200 mode for the MMC controller on hi6220 hikey board - Remove "cooling-{min|max}-level" this kind unused properties for hi6220 SoC - Add watchdog node for hi6220 SoC - Remove "CPU_NAP" idle state on hikey960 board since it is not stable and useless with the updated firmware * tag 'hisi-arm64-dt-for-4.17' of git://github.com/hisilicon/linux-hisi: arm64: dts: Hi3660: Remove 'CPU_NAP' idle state arm64: dts: hi6220: enable watchdog ARM64: dts: hi6220: Remove "cooling-{min|max}-level" for CPU nodes arm64: dts: hikey: Enable HS200 mode on eMMC arm64: dts: hisi: Disable hisilicon smmu node on hip06/hip07 arm64: dts: hisi: add hns-dsaf cpld control for the hip07 SoC
2018-03-12Merge tag 'xilinx-dt-for-4.17' of https://github.com/Xilinx/linux-xlnx into ↵Arnd Bergmann35-77/+3723
next/dt Pull "arm: Xilinx(Zynq and ZynqMP) DT changes for v4.17" from Michal Simek: - Use SPDX license identifier - Add Xilinx ZynqMP boards zcu100-revC, zcu102-revA/revB/rev1.0, zcu104-revA, zcu106-revA, zcu111-revA, zc1751 dc1/dc2/dc3/dc4 - Add Xilinx Zynq boards cc108, zc770 dc1/dc2/dc3/dc4 - Add Digilent Zybo Z7 - Minor fixes in current DTSes * tag 'xilinx-dt-for-4.17' of https://github.com/Xilinx/linux-xlnx: (22 commits) arm: dts: zynq: Add Digilent Zybo Z7 board arm: zynq: Add support for Xilinx zc770 xm013 dc4 board arm: zynq: Add support for Xilinx zc770 xm012 dc3 board arm: zynq: Add support for Xilinx zc770 xm011 dc2 board arm: zynq: Add support for Xilinx zc770 xm010 dc1 board arm: zynq: Add Xilinx cc108 board arm: zynq: Add missing address node name in microzed board arm: dts: zynq: Use SPDX-License-Identifier arm: zynq: Use i2c-mux instead of i2cswitch for pca9548 arm64: zynqmp: Add support for Xilinx zc1751 arm64: zynqmp: Add support for Xilinx zc12XX boards arm64: zynqmp: Add support for Xilinx zcu111-revA arm64: zynqmp: Add support for Xilinx zcu106-revA arm64: zynqmp: Add support for Xilinx zcu104-revA arm64: zynqmp: Add support for Xilinx zcu102 arm64: zynqmp: Add support for Xilinx zcu100-revC dt-bindings: xilinx: Add description for ZynqMP arm64: zynqmp: Add 8-bit bus width property for ep108 arm64: zynqmp: Added OOB timing settings in zynqmp-ep108.dts arm64: zynqmp: Add SPDX license identifier ...
2018-03-12dt-bindings: ifc: Fix the unit address format in the examplesFabio Estevam1-3/+3
DTC warnings will be seen if these examples are used in a real dts file due to a mismatch in the unit address notation. Align the unit address notation to what is done in the real dts files as per commit f81d7af79575 ("arm64: dts: fsl: fix ifc simple-bus unit address format warnings") Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-03-12ARM: dts: i.MX25: define SSI FIFO depthMartin Kaiser1-0/+2
According to the i.MX25 reference manuals, each SSI has four FIFOs. All of those FIFOs can store up to 15 entries. The fsl_ssi driver's internal default for the FIFO depth in 8. Set our non-default FIFO depth explicitly in the Device Tree. Signed-off-by: Martin Kaiser <martin@kaiser.cx> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-03-09ARM: dts: BCM5301X: add missing LEDs for Buffalo WZR-900DHPINAGAKI Hiroshi1-0/+68
Buffalo WZR-900DHP has 8 LEDs, but there is not LED definitions in the dts and cannot configure these LEDs. I Added missing LED definitions for WZR-900DHP. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> Reviewed-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2018-03-09ARM64: dts: marvell: armada-cp110: Add apb_pclk clock for the uart nodesGregory CLEMENT1-4/+12
This extra clock is needed to access the registers of the UARTs used on CP110 component of the Armada 7K/8K SoCs. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2018-03-08ARM: tegra: apalis-tk1: Support v1.2 hardware revisionMarcel Ziswiler3-0/+2303
Support the V1.2 hardware revision with the following pin muxing changes: Ddc_scl_pv4 and ddc_sda_pv5 previously used as Apalis GPIO3 and GPIO4 are now used as DDC pins. Gen2_i2c_scl_pt5 and gen2_i2c_sda_pt6 previously used as DDC pins are now used as USB power enable signals. Usb_vbus_en0_pn4 and usb_vbus_en1_pn5 previously used as USB power enable signals are now used as GPIO3 and GPIO4. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: apalis-tk1: Copyright period, spurious newlinesMarcel Ziswiler2-14/+3
Update the copyright period and get rid of some spurious newlines. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: apalis-tk1: Hog group for ethernet, PCIe, reset GPIOsMarcel Ziswiler2-0/+28
The Apalis TK1 module uses some dedicated GPIOs as I210 gigabit Ethernet controller reset and to control RESET_MOCI aka reset module output carrier input on MXM3 pin 26. The Apalis Evaluation Board furthermore uses Apalis GPIO7 on MXM3 pin 15 as reset signal for its PLX PEX 8605 PCIe Switch. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: apalis-tk1: Add missing as3722 gpio0 configurationMarcel Ziswiler1-3/+3
As the AS3722 GPIO0 is also a not connected on our Apalis TK1 module explicitly configure it to high-impedance as well. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: apalis-tk1: Activate PWM pin muxing for pwm3Marcel Ziswiler1-4/+4
Activate PWM pin muxing for Apalis PWM3. Note that the same PWM3 is already active on pu6 being Apalis BKL1_PWM as well. Therefore exporting that one for raw sysfs access will fail and one has to revert to using the PWM backlight. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: apalis-tk1: Set critical tripsMarcel Ziswiler1-24/+3
Set "critical" trip temperatures for cpu, gpu, mem and pllx thermal zones. These trips can trigger shut down or reset. Similar to commit 40823f8e267f ("arm: tegra: set critical trips for Tegra124"). Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: apalis/colibri: Remove unneeded reg propertyMarcel Ziswiler2-2/+0
As described in Documentation/devicetree/bindings/input/touchscreen/stmpe.txt there is no 'reg' property under stmpe_touchscreen, so remove it to fix the following build warning with W=1: arch/arm/boot/dts/tegra30-apalis-eval.dtb: Warning (unit_address_vs_reg): Node /i2c@7000d000/stmpe811@41/stmpe_touchscreen has a reg or ranges property, but no unit name Similar to commit 89277e8e2679 ("ARM: dts: imx6qdl-apalis: Remove unneeded reg property"). Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: apalis/colibri: Use correct compatible for RTCMarcel Ziswiler3-3/+3
All Toradex Carrier Boards use a st,m41t0 compatible RTC. Compared to a st,m41t00 this RTC has also an oscillator fail bit which allows to detect when the RTC lost track of time. Similar to commit c53bec16b150 ("ARM: dts: colibri/apalis: use correct compatible for RTC") covering our NXP i.MX and Vybrid based modules. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: Fix I2C bus frequencies on Apalis/ColibriMarcel Ziswiler7-13/+18
Use a faster speed of 400 kbit/s for regular I2C busses. Use a slower speed of 10 kbit/s for DDC/EDID to improve reliability. Use a slower speed of 100 kbit/s for power I2C to be within specs of the LM95245 temperature sensor. While at it further annotate I2C pin usage. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: venice2: Remove duplicate pcie-1 nodeMarcel Ziswiler1-5/+0
Get rid of duplicate pcie-1 node. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: beaver: Remove invalid uses of rsvd1Marcel Ziswiler1-15/+15
Remove invalid uses of rsvd1 from Beaver device tree. Replace by actual function names of pinmux option 1. Taken from https://github.com/NVIDIA/tegra-pinmux-scripts commit b0aceda108c0 ("remove invalid uses of rsvd1 from beaver config"). Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: Use proper IRQ type definitionsMarcel Ziswiler6-8/+8
This switches a few interrupt definitions that were using either GPIO_ACTIVE_HIGH or GPIO_ACTIVE_LOW as IRQ type, which is invalid. This is mostly a cosmetic change, that doesn't affect any driver. Analogous to Paul's commit 38333641b6dd ("ARM: tegra: nyan: Use proper IRQ type definitions"). Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08dt/bindings: Fix binding examples for Tegra GMI controllerMarcel Ziswiler1-4/+2
Fix devicetree binding examples for the Generic Memory Interface (GMI) bus driver found on Tegra SOCs. While at it also remove double new lines as a left over from Rob's commit 4da722ca19f3 ("dt-bindings: Remove "status" from examples"). Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: Fix ULPI regression on Tegra20Marcel Ziswiler1-1/+1
Since commit f8f8f1d04494 ("clk: Don't touch hardware when reparenting during registration") ULPI has been broken on Tegra20 leading to the following error message during boot: [ 1.974698] ulpi_phy_power_on: ulpi write failed [ 1.979384] tegra-ehci c5004000.usb: Failed to power on the phy [ 1.985434] tegra-ehci: probe of c5004000.usb failed with error -110 Debugging through the changes and finally also consulting the TRM revealed that rather than the CDEV2 clock off OSC requiring such pin muxing actually the PLL_P_OUT4 clock is in use. It looks like so far it just worked by chance of that one having been enabled which Stephen's commit now changed when reparenting sclk away from pll_p_out4 leaving that one disabled. Fix this by properly assigning the PLL_P_OUT4 clock as the ULPI PHY clock. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08dt-bindings: phy: Clarify ULPI PHY source clockMarcel Ziswiler1-1/+3
cdev2 is not actually a clock on Tegra20 but rather a pinmux pad group. PLL_P_OUT4 is the source clock for the ULPI PHY and is output to the DAP_MCLK2 pad. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: Add unit address to VDE IRAM areaThierry Reding1-1/+1
Add the missing unit address for the VDE IRAM area node in accordance with the mmio-sram device tree binding. Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: Add video decoder node on Tegra30Dmitry Osipenko1-0/+27
Add device tree node for the Video Decoder Engine found on Tegra30 SoC's. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: Add IRAM node on Tegra30Dmitry Osipenko1-0/+8
IRAM is a static RAM that consists of four contiguous 64 KiB blocks, it is currently used to store CPU resume code, utilized by the video decoder engine and could be used as a general-purpose fast memory. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08arm64: tegra: Add device tree for the Tegra194 P2972-0000 boardMikko Perttunen3-0/+265
Add device tree files for the Tegra194 P2972-0000 development board. The board consists of the P2888 compute module and the P2822 baseboard. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08arm64: tegra: Add Tegra194 chip device treeMikko Perttunen5-0/+913
Add the chip-level device tree, including binding headers, for the NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices are initially available, enough to boot to UART console. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08dt-bindings: tegra: Add documentation for nvidia,tegra194-pmcMikko Perttunen1-0/+2
The Tegra194 power management controller has one additional register aperture to be specified in the device tree node. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08dt-bindings: tegra: Add missing chips and NVIDIA boardsMikko Perttunen1-0/+16
Add compatibility strings for supported but undocumented Tegra chips (Tegra114/124/132/210/186/194) and reference boards. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: dts: vf610m4: Remove the zero length reg propertyFabio Estevam1-1/+1
All the vf610m4 based boards include the real memory size in their dts files, so remove the the zero length reg property. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-03-08ARM: dts: vf610m4: Remove skeleton.dtsi inclusionFabio Estevam1-1/+8
Since commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi as deprecated") the inclusion of skeleton.dtsi is deprecated, so remove it as this file will eventually go away someday. Move its content to the SoC dtsi file, so that the resultant dtb is the same. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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