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2019-12-24clk: qcom: alpha-pll: Remove useless read from set rateTaniya Das1-6/+1
PLL_MODE read in fabia set rate is not required, thus remove the same. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/1573812304-24074-2-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-24clk: add terminate callback to clk_opsJerome Brunet2-1/+9
Add a terminate callback to the clk_ops to release the resources claimed in .init() Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lkml.kernel.org/r/20190924123954.31561-4-jbrunet@baylibre.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-24clk: let init callback return an error codeJerome Brunet14-35/+72
If the init callback is allowed to request resources, it needs a return value to report the outcome of such a request. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lkml.kernel.org/r/20190924123954.31561-3-jbrunet@baylibre.com Reviewed-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-24clk: actually call the clock init before any other callback of the clockJerome Brunet1-11/+15
__clk_init_parent() will call the .get_parent() callback of the clock so .init() must run before. Fixes: 541debae0adf ("clk: call the clock init() callback before any other ops callback") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lkml.kernel.org/r/20190924123954.31561-2-jbrunet@baylibre.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-24clk: qcom: Add missing msm8998 gcc_bimc_gfx_clkJeffrey Hugo2-0/+15
gcc_bimc_gfx_clk is a required clock for booting the GPU and GPU SMMU. Fixes: 4807c71cc688 (arm64: dts: Add msm8998 SoC and MTP board support) Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lkml.kernel.org/r/20191217164913.4783-1-jeffrey.l.hugo@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-23clk: imx: imx8mq: Switch to clk_hw based APIPeng Fan1-281/+292
Switch the entire clk-imx8mq driver to clk_hw based API. This allows us to move closer to a clear split between consumer and provider clk APIs. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-23clk: imx: imx8mm: Switch to clk_hw based APIPeng Fan1-271/+284
Switch the entire clk-imx8mm driver to clk_hw based API. This allows us to move closer to a clear split between consumer and provider clk APIs. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-23clk: imx: imx8mn: Switch to clk_hw based APIPeng Fan1-238/+251
Switch the entire clk-imx8mn driver to clk_hw based API. This allows us to move closer to a clear split between consumer and provider clk APIs. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-23clk: imx: Remove __init for imx_obtain_fixed_clk_hw() APIPeng Fan1-2/+2
Some of i.MX SoCs' clock driver will use platform driver model, and they need to call imx_obtain_fixed_clk_hw() API, so imx_obtain_fixed_clk_hw() API should NOT be in .init section. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-23clk: imx: gate3: Switch to clk_hw based APIPeng Fan1-2/+5
Switch the imx_clk_hw_gate3_flags function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-23clk: imx: add hw API imx_clk_hw_mux2_flagsPeng Fan1-0/+10
Introduce hw based API imx_clk_hw_mux2_flags, then we could convert i.MX8MN clk driver to use hw based APIs. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-23clk: imx: add imx_unregister_hw_clocksPeng Fan2-0/+9
There is a non hw API based imx_unregister_clocks to unregister clocks when of_clk_add_provider failed. Add a hw API based imx_unregister_hw_clocks when of_clk_add_hw_provider failed. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-23clk: imx: clk-composite-8m: Switch to clk_hw based APIPeng Fan2-9/+24
Switch the imx8m_clk_hw_composite_flags function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-23clk: imx: clk-pll14xx: Switch to clk_hw based APIPeng Fan2-9/+20
Switch the imx_clk_pll14xx function to clk_hw based API, rename accordingly and add a macro for clk based legacy. This allows us to move closer to a clear split between consumer and provider clk APIs. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-20dt-bindings: clock: renesas: cpg-mssr: Fix r8a774b1 typoBiju Das1-1/+1
This patch fixes the typo %s/r8a774a1/r8a774b1/. Fixes: 10003938a0c64 ("dt-bindings: clock: renesas: cpg-mssr: Document r8a774b1 binding") Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1576673984-37752-1-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-12-20clk: renesas: r7s9210: Add SPIBSC clockChris Brandt1-0/+1
Add SPIBSC clock for RZ/A2. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Link: https://lore.kernel.org/r/20191206134202.18784-4-chris.brandt@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-12-20clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocksSergei Shtylyov1-2/+4
I was unable to get clk_set_rate() setting a lower RPC-IF clock frequency and that issue boiled down to me not passing CLK_SET_RATE_PARENT flag to clk_register_composite() when registering the RPC[D2] clocks... Fixes: db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC clocks") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Link: https://lore.kernel.org/r/be27a344-d8bf-9e0c-8950-2d1b48498496@cogentembedded.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-12-19clk: qcom: apcs-msm8916: silently error out on EPROBE_DEFERJorge Ramirez-Ortiz1-1/+2
If devm_clk_get() fails due to probe deferral, we shouldn't print an error message. Just be silent in this case. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Link: https://lkml.kernel.org/r/20191125135910.679310-7-niklas.cassel@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-19clk: qcom: hfpll: use clk_parent_data to specify the parentJorge Ramirez-Ortiz1-1/+3
This permits extending the driver to other platforms without having to modify its source code. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Link: https://lkml.kernel.org/r/20191125135910.679310-6-niklas.cassel@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-19clk: qcom: hfpll: CLK_IGNORE_UNUSEDJorge Ramirez-Ortiz1-0/+7
When COMMON_CLK_DISABLED_UNUSED is set, in an effort to save power and to keep the software model of the clock in line with reality, the framework transverses the clock tree and disables those clocks that were enabled by the firmware but have not been enabled by any device driver. If CPUFREQ is enabled, early during the system boot, it might attempt to change the CPU frequency ("set_rate"). If the HFPLL is selected as a provider, it will then change the rate for this clock. As boot continues, clk_disable_unused_subtree will run. Since it wont find a valid counter (enable_count) for a clock that is actually enabled it will attempt to disable it which will cause the CPU to stop. Notice that in this driver, calls to check whether the clock is enabled are routed via the is_enabled callback which queries the hardware. The following commit, rather than marking the clock critical and forcing the clock to be always enabled, addresses the above scenario making sure the clock is not disabled but it continues to rely on the firmware to enable the clock. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lkml.kernel.org/r/20191125135910.679310-5-niklas.cassel@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-19clk: qcom: hfpll: register as clock providerJorge Ramirez-Ortiz1-1/+9
Make the output of the high frequency pll a clock provider. On the QCS404 this PLL controls cpu frequency scaling. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20191125135910.679310-4-niklas.cassel@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-19clk: qcom: gcc: limit GPLL0_AO_OUT operating frequencyJorge Ramirez-Ortiz3-1/+10
Limit the GPLL0_AO_OUT_MAIN operating frequency as per its hardware specifications. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20191125135910.679310-3-niklas.cassel@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-19dt-bindings: mailbox: qcom: Add clock-name optional propertyJorge Ramirez-Ortiz1-3/+21
When the APCS clock is registered (platform dependent), it retrieves its parent names from hardcoded values in the driver. The following commit allows the DT node to provide such clock names to the platform data based clock driver therefore avoiding having to explicitly embed those names in the clock driver source code. Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lkml.kernel.org/r/20191125135910.679310-2-niklas.cassel@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-19clk: qcom: smd: Add missing bimc clockJeffrey Hugo1-0/+3
It turns out booting the modem is dependent on a bimc vote from Linux on msm8998. To make the modem happy, add the bimc clock to rely on the default vote from rpmcc. Once we have interconnect support, bimc should be controlled properly. Fixes: 6131dc81211c ("clk: qcom: smd: Add support for MSM8998 rpm clocks") Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lkml.kernel.org/r/20191217165409.4919-1-jeffrey.l.hugo@gmail.com Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-19clk: qcom: Avoid SMMU/cx gdsc corner casesJeffrey Hugo1-0/+2
Mark the msm8998 cpu CX gdsc as votable and use the hw control to avoid corner cases with SMMU per hardware documentation. Fixes: 3f7df5baa259 ("clk: qcom: Add MSM8998 GPU Clock Controller (GPUCC) driver") Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lkml.kernel.org/r/20191217171905.5619-1-jeffrey.l.hugo@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-19clk: qcom: Add MSM8998 Multimedia Clock Controller (MMCC) driverJeffrey Hugo3-0/+2923
Add a driver for the multimedia clock controller found on MSM8998 based devices. This should allow most multimedia device drivers to probe and control their clocks. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lkml.kernel.org/r/1576596033-10189-1-git-send-email-jhugo@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-19dt-bindings: clock: Add support for the MSM8998 mmccJeffrey Hugo2-0/+248
Document the multimedia clock controller found on MSM8998. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lkml.kernel.org/r/1576596018-10140-1-git-send-email-jhugo@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-19dt-bindings: clock: Convert qcom,mmcc to DT schemaJeffrey Hugo2-28/+60
Convert the qcom,mmcc-X clock controller binding to DT schema. Add the protected-clocks property to the schema to show that is it explicitly allowed, instead of relying on the generic, pre-schema binding. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lkml.kernel.org/r/1576596003-10093-1-git-send-email-jhugo@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-19dt-bindings: clock: Document external clocks for MSM8998 gccJeffrey Hugo1-14/+59
The global clock controller on MSM8998 can consume a number of external clocks. Document them. For 7180 and 8150, the hardware always exists, so no clocks are truly optional. Therefore, simplify the binding by removing the min/max qualifiers to clocks. Also, fixup an example so that dt_binding_check passes. Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lkml.kernel.org/r/1576595987-10043-1-git-send-email-jhugo@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-19clk: qcom: gcc-sc7180: Fix setting flag for votable GDSCsMatthias Kaehlcke1-2/+4
Commit 17269568f7267 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") sets the VOTABLE flag in .pwrsts, but it needs to be set in .flags, fix this. Fixes: 17269568f7267 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lkml.kernel.org/r/20191204120341.1.I9971817e83ee890d1096c43c5a6ce6ced53d5bd3@changeid Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-19clk: qcom: mmcc8974: move gfx3d_clk_src from the mmcc to rpmBrian Masney2-13/+2
gfx3d_clk_src for msm8974 was introduced into the MMCC by commit d8b212014e69 ("clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)") to ensure that all of the clocks for this platform are documented upstream. This clock actually belongs on the RPM. Since then, commit 685dc94b7d8f ("clk: qcom: smd-rpmcc: Add msm8974 clocks") was introduced, which contains the proper definition for gfx3d_clk_src. Let's drop the definition from the mmcc and register the clock with the rpm instead. This change was tested on a Nexus 5 (hammerhead) phone. Signed-off-by: Brian Masney <masneyb@onstation.org> Link: https://lkml.kernel.org/r/20191115123931.18919-1-masneyb@onstation.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-19clk: qcom: dispcc: Add support for display port clocksTaniya Das2-2/+225
SDM845 dispcc supports RCG and CBCRs for display port, so add support for the same. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/20190731182713.8123-3-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-19clk: qcom: rcg2: Add support for display port clock opsTaniya Das3-0/+79
New display port clock ops supported for display port clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/20190731182713.8123-2-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-18clk: Move clk_core_reparent_orphans() under CONFIG_OFOlof Johansson1-7/+7
A recent addition exposed a helper that is only used for CONFIG_OF. Move it into the CONFIG_OF zone in this file to make the compiler stop warning about an unused function. Fixes: 66d9506440bb ("clk: walk orphan list on clock provider registration") Signed-off-by: Olof Johansson <olof@lixom.net> Link: https://lkml.kernel.org/r/20191217082501.424892072D@mail.kernel.org [sboyd@kernel.org: "Simply" move the function instead] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-16clk: at91: fix possible deadlockAlexandre Belloni6-6/+6
Lockdep warns about a possible circular locking dependency because using syscon_node_to_regmap() will make the created regmap get and enable the first clock it can parse from the device tree. This clock is not needed to access the registers and should not be enabled at that time. Use the recently introduced device_node_to_regmap to solve that as it looks up the regmap in the same list but doesn't care about the clocks. Reported-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lkml.kernel.org/r/20191128102531.817549-1-alexandre.belloni@bootlin.com Tested-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-16Merge branch 'v5.5/fixes' into v5.6/driversJerome Brunet2-0/+10
2019-12-16clk: meson: pll: Fix by 0 division in __pll_params_to_rate()Remi Pommarel1-0/+9
Some meson pll registers can be initialized with 0 as N value, introducing the following division by 0 when computing rate : UBSAN: Undefined behaviour in drivers/clk/meson/clk-pll.c:75:9 division by zero CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.4.0-rc3-608075-g86c9af8630e1-dirty #400 Call trace: dump_backtrace+0x0/0x1c0 show_stack+0x14/0x20 dump_stack+0xc4/0x100 ubsan_epilogue+0x14/0x68 __ubsan_handle_divrem_overflow+0x98/0xb8 __pll_params_to_rate+0xdc/0x140 meson_clk_pll_recalc_rate+0x278/0x3a0 __clk_register+0x7c8/0xbb0 devm_clk_hw_register+0x54/0xc0 meson_eeclkc_probe+0xf4/0x1a0 platform_drv_probe+0x54/0xd8 really_probe+0x16c/0x438 driver_probe_device+0xb0/0xf0 device_driver_attach+0x94/0xa0 __driver_attach+0x70/0x108 bus_for_each_dev+0xd8/0x128 driver_attach+0x30/0x40 bus_add_driver+0x1b0/0x2d8 driver_register+0xbc/0x1d0 __platform_driver_register+0x78/0x88 axg_driver_init+0x18/0x20 do_one_initcall+0xc8/0x24c kernel_init_freeable+0x2b0/0x344 kernel_init+0x10/0x128 ret_from_fork+0x10/0x18 This checks if N is null before doing the division. Fixes: 7a29a869434e ("clk: meson: Add support for Meson clock controller") Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Remi Pommarel <repk@triplefau.lt> [jbrunet@baylibre.com: update the comment in above the fix] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-12-16clk: meson: g12a: fix missing uart2 in regmap tableJerome Brunet1-0/+1
UART2 peripheral is missing from the regmap fixup table of the g12a family clock controller. As it is, any access to this clock would Oops, which is not great. Add the clock to the table to fix the problem. Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") Reported-by: Dmitry Shmidt <dimitrysh@google.com> Tested-by: Dmitry Shmidt <dimitrysh@google.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-12-13clk: renesas: Remove use of ARCH_R8A7796Geert Uytterhoeven1-1/+1
CONFIG_ARCH_R8A7796 was renamed to CONFIG_ARCH_R8A77960 in commit 39e57e14d7eaf818 ("soc: renesas: Add ARCH_R8A77960 for existing R-Car M3-W"), so its users can be removed. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20191211100220.6854-1-geert+renesas@glider.be
2019-12-13Merge tag 'imx-clk-fixes-5.5' of ↵Stephen Boyd3-1/+4
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-fixes Pull i.MX clk fixes from Shawn Guo: - Add missing lock to divider in the composite driver for exclusive register access - Add missing sentinel for ulp_div_table in clk-imx7ulp driver - Fix clk_pll14xx_wait_lock() function which calls into readl_poll_timeout() with incorrect parameter * tag 'imx-clk-fixes-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: clk: imx: pll14xx: fix clk_pll14xx_wait_lock clk: imx: clk-imx7ulp: Add missing sentinel of ulp_div_table clk: imx: clk-composite-8m: add lock to gate/mux
2019-12-13clk: walk orphan list on clock provider registrationJerome Brunet1-22/+40
So far, we walked the orphan list every time a new clock was registered in CCF. This was fine since the clocks were only referenced by name. Now that the clock can be referenced through DT, it is not enough: * Controller A register first a reference clocks from controller B through DT. * Controller B register all its clocks then register the provider. Each time controller B registers a new clock, the orphan list is walked but it can't match since the provider is registered yet. When the provider is finally registered, the orphan list is not walked unless another clock is registered afterward. This can lead to situation where some clocks remain orphaned even if the parent is available. Walking the orphan list on provider registration solves the problem. Reported-by: Jian Hu <jian.hu@amlogic.com> Fixes: fc0c209c147f ("clk: Allow parents to be specified without string names") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lkml.kernel.org/r/20191203080805.104628-1-jbrunet@baylibre.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-12-11clk: meson: meson8b: use of_clk_hw_register to register the clocksMartin Blumenstingl1-1/+1
Switch from clk_hw_register to of_clk_hw_register so we can use clk_parent_data.fw_name. This will be used to get the "xtal", "ddr_pll" and possibly others from the .dtb. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-12-11clk: meson: meson8b: don't register the XTAL clock when provided via OFMartin Blumenstingl1-3/+9
The XTAL clock is an actual crystal on the PCB. Thus the meson8b clock driver should not register the XTAL clock - instead it should be provided via .dts and then passed to the clock controller. Skip the registration of the XTAL clock if a parent clock is provided via OF. Fall back to registering the XTAL clock if this is not the case to keep support for old .dtbs. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-12-11clk: meson: meson8b: change references to the XTAL clock to use [fw_]nameMartin Blumenstingl1-34/+44
The XTAL clock is an actual crystal which is mounted on the PCB. Thus the meson8b clock controller driver should not provide the XTAL clock. The meson8b clock controller driver must not use references to the meson8b_xtal clock anymore before we can provide the XTAL clock via OF. Replace the references to the meson8b_xtal.hw by using clk_parent_data's .fw_name and .name = "xtal" (along with index = -1). This makes the common clock framework use the clock provided via OF and if that's not available it falls back to getting the clock by it's name (which is then the clk_fixed_rate which we register in our driver). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-12-11clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifierMartin Blumenstingl1-13/+8
Switch from clk_set_parent() to clk_hw_set_parent() now that we have a way to configure a mux clock based on clk_hw pointers. This simplifies the meson8b_cpu_clk_notifier_cb logic. No functional changes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-12-11clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controllerMartin Blumenstingl2-1/+150
The Meson8/Meson8b/Meson8m2 SoCs embed a DDR clock controller in the MMCBUS registers. There is no public documentation, but the u-boot GPL sources from the Amlogic BSP show that the DDR clock controller is identical on all three SoCs: #define CFG_DDR_CLK 792 #define CFG_PLL_M (((CFG_DDR_CLK/12)*12)/24) #define CFG_PLL_N 1 #define CFG_PLL_OD 1 // from set_ddr_clock: t_ddr_pll_cntl= (CFG_PLL_OD << 16)|(CFG_PLL_N<<9)|(CFG_PLL_M<<0) writel(timing_reg->t_ddr_pll_cntl|(1<<29),AM_DDR_PLL_CNTL); writel(readl(AM_DDR_PLL_CNTL) & (~(1<<29)),AM_DDR_PLL_CNTL); // from hx_ddr_power_down_enter: shut down DDR PLL writel(readl(AM_DDR_PLL_CNTL)|(1<<30),AM_DDR_PLL_CNTL); do { ... } while((readl(AM_DDR_PLL_CNTL)&(1<<31))==0) This translates to: - AM_DDR_PLL_CNTL[29] is the reset bit - AM_DDR_PLL_CNTL[30] is the enable bit - AM_DDR_PLL_CNTL[31] is the lock bit - AM_DDR_PLL_CNTL[8:0] is the m value (assuming the width is 9 bits based on the start of the n value) - AM_DDR_PLL_CNTL[13:9] is the n value (assuming the width is 5 bits based on the start of the od) - AM_DDR_PLL_CNTL[17:16] is the od (assuming the width is 2 bits based on other PLLs on this SoC) Add a driver for this PLL setup because it's used as one of the inputs of the audio clocks. There may be more clocks inside that clock controller - those can be added in subsequent patches. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-12-11dt-bindings: clock: meson8b: add the clock inputsMartin Blumenstingl1-0/+5
The clock controller on Meson8/Meson8b/Meson8m2 has three (known) inputs: - "xtal": the main 24MHz crystal - "ddr_pll": some of the audio clocks use the output of the DDR PLL as input - "clk_32k": an optional clock signal which can be connected to GPIOAO_6 (which then has to be switched to the CLK_32K_IN function) Add the inputs to the documentation so we can wire up these inputs in a follow-up patch. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-12-11dt-bindings: clock: add the Amlogic Meson8 DDR clock controller bindingMartin Blumenstingl2-0/+54
Amlogic Meson8, Meson8b and Meson8m2 SoCs have a DDR clock controller in the MMCBUS registers. There is no public documentation on this, but the GPL u-boot sources from the Amlogic BSP show that: - it uses the same XTAL input as the main clock controller - it contains a PLL which seems to be implemented just like the other PLLs in this SoC - there is a power-of-two PLL post-divider Add the documentation and header file for this DDR clock controller. Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-12-11clk: imx7up: Rename the clks to hwsAbel Vesa1-91/+91
This is just to keep in line with the other i.MX clock drivers that are clk_hw based. Plus, it makes more sense to be called hws since its type is clk_hw not clk. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-11clk: imx: Rename the imx_clk_divider_gate to imply it's clk_hw basedAbel Vesa3-6/+6
Renaming the imx_clk_divider_gate register function to imx_clk_hw_divider_gate to be more obvious it is clk_hw based. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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