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2021-10-24dt-bindings: arm: qcom-ipq4019: add missing device compatibleDavid Heidelberg1-0/+1
One board version (dk01.1-c1) didn't have set device compatible, so let's list it. Signed-off-by: David Heidelberg <david@ixit.cz> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211009193102.76852-1-david@ixit.cz
2021-10-24ARM: dts: qcom: apq8026-lg-lenok: rename board vendorLuca Weiss2-2/+2
In order to avoid having prefixes for multiple internal divisions of LG use the "lg" prefix instead of "lge". Fixes: ad3f04b7bef6 ("ARM: dts: qcom: Add support for LG G Watch R") Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210928203815.77175-2-luca@z3ntu.xyz
2021-10-24dt-bindings: arm: qcom: rename vendor of apq8026-lenokLuca Weiss1-1/+1
In order to avoid having prefixes for multiple internal divisions of LG use the "lg" prefix instead of "lge". Fixes: 21f3cbf693b0 ("dt-bindings: arm: qcom: Document APQ8026 SoC binding") Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Acked-by: David Heidelberg <david@ixit.cz> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210928203815.77175-1-luca@z3ntu.xyz
2021-10-24ARM: dts: qcom: sdx55: Drop '#clock-cells' from QMP PHY nodeShawn Guo1-1/+0
'#clock-cells' is a required property of QMP PHY child node, not itself. Drop it to fix the dtbs_check warnings below. qcom-sdx55-t55.dt.yaml: phy@ff6000: '#clock-cells' does not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+' qcom-sdx55-mtp.dt.yaml: phy@ff6000: '#clock-cells' does not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+' qcom-sdx55-telit-fn980-tlb.dt.yaml: phy@ff6000: '#clock-cells' does not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+' Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210929034253.24570-11-shawn.guo@linaro.org
2021-10-24arm64: dts: qcom: qrb5165-rb5: Add msm-id and board-idAmit Pundir1-0/+2
Add qcom,msm-id and qcom,board-id for Robotics Board RB5. This will help us boot the device with newer Android boot image header versions, which package dtb separately instead of the default Image.gz-dtb (appended dtb) format. Signed-off-by: Amit Pundir <amit.pundir@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210930185742.117928-2-amit.pundir@linaro.org
2021-10-24arm64: dts: qcom: sdm845-db845c: Add msm-id and board-idAmit Pundir1-0/+2
Add qcom,msm-id and qcom,board-id for Dragonboard 845c. This will help us boot the device with newer Android boot image header versions, which package dtb separately instead of the default Image.gz-dtb (appended dtb) format. Signed-off-by: Amit Pundir <amit.pundir@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210930185742.117928-1-amit.pundir@linaro.org
2021-10-24arm64: dts: qcom: sdm845: Move gpio.h inclusion to SoC DTSIKonrad Dybcio7-6/+1
Almost any board that boots and has a way to interact with it (say for the rare cases of just-pstore or let's-rely-on-bootloader-setup) needs to set some GPIOs, so it makes no sense to include gpio.h separately each time. Hence move it to SoC DTSI. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211002001358.45920-6-konrad.dybcio@somainline.org
2021-10-24arm64: dts: qcom: sdm845: Add size/address-cells to dsi[01]Konrad Dybcio4-9/+6
Add the aforementioned properties in the SoC DTSI so that everybody doesn't have to copy that into their device DTs, effectively reducing code duplication. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211002001358.45920-5-konrad.dybcio@somainline.org
2021-10-24arm64: dts: qcom: sdm845: Don't disable MDP explicitlyKonrad Dybcio7-26/+0
DPU/MDSS is borderline useless without MDP, so disabling both of them makes little sense. With this change, enabling mdss will be enough. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211002001358.45920-4-konrad.dybcio@somainline.org
2021-10-24arm64: dts: qcom: sdm845: Disable Adreno, modem and Venus by defaultKonrad Dybcio7-0/+69
Components that rely on proprietary (not to mention signed!) firmware should not be enabled by default, as lack of the aforementioned firmware could cause various issues, from random errors to straight-up failing to boot. Re-enable these remote processors on boards that didn't previously explicitly disable them. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Tested-By: Steev Klimaszewski <steev@kali.org> [bjorn: Added missing changes to db845c and lenovo-yoga-c630 to the patch] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211002001358.45920-3-konrad.dybcio@somainline.org
2021-10-24arm64: dts: qcom: sdm845: Add XO clock to SDHCIKonrad Dybcio1-2/+3
Add the missing XO clock to the SDHCI controller. Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211002001358.45920-2-konrad.dybcio@somainline.org
2021-10-24ARM: dts: qcom: msm8916-samsung-serranove: Include dts from arm64Stephan Gerhold2-0/+4
After adding all necessary support for MSM8916 SMP/cpuidle without PSCI on ARM32, build the Samsung Galaxy S4 Mini VE device tree from the arm64 tree together with the ARM32 include to allow booting this device on ARM32. The approach to include device tree files from other architectures is inspired from e.g. the Raspberry Pi (bcm2711-rpi-4-b.dts) where this is used to build the device tree for both ARM32 and ARM64. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211004204955.21077-15-stephan@gerhold.net
2021-10-24ARM: dts: qcom: msm8916: Add include for SMP without PSCI on ARM32Stephan Gerhold1-0/+62
Add a special device tree include for MSM8916 on ARM32 that sets up SMP and cpuidle without PSCI. This is meant for devices with signed firmware that does not support PSCI and only allows booting ARM32 kernels. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211004204955.21077-14-stephan@gerhold.net
2021-10-24arm64: dts: qcom: msm8916: Add CPU ACC and SAW/SPMStephan Gerhold1-0/+56
Add the device tree nodes necessary for SMP bring-up and cpuidle without PSCI on ARM32. The hardware is typically controlled by the PSCI implementation in the TrustZone firmware and is therefore marked as status = "reserved" by default (from the device tree specification): "Indicates that the device is operational, but should not be used. Typically this is used for devices that are controlled by another software component, such as platform firmware." Since this is part of the MSM8916 SoC it should be added to msm8916.dtsi but in practice these nodes should only get enabled via an extra include on ARM32. This is necessary for some devices with signed firmware which is missing both ARM64 and PSCI support and can therefore only boot ARM32 kernels. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211004204955.21077-13-stephan@gerhold.net
2021-10-24ARM: qcom: Add ARCH_MSM8916 for MSM8916 on ARM32Stephan Gerhold1-0/+10
Add a CONFIG_ARCH_MSM8916 option to enable building MSM8916 support on ARM32. Note that since ARM64 is the main supported architecture for MSM8916 this is only intended for testing and for devices where signed firmware does not allow booting ARM64 kernels. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211004204955.21077-7-stephan@gerhold.net
2021-10-24arm64: dts: qcom: msm8916-samsung-serranove: Add NFCStephan Gerhold1-0/+50
The LTE version of the S4 Mini VE has a NXP PN547, which is supported by the nxp-nci-i2c driver in mainline. It seems to detect NFC tags using "nfctool" just fine, although more testing is difficult given there seem to be very few useful applications making use of the Linux NFC subsystem. :( Note that for some reason Samsung decided to connect the I2C pins to GPIOs where no hardware I2C bus is available, so we need to fall back to software bit-banging with i2c-gpio. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211004201921.18526-7-stephan@gerhold.net
2021-10-24arm64: dts: qcom: msm8916-samsung-serranove: Add rt5033 batteryStephan Gerhold1-0/+23
Like the Samsung Galaxy A3/A5, the S4 Mini VE uses a Richtek RT5033 PMIC as battery fuel gauge, charger, flash LED and for some regulators. For now, only add the fuel gauge/battery device to the device tree, so we can check the remaining battery percentage. The other RT5033 drivers need some more work first before they can be used properly. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211004201921.18526-6-stephan@gerhold.net
2021-10-24arm64: dts: qcom: msm8916-samsung-serranove: Add IMUStephan Gerhold1-0/+23
Add the STMicroelectronics LSM6DS3 IMU that is used in the S4 Mini VE to the device tree. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211004201921.18526-5-stephan@gerhold.net
2021-10-24arm64: dts: qcom: msm8916-samsung-serranove: Add touch keyStephan Gerhold1-0/+87
Add the CORERIVER TC360 touch key together with the two necessary fixed regulators for it. Note that for some reason Samsung decided to connect this to GPIOs where no hardware I2C bus is available, so we need to fall back to software bit-banging using i2c-gpio. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211004201921.18526-4-stephan@gerhold.net
2021-10-24arm64: dts: qcom: msm8916-samsung-serranove: Add touch screenStephan Gerhold1-0/+50
Like msm8916-samsung-a3u-eur, the S4 Mini VE uses a Zinitix BT541 touch screen. Add it together with the necessary fixed-regulator to the device tree. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211004201921.18526-3-stephan@gerhold.net
2021-10-24arm64: dts: qcom: Add device tree for Samsung Galaxy S4 Mini Value EditionStephan Gerhold2-0/+302
The Samsung Galaxy S4 Mini Value Edition is an updated version of the original S4 Mini based on MSM8916. It is similar to the other Samsung devices based on MSM8916 with only a few minor differences. The device tree contains initial support for the S4 Mini Value Edition with: - UART - eMMC/SD card (needs quirk for some reason) - Buttons - Vibrator - WiFi/Bluetooth (WCNSS) - USB Unfortunately, the S4 Mini VE was released with outdated 32-bit only firmware and never received any update from Samsung. Since the 32-bit TrustZone firmware is signed there seems to be no way currently to actually boot this device tree on arm64 Linux at the moment. :( However, it is possible to use this device tree by compiling an ARM32 kernel instead. The device tree can be easily built on ARM32 with an #include and it works really well there. To avoid confusion for others it is still better to add this device tree on arm64. Otherwise it's easy to forget to update this one when making some changes that affect all MSM8916 devices. Maybe someone finds a way to boot ARM64 Linux on this device at some point. In this case I expect that this device tree can be simply used as-is. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211004201921.18526-2-stephan@gerhold.net
2021-10-24ARM: dts: qcom: mdm9615: fix memory node for Sierra Wireless WP8548David Heidelberg1-1/+1
Specify unit address for the memory node, to match the reg. Signed-off-by: David Heidelberg <david@ixit.cz> [bjorn: Rewrote commit message] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211020234431.298310-1-david@ixit.cz
2021-10-24arm64: dts: qcom: sm7225: Add device tree for Fairphone 4Luca Weiss2-0/+321
Add device tree for the Fairphone 4 smartphone which is based on Snapdragon 750G (sm7225) which is basically sm6350. Currently supported are UART, physical buttons (power & volume), screen (based on simple-framebuffer set up by the bootloader), regulators and USB. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211007212444.328034-12-luca@z3ntu.xyz
2021-10-24arm64: dts: qcom: Add SM7225 device treeLuca Weiss1-0/+16
The Snapdragon 750G (sm7225) is software-wise very similar to Snapdragon 690 (sm6350) with minor differences in clock speeds and as added here, it uses the Kryo 570 instead of Kryo 560. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211007212444.328034-11-luca@z3ntu.xyz
2021-10-24dt-bindings: arm: qcom: Document sm7225 and fairphone,fp4 boardLuca Weiss1-0/+6
Add binding documentation for Fairphone 4 smartphone which is based on Snapdragon 750G (sm7225). Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211007212444.328034-10-luca@z3ntu.xyz
2021-10-24dt-bindings: arm: cpus: Add Kryo 570 CPUsLuca Weiss1-0/+1
Document Kryo 570 CPUs found in Qualcomm Snapdragon 750G (SM7225). Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211007212444.328034-9-luca@z3ntu.xyz
2021-10-24arm64: dts: qcom: sm6350: add debug uartLuca Weiss1-0/+31
Add the necessary nodes for the debug uart on SM6350. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211007212444.328034-8-luca@z3ntu.xyz
2021-10-24arm64: dts: qcom: Add PM6350 PMICLuca Weiss1-0/+54
PM6350 is used in SM6350 and provides similar functionality to other Qualcomm PMICs. Add the pon node with power & volume key and the gpios. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211007212444.328034-7-luca@z3ntu.xyz
2021-10-24arm64: dts: qcom: sa8155p-adp: Enable remoteproc capabilitiesBhupesh Sharma1-0/+10
Enable two of the remoteprocs found on SA8155p platform - 'audio and compute'. Also specify firmware path for them. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210928140929.2549459-3-bhupesh.sharma@linaro.org
2021-10-24arm64: dts: qcom: sm8150: Add fastrpc nodesBhupesh Sharma1-0/+119
Add fastrpc nodes for sDSP, cDSP, and aDSP. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210928140929.2549459-2-bhupesh.sharma@linaro.org
2021-10-24arm64: dts: qcom: sm8350: Add fastrpc nodesOla Jeppsson1-0/+118
Add fastrpc nodes for sDSP, cDSP, and aDSP. Signed-off-by: Ola Jeppsson <ola@snap.com> Acked-by: Heinrich Fink <hfink@snap.com> Acked-by: Olivier Schonken <oschonken@snapchat.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211018085017.1549494-1-ola@snap.com
2021-10-22Merge tag 'aspeed-5.16-devicetree-2' of ↵Arnd Bergmann7-1246/+470
git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc into arm/dt ASPEED device tree updates for 5.16, round 2 - New machines: * Inventec Transformers, an x86 family server with an AST2600 BMC - Updates to the Everest and Rainier sensors, gpios and KCS devices - New UART routing device tree description * tag 'aspeed-5.16-devicetree-2' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc: ARM: dts: aspeed: Add uart routing to device tree ARM: dts: aspeed: rainier: Enable earlycon ARM: dts: aspeed: rainier: Add front panel LEDs ARM: dts: aspeed: rainier: Add 'factory-reset-toggle' as GPIOF6 ARM: dts: aspeed: rainier: Remove PSU gpio-keys ARM: dts: aspeed: rainier: Remove gpio hog for GPIOP7 ARM: dts: aspeed: rainier: Add eeprom on bus 12 ARM: dts: aspeed: p10bmc: Enable KCS channel 2 ARM: dts: aspeed: p10bmc: Use KCS 3 for MCTP binding ARM: dts: aspeed: Adding Inventec Transformers BMC ARM: dts: aspeed: everest: Fix bus 15 muxed eeproms ARM: dts: aspeed: everest: Add IBM Operation Panel I2C device ARM: dts: aspeed: everest: Add I2C switch on bus 8 ARM: dts: aspeed: rainier and everest: Remove PCA gpio specification ARM: dts: aspeed: p10bmc: Fix ADC iio-hwmon battery node name Link: https://lore.kernel.org/r/CACPK8Xd=eAMk-S3akhGgL4i_K190Nz9t=_CrdHQMJ+nbW172mg@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-22dts: socfpga: Add Mercury+ AA1 devicetreePaweł Anikiel2-0/+113
Add support for the Mercury+ AA1 module for Arria 10 SoC FPGA. Signed-off-by: Paweł Anikiel <pan@semihalf.com> Signed-off-by: Joanna Brozek <jbrozek@antmicro.com> Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com> Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com> Signed-off-by: Maciej Mikunda <mmikunda@antmicro.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20211021151736.2096926-2-pan@semihalf.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-22ARM: dts: spear13xx: Drop malformed 'interrupt-map' on PCI nodesRob Herring2-8/+0
The spear13xx PCI 'interrupt-map' property is not parse-able. '#interrupt-cells' is missing and there are 3 #address-cells. Based on the driver, the only supported interrupt is for MSI. Therefore, 'interrupt-map' is not needed. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Shiraz Hashim <shiraz.linux.kernel@gmail.com> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20211022141156.2592221-1-robh@kernel.org' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-10-21ARM: dts: at91: sama7g5-ek: use blocks 0 and 1 of TCB0 as cs and ceClaudiu Beznea1-0/+12
Use blocks 0 and 1 of TCB0 for clocksource and clockevent functionality. PIT64B is already enabled on SAMA7G5 targets for this but TCB0 will be used as a fallback only in case PIT64B will fail to probe. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211020094656.3343242-4-claudiu.beznea@microchip.com
2021-10-21ARM: dts: at91: sama7g5: add tcb nodesClaudiu Beznea1-0/+20
Add TCB nodes. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211020094656.3343242-3-claudiu.beznea@microchip.com
2021-10-21ARM: dts: at91: sama7g5: add rtc nodeEugen Hristev1-0/+7
Add RTC node. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> [claudiu.beznea: add sama7g5 compatible as the IP has 2 extra registers compared with sam9x60] Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211020094656.3343242-2-claudiu.beznea@microchip.com
2021-10-21ARM: dts: aspeed: Add uart routing to device treeChia-Wei Wang3-0/+18
Add LPC uart routing to the device tree for Aspeed SoCs. Signed-off-by: Oskar Senft <osk@google.com> Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Tested-by: Lei YU <yulei.sh@bytedance.com> Link: https://lore.kernel.org/r/20210927023053.6728-6-chiawei_wang@aspeedtech.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: rainier: Enable earlyconJoel Stanley1-1/+1
Rainier was missed when enabling all of the other machines in commit 239566b032f3 ("ARM: dts: aspeed: Set earlycon boot argument"). Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: rainier: Add front panel LEDsJoel Stanley1-0/+42
These were meant to be part of commit 4fb27b3f9176 ("ARM: dts: aspeed: rainier: Add system LEDs") but went missing. Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: rainier: Add 'factory-reset-toggle' as GPIOF6Isaac Kurth1-1/+1
The state of this GPIO determines whether a factory reset has been requested. If a physical switch is used, it can be high or low. During boot, the software checks and records the state of this switch. If it is different than the previous recorded state, then the read-write portions of memory are reformatted. Signed-off-by: Isaac Kurth <isaac.kurth@ibm.com> Reviewed-by: Adriana Kobylak <anoo@us.ibm.com> Link: https://lore.kernel.org/r/20210714214741.1547052-1-blisaac91@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: rainier: Remove PSU gpio-keysB. J. Wyman1-28/+0
Remove the gpio-keys entries for the power supply presence lines from the Rainier device tree. The user space applications are going to change from using libevdev to libgpiod. Signed-off-by: B. J. Wyman <bjwyman@gmail.com> Link: https://lore.kernel.org/r/20210623230401.3050076-1-bjwyman@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: rainier: Remove gpio hog for GPIOP7Eddie James1-7/+0
Only the pass 1 Ingraham board (Rainier system) had a micro-controller wired to GPIOP7 on ball Y23. Pass 2 boards have this ball wired to the heartbeat LED, so remove the hog as this device tree supports pass 2. Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20210915214738.34382-5-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: rainier: Add eeprom on bus 12Eddie James1-0/+5
The devicetree was missing an eeprom. Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20210915214738.34382-4-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: p10bmc: Enable KCS channel 2Andrew Jeffery2-0/+10
Rainier uses KCS channel 2 as the source for the debug-trigger application outlined at [1] and implemented at [2]. [1] https://github.com/openbmc/docs/blob/master/designs/bmc-service-failure-debug-and-recovery.md [2] https://github.com/openbmc/debug-trigger Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20210623033854.587464-8-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: p10bmc: Use KCS 3 for MCTP bindingAndrew Jeffery2-5/+12
The MCTP LPC driver was loaded by hacking up the compatible in the devicetree node for KCS 4. With the introduction of the raw KCS driver this hack is no-longer required. Use the regular compatible string for KCS 4 and configure the appropriate SerIRQ. The reset state of the status bits on KCS 4 is inappropriate for the MCTP LPC binding. Switch to KCS 3 which has a different reset behaviour. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: Adding Inventec Transformers BMCLin.TommySC 林世欽 TAO2-0/+329
Initial introduction of Inventec Transformers x86 family equipped with AST2600 BMC SoC. Signed-off-by: Tommy Lin <Lin.TommySC@inventec.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/7d7b20575f994a3c9018223a3c5f198d@inventec.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: everest: Fix bus 15 muxed eepromsEddie James1-20/+20
The eeproms on bus 15 muxes were at the wrong addresses. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20211020215321.33960-6-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: everest: Add IBM Operation Panel I2C deviceEddie James1-1/+7
Set I2C bus 14 to multi-master mode and add the panel device that will register the I2C controller as a slave device. In addition, in early Everest systems, the panel device was behind an I2C switch, which doesn't work for slave mode. Get it working (albeit unreliably, since a master transaction might switch the switch at any moment) by defaulting the switch channel to the one with the panel. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20211020215321.33960-5-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-10-21ARM: dts: aspeed: everest: Add I2C switch on bus 8Eddie James1-0/+23
The switch controls two busses containing some VRMs. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20211020215321.33960-4-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-27 10:33:51 +0300