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2021-10-18ARM: dts: qcom-msm8660: add gpio-ranges to mpps nodesDmitry Baryshkov1-0/+1
Add gpio-ranges property to mpps device tree nodes, adding the mapping between pinctrl and GPIO pins. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211008012524.481877-5-dmitry.baryshkov@linaro.org
2021-10-18ARM: dts: qcom-apq8064: add gpio-ranges to mpps nodesDmitry Baryshkov1-0/+2
Add gpio-ranges property to mpps device tree nodes, adding the mapping between pinctrl and GPIO pins. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211008012524.481877-4-dmitry.baryshkov@linaro.org
2021-10-18arm64: dts: qcom: pm8994: add interrupt controller propertiesDmitry Baryshkov1-8/+2
Now that the pmic-mpp is a proper hierarchical IRQ chip, add interrupt controller properties ('interrupt-controller' and '#interrupt-cells'). The interrupts property is no longer needed so remove it. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211008012524.481877-26-dmitry.baryshkov@linaro.org
2021-10-18arm64: dts: qcom: pm8916: add interrupt controller propertiesDmitry Baryshkov1-4/+2
Now that the pmic-mpp is a proper hierarchical IRQ chip, add interrupt controller properties ('interrupt-controller' and '#interrupt-cells'). The interrupts property is no longer needed so remove it. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211008012524.481877-25-dmitry.baryshkov@linaro.org
2021-10-18arm64: dts: qcom: apq8016-sbc: fix mpps state namesDmitry Baryshkov1-2/+2
The majority of device tree nodes for mpps use xxxx-state as pinctrl nodes. Change names of mpps pinctrl nodes for the apq8016-sbc board to follow that pattern. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211008012524.481877-13-dmitry.baryshkov@linaro.org
2021-10-18arm64: dts: qcom: pm8994: fix mpps device tree nodeDmitry Baryshkov1-1/+2
Add missing "qcom,spmi-mpp" to the compatible list as required by the node description. Also add gpio-ranges property to mpps device tree node, adding the mapping between pinctrl and GPIO pins. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211008012524.481877-12-dmitry.baryshkov@linaro.org
2021-10-18arm64: dts: qcom: pm8916: fix mpps device tree nodeDmitry Baryshkov1-1/+2
Add missing "qcom,spmi-mpp" to the compatible list as required by the node description. Also add gpio-ranges property to mpps device tree node, adding the mapping between pinctrl and GPIO pins. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211008012524.481877-11-dmitry.baryshkov@linaro.org
2021-10-17arm64: dts: rockchip: Add analog audio on Quartz64Nicolas Frattaroli1-3/+32
On the Quartz64 Model A, the I2S1 TDM controller is connected to the rk817 codec in I2S mode. Enabling it and adding the necessary simple-sound-card and codec nodes allows for analog audio output on the PINE64 Quartz64 Model A SBC. Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Link: https://lore.kernel.org/r/20211016105354.116513-5-frattaroli.nicolas@gmail.com [some property sorting] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-10-17arm64: dts: rockchip: Add i2s1 on rk356xNicolas Frattaroli1-0/+25
This adds the necessary device tree node on rk3566 and rk3568 to enable the I2S1 TDM audio controller. I2S0 has not been added, as it is connected to HDMI and there is no way to test that it's working without a functioning video clock (read: VOP2 driver). Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Link: https://lore.kernel.org/r/20211016105354.116513-4-frattaroli.nicolas@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-10-17arm64: dts: rockchip: change gpio nodenamesJohan Jonker5-22/+22
Currently all gpio nodenames are sort of identical to there label. Nodenames should be of a generic type, so change them all. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20211007144019.7461-3-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-10-17ARM: dts: rockchip: change gpio nodenamesJohan Jonker6-30/+30
Currently all gpio nodenames are sort of identical to there label. Nodenames should be of a generic type, so change them all. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20211007144019.7461-2-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-10-17arm64: dts: qcom: Enable RPM Sleep statsMaulik Shah5-0/+25
Add device node for Sleep stats driver which provides various low power mode stats on msm8996, msm8998, qcs404, sdm630 and sm6125. Cc: devicetree@vger.kernel.org Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1634107104-22197-6-git-send-email-mkshah@codeaurora.org
2021-10-17arm64: dts: qcom: Enable RPMh Sleep statsMaulik Shah5-5/+30
Add device node for Sleep stats driver which provides various low power mode stats on sc7180, sc7280, sm8150, sm8250 and sm8350. Also update the reg size of aoss_qmp device to 0x400. Cc: devicetree@vger.kernel.org Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1634107104-22197-5-git-send-email-mkshah@codeaurora.org
2021-10-17arm64: dts: sc7180: Support Parade ps8640 edp bridgePhilip Chen1-0/+109
Add a dts fragment file to support the sc7180 boards with the second source edp bridge, Parade ps8640. Signed-off-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211008113839.v3.2.I187502fa747bc01a1c624ccf20d985fdffe9c320@changeid
2021-10-17arm64: dts: sc7180: Factor out ti-sn65dsi86 supportPhilip Chen7-86/+95
Factor out ti-sn65dsi86 edp bridge as a separate dts fragment. This helps us introduce the second source edp bridge later. Signed-off-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211008113839.v3.1.Ibada67e75d2982157e64164f1d11715d46cdc42c@changeid
2021-10-17ARM: dts: qcom-apq8064: stop using legacy clock names for HDMIDmitry Baryshkov1-4/+4
Stop using legacy clock names (with _clk suffix) for HDMI and HDMI PHY device tree nodes. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211014214221.4173287-1-dmitry.baryshkov@linaro.org
2021-10-17arm64: dts: qcom: add 'chassis-type' propertyArnaud Ferraris49-0/+51
A new 'chassis-type' root node property has recently been approved for the device-tree specification, in order to provide a simple way for userspace to detect the device form factor and adjust their behavior accordingly. This patch fills in this property for end-user devices (such as laptops, smartphones and tablets) based on Qualcomm ARM64 processors. Signed-off-by: Arnaud Ferraris <arnaud.ferraris@collabora.com> Reviewed-by: Stephan Gerhold <stephan@gerhold.net> # msm8916 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211016102025.23346-4-arnaud.ferraris@collabora.com
2021-10-16arm64: dts: rockchip: add 'chassis-type' propertyArnaud Ferraris4-0/+5
A new 'chassis-type' root node property has recently been approved for the device-tree specification, in order to provide a simple way for userspace to detect the device form factor and adjust their behavior accordingly. This patch fills in this property for end-user devices (such as laptops, smartphones and tablets) based on Rockchip ARM64 processors. Signed-off-by: Arnaud Ferraris <arnaud.ferraris@collabora.com> Link: https://lore.kernel.org/r/20211016102025.23346-5-arnaud.ferraris@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-10-16arm64: dts: rockchip: add powerdomains to rk3368Heiko Stuebner1-0/+178
Add the core io-domain node for rk3368. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20210925090405.2601792-3-heiko@sntech.de
2021-10-16dt-bindings: arm: rockchip: add rk3368 compatible string to pmu.yamlHeiko Stuebner1-0/+2
Add the compatible for the pmu mfd on rk3368. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210925090405.2601792-1-heiko@sntech.de
2021-10-16arm64: dts: rockchip: enable spdif on Quartz64 ANicolas Frattaroli1-0/+22
Add the necessary nodes to enable the spdif output on the RK3566-Quartz-A board. Co-developed-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Link: https://lore.kernel.org/r/20211015111303.1365328-2-frattaroli.nicolas@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-10-16arm64: dts: rockchip: add spdif node to rk356xPeter Geis1-0/+14
This adds the spdif node to the rk356x device tree. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Link: https://lore.kernel.org/r/20211015111303.1365328-1-frattaroli.nicolas@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2021-10-16arm64: dts: imx8mm-kontron: Add support for ultra high speed modes on SD cardFrieder Schrempf2-1/+29
In order to use ultra high speed modes (UHS) on the SD card slot, we add matching pinctrls and fix the voltage switching for LDO5 of the PMIC, by providing the SD_VSEL pin as GPIO to the PMIC driver. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-10-16arm64: dts: visconti: Add DTS for the VisROBO boardYuji Ishikawa3-0/+106
This board consists of two boards: the SoM board (VRC SoM) with the SoC on board, and the board for I/O (VRB). The functions of each board supported by this update are as follows: - VRC SoM - WDT - GPIO - SDCard (SPI-MMC mode) - I2C x1 - VRB board - VRC SoM - UART x2 - Ethernet phy Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp> Link: https://lore.kernel.org/r/20211014092703.15251-4-yuji2.ishikawa@toshiba.co.jp Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
2021-10-16dt-bindings: arm: toshiba: Add the TMPV7708 VisROBO VRB boardYuji Ishikawa1-0/+1
Add an entry for the Toshiba Visconti TMPV7708 VisROBO VRB board (tmpv7708-visrobo-vrb) to the board/SoC bindings. Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp> Link: https://lore.kernel.org/r/20211014092703.15251-3-yuji2.ishikawa@toshiba.co.jp Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
2021-10-16arm64: dts: visconti: Add 150MHz fixed clock to TMPV7708 SoCYuji Ishikawa1-0/+7
This clock source is referred by baudrate generators of SPI and I2C devices. Signed-off-by: Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp> Link: https://lore.kernel.org/r/20211014092703.15251-2-yuji2.ishikawa@toshiba.co.jp Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
2021-10-16arm64: dts: visconti: Add PCIe host controller support for TMPV7708 SoCNobuhiro Iwamatsu2-0/+58
Add PCIe node and fixed clock for PCIe in TMPV7708's dtsi, and tmpv7708-rm-mbrc boards's dts. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> Link: https://lore.kernel.org/r/20210907042500.1525771-1-nobuhiro1.iwamatsu@toshiba.co.jp
2021-10-15ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151Amelie Delaunay1-1/+1
Referring to the note under USBH reset and clocks chapter of RM0436, "In order to access USBH_OHCI registers it is necessary to activate the USB clocks by enabling the PLL controlled by USBPHYC" (ck_usbo_48m). The point is, when USBPHYC PLL is not enabled, OHCI register access freezes the resume from STANDBY. It is the case when dual USBH is enabled, instead of OTG + single USBH. When OTG is probed, as ck_usbo_48m is USBO clock parent, then USBPHYC PLL is enabled and OHCI register access is OK. This patch adds ck_usbo_48m (provided by USBPHYC PLL) as clock of USBH OHCI, thus USBPHYC PLL will be enabled and OHCI register access will be OK. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-10-15ARM: dts: stm32: fix AV96 board SAI2 pin muxing on stm32mp15Olivier Moysan1-4/+4
Fix SAI2A and SAI2B pin muxings for AV96 board on STM32MP15. Change sai2a-4 & sai2a-5 to sai2a-2 & sai2a-2. Change sai2a-4 & sai2a-sleep-5 to sai2b-2 & sai2b-sleep-2 Fixes: dcf185ca8175 ("ARM: dts: stm32: Add alternate pinmux for SAI2 pins on stm32mp15") Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-10-15ARM: dts: stm32: fix SAI sub nodes register rangeOlivier Moysan1-8/+8
The STM32 SAI subblocks registers offsets are in the range 0x0004 (SAIx_CR1) to 0x0020 (SAIx_DR). The corresponding range length is 0x20 instead of 0x1c. Change reg property accordingly. Fixes: 5afd65c3a060 ("ARM: dts: stm32: add sai support on stm32mp157c") Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-10-15ARM: dts: stm32: fix STUSB1600 Type-C irq level on stm32mp15xx-dkxFabrice Gasnier1-1/+1
STUSB1600 IRQ (Alert pin) is active low (open drain). Interrupts may get lost currently, so fix the IRQ type. Fixes: 83686162c0eb ("ARM: dts: stm32: add STUSB1600 Type-C using I2C4 on stm32mp15xx-dkx") Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-10-15ARM: dts: stm32: set the DCMI pins on stm32mp157c-odysseyGrzegorz Szymaszek1-0/+6
The Seeed Odyssey-STM32MP157C board has a 20-pin DVP camera output. The DCMI pins used on this output are defined in the pin state definition &pinctrl/dcmi-1, AKA &dcmi_pins_b (added in mainline commit 02814a41529a55dbfb9fbb2a3728e78e70646ea6). Set these pins as the default pinctrl of the DCMI peripheral in the board device tree. The pins are not used for any other purpose, so it seems safe to assume most users will not need to override (delete) what this patch provides. status defaults to "disabled", so the peripheral will not be unnecessarily started. And the users who actually intend to make use of a camera on the DVP port will have this little part of the configuration ready. Signed-off-by: Grzegorz Szymaszek <gszymaszek@short.pl> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-10-15ARM: dts: stm32: Reduce DHCOR SPI NOR frequency to 50 MHzMarek Vasut1-1/+1
The SPI NOR is a bit further away from the SoC on DHCOR than on DHCOM, which causes additional signal delay. At 108 MHz, this delay triggers a sporadic issue where the first bit of RX data is not received by the QSPI controller. There are two options of addressing this problem, either by using the DLYB block to compensate the extra delay, or by reducing the QSPI bus clock frequency. The former requires calibration and that is overly complex, so opt for the second option. Fixes: 76045bc457104 ("ARM: dts: stm32: Add QSPI NOR on AV96") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2021-10-15ARM: dts: stm32: add initial support of stm32mp135f-dk boardAlexandre Torgue3-0/+121
Add support of stm32mp135f discovery board (part number: STM32MP135F-DK). It embeds a STM32MP135F SOC with 512 MB of DDR3. Several connections are available on this board: 4*USB2.0, 1*USB2.0 typeC DRD, SDcard, 2*RJ45, HDMI, Combo Wifi/BT, ... Only SD card, uart4 (console) and watchdog IPs are enabled in this commit. Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2021-10-15dt-bindings: stm32: document stm32mp135f-dk boardAlexandre Torgue1-0/+4
Add new entry for stm32mp135f-dk board. Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Rob Herring <robh@kernel.org>
2021-10-15ARM: dts: stm32: add STM32MP13 SoCs supportAlexandre Torgue5-0/+366
Add initial support of STM32MP13 family. The STM32MP13 SoC diversity is composed by: -STM32MP131: -core: 1*CA7, 17*TIMERS, 5*LPTIMERS, DMA/MDMA/DMAMUX -storage: 3*SDMCC, 1*QSPI, FMC -com: USB (OHCI/EHCI, OTG), 5*I2C, 5*SPI/I2S, 8*U(S)ART -audio: 2*SAI -network: 1*ETH(GMAC) -STM32MP133: STM32MP131 + 2*CAN, ETH2(GMAC), ADC1 -STM32MP135: STM32MP133 + DCMIPP, LTDC A second diversity layer exists for security features: -STM32MP13xY, "Y" gives information: -Y = A/D means no cryp IP and no secure boot. -Y = C/F means cryp IP + secure boot. This commit adds basic peripheral. Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2021-10-15dt-bindings: interconnect: sunxi: Add R40 MBUS compatibleMaxime Ripard1-0/+1
The R40 MBUS compatible was introduced recently but it was never documented. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20210901091852.479202-26-maxime@cerno.tech
2021-10-15mailmap: Fix text encoding for Niklas SöderlundNiklas Söderlund1-0/+1
There are commits that mess up the encoding of 'ö' in Söderlund, add a correct entry to .mailmap. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20211014212906.2331293-1-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-10-15ARM: dts: ls1021a-tsn: use generic "jedec,spi-nor" compatible for flashLi Yang1-1/+1
We cannot list all the possible chips used in different board revisions, just use the generic "jedec,spi-nor" compatible instead. This also fixes dtbs_check error: ['jedec,spi-nor', 's25fl256s1', 's25fl512s'] is too long Signed-off-by: Li Yang <leoyang.li@nxp.com> Reviewed-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-10-15ARM: dts: ls1021a: move thermal-zones node out of soc/Li Yang1-33/+33
This fixes dtbs-check error from simple-bus schema: soc: thermal-zones: {'type': 'object'} is not allowed for {'cpu-thermal': ..... } From schema: /home/leo/.local/lib/python3.8/site-packages/dtschema/schemas/simple-bus.yaml Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-10-15ARM: dts: ls1021a-tsn: remove undocumented property "position" from mma8452 nodeLi Yang1-1/+0
Property "postion" is not documented in the mma8452 binding. Remove it to resolve the error in "make dtbs_check" Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-10-15ARM: dts: ls1021a-qds: change fpga to simple-mfd deviceLi Yang1-1/+1
The FPGA is not really a bus but more like an MFD device. Change the compatible string from "simple-bus" to "simple-mfd". This also fix a node name issue with simple-bus schema. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-10-15ARM: dts: ls1021a: add #power-domain-cells for power-controller nodeLi Yang1-0/+1
Add the #power-domain-cells for power-controller node as required by the schema. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-10-15ARM: dts: ls1021a: add #dma-cells to qdma nodeLi Yang1-0/+1
Add the #dma-cells to align with the dma schema. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-10-15ARM: dts: ls1021a: fix memory node for schema checkLi Yang1-1/+1
Fix the following error from "make dtbs_check" memory: False schema does not allow ... Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-10-15ARM: dts: ls1021a: remove regulators simple-busLi Yang2-26/+12
There is no regulator bus in hardware. So move the regulator nodes out and remove the regulators simple-bus. This also make the dts align with the simple-bus schema. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-10-15ARM: dts: ls1021a: disable ifc node by defaultLi Yang2-3/+4
Disable the bus in the SoC dtsi file to be enabled only in board dts files. Also breakup long values in the ifc node to fix dtbs_check. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-10-15ARM: dts: ls1021a: breakup long values in thermal nodeLi Yang1-36/+36
Breakup long values to pass the schema check. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-10-15ARM: dts: ls1021a: fix board compatible to follow binding schemaLi Yang2-1/+1
Align the compatible strings with the board binding defined in schema file. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-10-15ARM: dts: ls1021a: update pcie nodes for dt-schema checkLi Yang1-8/+8
Break up long values to pass dt-schema checks. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-30 00:43:15 +0300