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2018-08-15Merge branches 'clk-mvebu-spdx', 'clk-meson', 'clk-imx7d-mu', ↵Stephen Boyd31-262/+3729
'clk-imx-init-array-cleanup' and 'clk-rockchip' into clk-next * clk-mvebu-spdx: clk: mvebu: armada-37xx-periph: switch to SPDX license identifier * clk-meson: clk: meson: add gen_clk clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition clk: meson-axg: add clocks required by pcie driver clk: meson: remove unused clk-audio-divider driver clk: meson: stop rate propagation for audio clocks clk: meson: axg: add the audio clock controller driver clk: meson: add axg audio sclk divider driver clk: meson: add triple phase clock driver clk: meson: add clk-phase clock driver clk: meson: clean-up meson clock configuration clk: meson: remove obsolete register access clk: meson: expose GEN_CLK clkid clk: meson-axg: add pcie and mipi clock bindings dt-bindings: clock: add meson axg audio clock controller bindings clk: meson: audio-divider is one based clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL * clk-imx7d-mu: : - i.MX7D mailbox clk support clk: imx7d: add IMX7D_MU_ROOT_CLK * clk-imx-init-array-cleanup: : - i.MX clk init arrays removed in place of CLK_IS_CRITICAL clk: imx6sx: remove clks_init_on array clk: imx6sl: remove clks_init_on array clk: imx6q: remove clks_init_on array * clk-rockchip: clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399 clk: rockchip: fix clk_i2sout parent selection bits on rk3399 clk: rockchip: add clock controller for px30 clk: rockchip: add support for half divider dt-bindings: add bindings for px30 clock controller clk: rockchip: add dt-binding header for px30
2018-08-15Merge branches 'clk-imx-critical', 'clk-tegra-bpmp', 'clk-tegra-124', ↵Stephen Boyd5-36/+30
'clk-tegra-critical' and 'clk-tegra-emc-oob' into clk-next * clk-imx-critical: : - Convert to CLK_IS_CRITICAL for i.MX51/53 driver clk: imx51-imx53: Include sizes.h to silence compile errors clk: imx51-imx53: Annotate critical clocks as CLK_IS_CRITICAL * clk-tegra-bpmp: : - Fix Tegra BPMP driver oops when some xlating a NULL clk clk: tegra: bpmp: Don't crash when a clock fails to register * clk-tegra-124: : - Proper default configuration for vic03 and vde clks on Tegra124 clk: tegra: Make vde a child of pll_c3 clk: tegra: Make vic03 a child of pll_c3 * clk-tegra-critical: : - Mark Tegra memory controller clks as critical clk: tegra: Mark Memory Controller clock as critical * clk-tegra-emc-oob: : - Fix array bounds clamp in Tegra's emc determine_rate() op clk: tegra: emc: Avoid out-of-bounds bug
2018-08-15Merge branches 'clk-ingenic-fixes', 'clk-max9485', 'clk-pxa-32k-pll', ↵Stephen Boyd14-14/+503
'clk-aspeed' and 'clk-imx6sll-gpio' into clk-next * clk-ingenic-fixes: : - Ingenic i2s bit update and allow UDC clk to gate clk: ingenic: Add missing flag for UDC clock clk: ingenic: Fix incorrect data for the i2s clock * clk-max9485: : - Maxim 9485 Programmable Clock Generator clk: Add driver for MAX9485 dts: clk: add devicetree bindings for MAX9485 * clk-pxa-32k-pll: : - Expose 32 kHz PLL on PXA SoCs clk: pxa: export 32kHz PLL * clk-aspeed: : - Fix name of aspeed SDC clk define to have only one 'CLK' clk: aspeed: Fix SDCLK name * clk-imx6sll-gpio: : - imx6sll GPIO clk gate support clk: imx6sll: add GPIO LPCGs
2018-08-15Merge branches 'clk-imx6-video-parent', 'clk-qcom-sdm845-criticals', ↵Stephen Boyd14-7/+1298
'clk-renesas', 'clk-stratix10-fixes' and 'clk-atmel-i2s' into clk-next * clk-imx6-video-parent: : - Fix i.MX6QDL video clk parent clk: imx6: fix video_27m parent for IMX6QDL_CLK_CKO1_SEL * clk-qcom-sdm845-criticals: : - critical clk markings for qcom SDM845 clk: qcom: Enable clocks which needs to be always on for SDM845 * clk-renesas: clk: renesas: Renesas R9A06G032 clock driver dt-bindings: clock: renesas,r9a06g032-sysctrl: documentation dt-bindings: clock: Add the r9a06g032-sysctrl.h file clk: renesas: r8a7795: Add CCREE clock clk: renesas: r8a7795: Add CR clock * clk-stratix10-fixes: : - Fix Stratix10 mpu_free_clk and sdmmc_free_clk parents clk: socfpga: stratix10: fix the sdmmc_free_clk mux clk: socfpga: stratix10: fix the parents of mpu_free_clk * clk-atmel-i2s: : - Atmel at91 I2S audio clk support clk: at91: add I2S clock mux driver dt-bindings: clk: at91: add an I2S mux clock
2018-08-15Merge branches 'clk-qcom-set-rate-gate', 'clk-core-set-rate-gate', ↵Stephen Boyd8-48/+412
'clk-core-duty-cycle', 'clk-si-prepare' and 'clk-imx-gpio-gates' into clk-next * clk-qcom-set-rate-gate: clk: qcom: drop CLK_SET_RATE_GATE from sdc clocks * clk-core-set-rate-gate: clk: fix CLK_SET_RATE_GATE with clock rate protection * clk-core-duty-cycle: clk: add duty cycle support * clk-si-prepare: : - SI544/SI514 clk on/off support clk-si514, clk-si544: Implement prepare/unprepare/is_prepared operations * clk-imx-gpio-gates: : - i.MX6UL GPIO clock gates in CCM CCGR clk: imx6ul: remove clks_init_on array clk: imx6ul: add GPIO clock gates dt-bindings: clock: imx6ul: Do not change the clock definition order
2018-08-08Merge tag 'v4.19-rockchip-clk2' of ↵Stephen Boyd1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull one final rockchip update from Heiko Stuebner: pclk_rkpwm_pmu as critical clock, due to it supplying the pwm used to drive the logic supply of the rk3399 core. * tag 'v4.19-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399
2018-08-07clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399Levin Du1-0/+1
PWM2 is commonly used to control voltage of PWM regulator of VDD_LOG in RK3399. On the Firefly-RK3399 board, PWM2 outputs 40 KHz square wave from power on and the VDD_LOG is about 0.9V. When the kernel boots normally into the system, the PWM2 keeps outputing PWM signal. But the kernel hangs randomly after "Starting kernel ..." line on that board. When it happens, PWM2 outputs high level which causes VDD_LOG drops to 0.4V below the normal operating voltage. By adding "pclk_rkpwm_pmu" to the rk3399_pmucru_critical_clocks array, PWM clock is ensured to be prepared at startup and the PWM2 output is normal. After repeated tests, the early boot hang is gone. This patch works on both Firefly-RK3399 and ROC-RK3399-PC boards. Signed-off-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-07-11Merge tag 'v4.19-rockchip-clk1' of ↵Stephen Boyd8-2/+1858
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull Rockchip clk driver updates from Heiko Stuebner: Support for Rockchip's PX30 SoC including its new half-divider clock type that is doing freq_out = 2*freq_in / (2*div + 3). As well as a register-bit fix for the rk3399 i2sout clock. * tag 'v4.19-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: fix clk_i2sout parent selection bits on rk3399 clk: rockchip: add clock controller for px30 clk: rockchip: add support for half divider dt-bindings: add bindings for px30 clock controller clk: rockchip: add dt-binding header for px30
2018-07-09clk: imx7d: add IMX7D_MU_ROOT_CLKOleksij Rempel1-0/+1
This clock is needed for iMX mailbox driver Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-09Merge tag 'meson-clk-4.19-1' of https://github.com/BayLibre/clk-meson into ↵Stephen Boyd22-211/+2141
clk-meson Pull first round of updates for meson clocks from Jerome Brunet: - Remove legacy register access (finish moving to syscon) - Clean up configuration flags - Add axg PCIe clocks - Add GEN CLK on gxbb, gxl and axg - Remove clk_audio_divider driver - Add axg audio clock controller * tag 'meson-clk-4.19-1' of https://github.com/BayLibre/clk-meson: clk: meson: add gen_clk clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition clk: meson-axg: add clocks required by pcie driver clk: meson: remove unused clk-audio-divider driver clk: meson: stop rate propagation for audio clocks clk: meson: axg: add the audio clock controller driver clk: meson: add axg audio sclk divider driver clk: meson: add triple phase clock driver clk: meson: add clk-phase clock driver clk: meson: clean-up meson clock configuration clk: meson: remove obsolete register access clk: meson: expose GEN_CLK clkid clk: meson-axg: add pcie and mipi clock bindings dt-bindings: clock: add meson axg audio clock controller bindings clk: meson: audio-divider is one based clk: add duty cycle support clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL
2018-07-09clk: mvebu: armada-37xx-periph: switch to SPDX license identifierGregory CLEMENT1-4/+1
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-09clk: meson: add gen_clkJerome Brunet4-3/+135
GEN_CLK is able to route several internal clocks to one of the SoC pads. In the future, even more clocks could be made accessible using cts_msr_clk - the clock measure block. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definitionJerome Brunet1-1/+0
HHI_GEN_CLK_CTNL is defined twice, just remove the duplicate definition Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver") Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09clk: meson-axg: add clocks required by pcie driverYixun Lan2-1/+150
Adding clocks for the pcie driver. Due to the ASIC design, the pcie controller re-use part of the mipi clock logic, so the mipi clock is also added. Tested-by: Jianxin Qin <jianxin.qin@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> [amended to remove unnecessary locales] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09clk: meson: remove unused clk-audio-divider driverJerome Brunet3-119/+1
clk-audio-divider is no longer used, we can remove it. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09clk: meson: stop rate propagation for audio clocksJerome Brunet1-9/+7
It is actually a lot easier to setup the PLL with carefully chosen rates than relying on CCF clock propagation for this audio use case. This way, we can make sure we will always be able to provide the common audio clock rates, while having the PLL in the optimal operating range. For this, we stop the rate propagation at the mux picking the PLL and let it round to the closest matching PLL. Doing so, we can use the generic divider for the i2s clock. clk-audio-divider is no longer required. It was a (poor) attempt to use CCF rate propagation while making sure the PLL rate would be high enough to work with audio use cases. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09clk: meson: axg: add the audio clock controller driverJerome Brunet4-0/+982
The axg audio clock controller is the clock generation unit for the amlogic audio subsystem of A113 based SoCs. It may be clocked by 8 different plls provided by the primary clock controller and also by 10 slave bit clocks and 10 slave sample clocks which may be provided by external components, such as audio codecs, through the SoC pads. It contains several muxes, dividers and gates which are fed into the the different devices of the audio subsystem. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09clk: meson: add axg audio sclk divider driverJerome Brunet3-1/+252
Add a driver to control the clock divider found in the sample clock generator of the axg audio clock controller. The sclk divider accumulates specific features which make the generic divider unsuitable to control it: - zero based divider (div = val + 1), but zero value gates the clock, so minimum divider value is 2. - lrclk variant may adjust the duty cycle depending the divider value and the 'hi' value. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09Merge remote-tracking branch 'clk/clk-core-duty-cycle' into next/driversJerome Brunet4-5/+289
2018-07-09clk: meson: add triple phase clock driverJerome Brunet4-0/+94
Add a driver to control the output of the sample clock generator found in the axg audio clock controller. The goal of this driver is to coherently control the phase provided to the different element using the sample clock generator. This simplify the usage of the sample clock generator a lot, without comprising the ability of the SoC. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09clk: meson: add clk-phase clock driverJerome Brunet3-0/+72
Add a driver based meson clk-regmap to control clock phase on amlogic SoCs Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09Merge branch 'next/dt' into next/driversJerome Brunet4-0/+155
2018-07-09clk: meson: clean-up meson clock configurationJerome Brunet1-9/+5
Clean the dependencies in meson clock Kconfig. CLK_AMLOGIC should actually select CLK_REGMAP_MESON which it uses. Also, each platform should select CLK_AMLOGIC, so everything is properly turned on when the platform Kconfig enable each configuration flag Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09clk: meson: remove obsolete register accessJerome Brunet2-69/+4
The legacy method to access the hhi register space is not longer used. We can safely drop it now. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09clk: meson: expose GEN_CLK clkidJerome Brunet2-0/+2
Expose GEN_CLK clock id Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09clk: tegra: emc: Avoid out-of-bounds bugDmitry Osipenko1-1/+1
Apparently there was an attempt to avoid out-of-bounds accesses when there is only one memory timing available, but there is a typo in the code that neglects that attempt. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-09clk: tegra: Mark Memory Controller clock as criticalDmitry Osipenko1-2/+3
Memory Controller should be always-on. Currently the sibling EMC clock is marked as critical, let's mark MC clock too for consistency. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-09clk: tegra: Make vde a child of pll_c3Thierry Reding1-1/+1
The current default is to leave the VDE clock's parent at the default, which is clk_m. However, that is not a configuration that will allow the VDE to function. Reparent it to pll_c3 instead to make sure the hardware can actually decode video content. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-09clk: tegra: Make vic03 a child of pll_c3Thierry Reding1-0/+1
By default, the vic03 clock is a child of pll_m but that runs at 924 MHz which is too fast for VIC. Make vic03 a child of pll_c3 by default so it will run at a supported frequency. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-09clk: tegra: bpmp: Don't crash when a clock fails to registerMikko Perttunen1-3/+9
When registering clocks, we just skip any that fail to register (leaving a NULL hole in the clock table). However, our of_xlate function still tries to dereference each entry while looking for the clock with the requested id, causing a crash if any clocks failed to register. Add a check to of_xlate to skip any NULL clocks. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-08clk: rockchip: fix clk_i2sout parent selection bits on rk3399Alberto Panizzo1-1/+1
Register, shift and mask were wrong according to datasheet. Fixes: 115510053e5e ("clk: rockchip: add clock controller for the RK3399") Cc: stable@vger.kernel.org Signed-off-by: Alberto Panizzo <alberto@amarulasolutions.com> Signed-off-by: Anthony Brandon <anthony@amarulasolutions.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-07-07clk: imx51-imx53: Include sizes.h to silence compile errorsStephen Boyd1-0/+1
This driver uses sizes.h, but relies on it being implicitly included somewhere else breaking random direct compilation of the file. Include sizes.h so we can build it those configurations too for better compile coverage. Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-07clk: imx51-imx53: Annotate critical clocks as CLK_IS_CRITICALFabio Estevam1-29/+14
Instead of explicitly enabling critical clocks via clk_prepare_enable(), let's use the standard CLK_IS_CRITICAL flag instead, which makes the code a bit shorter. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06clk: imx6sll: add GPIO LPCGsAnson Huang2-1/+14
According to Reference Manual Rev.0, 06/2017, there are GPIO LPCGs defined in CCM CCGRs, add them into clock tree. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06clk: aspeed: Fix SDCLK nameLei YU2-2/+2
The SDCLK was named SDCLKCLK, and no one has used this yet. Fix it. Signed-off-by: Lei YU <mine260309@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06clk: pxa: export 32kHz PLLRobert Jarzmik4-9/+14
This clock is especially used by the RTC driver, so export it so that devicetree users can use it. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06clk: Add driver for MAX9485Daniel Mack3-0/+394
This patch adds a driver for MAX9485, a programmable audio clock generator. The device requires a 27.000 MHz clock input. It can provide a gated buffered output of its input clock and two gated outputs of a PLL that can generate one out of 16 discrete frequencies. There is only one PLL however, so the two gated outputs will always have the same frequency but they can be switched individually. The driver for this device exposes 4 clocks in total: - MAX9485_MCLKOUT: A gated, buffered output of the input clock - MAX9485_CLKOUT: A PLL that can be configured to 16 different discrete frequencies - MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT Some PLL output frequencies can be achieved with different register settings. The driver will select the one with lowest jitter in such cases. Signed-off-by: Daniel Mack <daniel@zonque.org> [sboyd@kernel.org: Use local variable for val in max9485_clkout_recalc_rate() and shorten line of max9485_of_clk_get()] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06clk: ingenic: Add missing flag for UDC clockPaul Cercueil1-1/+1
The UDC clock of the JZ4740 SoC can be gated, but the data structure representing it was missing the CGU_CLK_GATE flag to make it work. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06clk: ingenic: Fix incorrect data for the i2s clockPaul Cercueil1-1/+1
The register field for configuring the divider for the i2s clock occupies the bits [8-0], which means 9 bits and not 8. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06dts: clk: add devicetree bindings for MAX9485Daniel Mack2-0/+77
This patch adds the devicetree bindings for MAX9485, a programmable audio clock generator. Signed-off-by: Daniel Mack <daniel@zonque.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06clk: at91: add I2S clock mux driverCodrin Ciubotariu3-0/+121
This driver is a simple muxing driver that controls the I2S's clock input by using syscon/regmap to change the parent. The available inputs can be peripheral clock and generated clock. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> [sboyd@kernel.org: Fix SPDX tag comment style] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06dt-bindings: clk: at91: add an I2S mux clockCodrin Ciubotariu1-0/+35
The I2S mux clock can be used to select the I2S input clock. The available parents are the peripheral and the generated clocks. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06clk: socfpga: stratix10: fix the sdmmc_free_clk muxDinh Nguyen1-1/+1
The first parent of the sdmmc_free_clk should be the main_sdmmc_clk. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06clk: socfpga: stratix10: fix the parents of mpu_free_clkDinh Nguyen1-1/+6
Add a clock mux that is used as a parent for the mpu_free_clk. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-07-06Merge tag 'clk-renesas-for-v4.19-tag1' of ↵Stephen Boyd6-0/+1093
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates for v4.19 from Geert Uytterhoeven: - Add support for Crypto Engine clocks on R-Car H3 - Add support for the new RZ/N1D SoC * tag 'clk-renesas-for-v4.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: Renesas R9A06G032 clock driver dt-bindings: clock: renesas,r9a06g032-sysctrl: documentation dt-bindings: clock: Add the r9a06g032-sysctrl.h file clk: renesas: r8a7795: Add CCREE clock clk: renesas: r8a7795: Add CR clock
2018-07-06clk: rockchip: add clock controller for px30Elaine Zhang3-1/+1080
Add the clock tree definition for the new px30 SoC. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-07-06clk: rockchip: add support for half dividerElaine Zhang4-0/+323
The new Rockchip socs have optional half divider: The formula is shown as: freq_out = 2*freq_in / (2*div + 3) Is this the same for all of new SoCs. So we use "branch_half_divider" + "COMPOSITE_NOMUX_HALFDIV \ DIV_HALF \ COMPOSITE_HALFDIV \ CMPOSITE_NOGATE_HALFDIV" to hook that special divider clock-type into our clock-tree. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-07-03Merge branch 'v4.19-shared/clkids' into v4.19-clk/nextHeiko Stuebner1-0/+389
2018-07-03dt-bindings: add bindings for px30 clock controllerElaine Zhang1-0/+65
Add devicetree bindings for Rockchip cru which found on Rockchip SoCs. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2018-07-03clk: rockchip: add dt-binding header for px30Elaine Zhang1-0/+389
Add the dt-bindings header for the px30, that gets shared between the clock controller and the clock references in the dts. Add softreset ID for px30. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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