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2015-11-03drm/nouveau/pci/g84: split implementation from nv50Ben Skeggs6-5/+49
An upcoming patch will implement functionality that we don't use on the original NV50. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/ibus/gf100: increase wait timeout to avoid read faultsSamuel Pitoiset6-4/+77
Increase clock timeout of some unknown engines in order to avoid failure at high gpcclk rate. This fixes IBUS read faults on my GF119 when reclocking is manually enabled. Note that memory reclocking is completely broken and NvMemExec has to be disabled to allow core clock reclocking only. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/gm204/6: add voltage control using the new gk104 volt classMartin Peres1-0/+2
I got confirmation that we can read and change the voltage with the same code. The divider is also computed correctly on the gm204 we got our hands on. Thanks to Yoshimo on IRC for executing the tests on his gm204! Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/gm107: add voltage control using the new gk104 volt classMartin Peres1-0/+1
Let's ignore the other desktop Maxwells until I get my hands on one and confirm that we still can change the voltage. Signed-off-by: Martin Peres <martin.peres@free.fr>
2015-11-03drm/nouveau/volt/gk104: add support for pwm and gpio modesMartin Peres6-7/+133
Most Keplers actually use the GPIO-based voltage management instead of the new PWM-based one. Use the GPIO mode as a fallback as it already gracefully handles the case where no GPIOs exist. All the Maxwells seem to use the PWM method though. v2: - Do not forget to commit the PWM configuration change! Signed-off-by: Martin Peres <martin.peres@free.fr>
2015-11-03drm/nouveau/volt: add support for non-vid-based voltage controllersMartin Peres2-1/+12
This patch is not ideal but it definitely beats a rewrite of the current interface and is very self-contained. Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/bios/volt: add support for pwm-based volt managementMartin Peres2-3/+29
Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/ttm: set the DMA mask for platform devicesAlexandre Courbot1-6/+19
So far the DMA mask was not set for platform devices, which limited them to a 32-bit physical space. Allow dma_set_mask() to be called for non-PCI devices, and also take the IOMMU bit into account since it could restrict the physically addressable space. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/ttm: convert to DMA APIAlexandre Courbot1-7/+5
The pci_dma_* functions are now superseeded in the kernel by the DMA API. Make the conversion to this more generic API. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/instmem/gk20a: make use of the IOMMU bitAlexandre Courbot1-4/+6
Use the IOMMU bit specified in platform data instead of hardcoding it to the bit used by current Tegra GPUs. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/platform: allow to specify the IOMMU bitAlexandre Courbot6-10/+46
Current Tegra code taking advantage of the IOMMU assumes a hardcoded value for the IOMMU bit. Make it a platform property instead for flexibility. v2 (Ben Skeggs): remove nvkm dependence on drm structures Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/instmem/gk20a: use direct CPU accessAlexandre Courbot1-97/+264
The Great Nouveau Refactoring Take II brought us a lot of goodness, including acquire/release methods that are called before and after an instobj is modified. These functions can be used as synchronization points to manage CPU/GPU coherency if we modify an instobj using the CPU. This patch replaces the legacy and slow PRAMIN access for gk20a instmem with CPU mappings and writes. A LRU list is used to unmap unused mappings after a certain threshold (currently 1MB) of mapped instobjs is reached. This allows mappings to be reused most of the time. Accessing instobjs using the CPU requires to maintain the GPU L2 cache, which we do in the acquire/release functions. This triggers a lot of L2 flushes/invalidates, but most of them are performed on an empty cache (and thus return immediately), and overall context setup performance greatly benefits from this (from 250ms to 160ms on Jetson TK1 for a simple libdrm program). Making L2 management more explicit should allow us to grab some more performance in the future. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau: remove unnecessary usage of object handlesBen Skeggs10-61/+31
No longer required in a lot of cases, as objects are identified over NVIF via an alternate mechanism since the rework. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/ltc/gf100: add flush/invalidate functionsAlexandre Courbot5-0/+39
Allow clients to manually flush and invalidate L2. This will be useful for Tegra systems for which we want to write instmem using the CPU. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/ltc: add hooks for invalidate and flushAlexandre Courbot3-0/+20
These are useful for systems without a coherent CPU/GPU bus. For such systems we may need to maintain the L2 ourselves. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/timer: re-introduce nvkm_wait_xsec macrosAlexandre Courbot1-0/+10
Reintroduce macros allowing us to test a register against a certain mask, since this is the most common usage pattern for the more generic nvkm_xsec macros and makes the code more concise and readable. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/pmu: do not assume a PMU is presentAlexandre Courbot1-1/+1
Some devices may not have a PMU. Avoid a NULL pointer dereference in such cases by checking whether the pointer given to nvkm_pmu_pgob() is valid. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/nouveau/gem: return only valid domain when there's only oneIlia Mirkin1-2/+3
On nv50+, we restrict the valid domains to just the one where the buffer was originally created. However after the buffer is evicted to system memory, we might move it back to a different domain that was not originally valid. When sharing the buffer and retrieving its GEM_INFO data, we still want the domain that will be valid for this buffer in a pushbuf, not the one where it currently happens to be. This resolves fdo#92504 and several others. These are due to suspend evicting all buffers, making it more likely that they temporarily end up in the wrong place. Cc: stable@vger.kernel.org Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92504 Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-03drm/exynos/gem: remove DMA-mapping hacks used for constructing page arrayMarek Szyprowski1-25/+33
Exynos GEM objects contains an array of pointers to the pages, which the allocated buffer consists of. Till now the code used some hacks (like relying on DMA-mapping internal structures or using ARM-specific dma_to_pfn helper) to build this array. This patch fixes this by adding proper call to dma_get_sgtable_attrs() and using the acquired scatter-list to construct needed array. This approach is more portable (work also for ARM64) and finally fixes the layering violation that was present in this code. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03ARM: exynos_defconfig: enable Exynos DRM Mixer driverAndrzej Hajda1-0/+1
Mixer driver is selected by CONFIG_DRM_EXYNOS_HDMI option. Since Exynos5433 HDMI does not require Mixer. There will be separate options to select Mixer and HDMI. Adding new option to defconfig before Kconfig will allow to keep bisectability. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03drm/exynos: simplify Kconfig component namesAndrzej Hajda1-15/+15
Many Exynos DRM sub-options mentions Exynos DRM in their titles. It is redundant and can be safely shortened. The patch additionally makes some entries more descriptive. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03drm/exynos: re-arrange Kconfig entriesAndrzej Hajda1-16/+22
Exynos DRM driver have quite big number of components and options. The patch re-arranges them into three logical groups: - CRTCs, - Encoders and Bridges, - Sub-drivers. It should make driver options more clear. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03drm/exynos: abstract out common dependencyAndrzej Hajda1-13/+14
All options depends on DRM_EXYNOS so it can be moved to enclosing if clause. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03drm/exynos: separate Mixer and HDMI driversAndrzej Hajda3-3/+12
Latest Exynos SoCs does not have Mixer IP, but they still have HDMI IP. Their drivers should be configurable separately. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03drm/exynos/mixer: replace direct cross-driver call with drm mode validationAndrzej Hajda3-27/+4
HDMI driver called directly function from MIXER driver to invalidate modes not supported by MIXER. The patch replaces the hack with proper .atomic_check callback. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03drm/exynos: add atomic_check callback to exynos_crtcAndrzej Hajda2-0/+15
Some CRTCs needs mode validation, this patch adds neccessary callback to Exynos DRM framework. It is called from DRM core via atomic_check helper for drm_crtc. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03drm/exynos/decon5433: add support for DECON-TVAndrzej Hajda2-61/+122
DECON-TV IP is responsible for generating video stream which is transferred to HDMI IP. It is almost fully compatible with DECON IP. The patch is based on initial work of Hyungwon Hwang. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03drm/exynos/decon5433: remove duplicated initializationAndrzej Hajda1-1/+0
Field .commit is already initialized few lines above. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03drm/exynos/decon5433: merge different flag fieldsAndrzej Hajda1-31/+30
Driver uses four different fields for internal flags. They can be merged into one. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03drm/exynos/decon5433: add function to set particular register bitsAndrzej Hajda1-50/+19
The driver often sets only particular bits of configuration registers. Using separate function to such action simplifies the code. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03drm/exynos/decon5433: fix timing registers writesAndrzej Hajda1-9/+9
All timing registers should contain values decreased by one. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03drm/exynos/decon5433: add PCLK clockAndrzej Hajda1-10/+11
PCLK clock is used by DECON IP. The patch also replaces magic number with number of clocks in array definition. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
2015-11-03Merge branch 'vmwgfx-next' of git://people.freedesktop.org/~thomash/linux ↵Dave Airlie8-101/+140
into drm-next Changes for vmwgfx for 4.4. If there is time, I'll follow up with a series to move to threaded irqs. * 'vmwgfx-next' of git://people.freedesktop.org/~thomash/linux: drm/vmwgfx: Replace iowrite/ioread with volatile memory accesses drm/vmwgfx: Turn off support for multisample count != 0 v2 drm/vmwgfx: switch from ioremap_cache to memremap
2015-11-02drm/amdgpu: Make amdgpu_mn functions inlineHarry Wentland1-2/+2
Unused amdgpu_mn functions threw warnings for every file that includes amdgpu.h. It makes sense to inline this amdgpu_mn stubs to avoid the warning. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org
2015-11-02drm/vmwgfx: Replace iowrite/ioread with volatile memory accessesThomas Hellstrom7-105/+118
Now that we use memremap instead of ioremap, Use WRITE_ONCE / READ_ONCE instead of iowrite / ioread. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Sinclair Yeh <syeh@vmware.com>
2015-11-02drm/vmwgfx: Turn off support for multisample count != 0 v2Thomas Hellstrom2-2/+22
Do this until we know how much MOB memory to allocate for these surfaces. v2: Mask also non-DX multisample. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com>
2015-11-02drm/vmwgfx: switch from ioremap_cache to memremapDan Williams1-4/+10
Per commit 2e586a7e017a "drm/vmwgfx: Map the fifo as cached" the driver expects the fifo registers to be cacheable. In preparation for deprecating ioremap_cache() convert its usage in vmwgfx to memremap(). Cc: David Airlie <airlied@linux.ie> Cc: Thomas Hellstrom <thellstrom@vmware.com> Cc: Sinclair Yeh <syeh@vmware.com> Cc: dri-devel@lists.freedesktop.org Signed-off-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
2015-10-30drm/tegra: dc: Request/free syncpoint at init/exitThierry Reding1-7/+7
syncpoints are resources provided by host1x and their lifetime is tied to the host1x device. They are not properly reference counted either, so removing the host1x device before any of its clients causes a use-after- free error. Adding proper reference counting would be a major enterprise so work around it for now by requesting and freeing the syncpoint at init and exit time, respectively. The host1x device is guaranteed to be around at this point. Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-10-30drm/bridge: ptn3460: Fix coccinelle warningskbuild test robot1-1/+0
The platform_no_drv_owner.cocci coccinelle script generates the following warning: drivers/gpu/drm/bridge/nxp-ptn3460.c:403:3-8: No need to set .owner here. The core will do it. Remove .owner field if calls are used which set it automatically. Patch generated by scripts/coccinelle/api/platform_no_drv_owner.cocci. Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-10-30drm/bridge: ps8622: Fix coccinelle warningskbuild test robot1-1/+0
The platform_no_drv_owner.cocci coccinelle script generates the following warning: drivers/gpu/drm/bridge/parade-ps8622.c:671:3-8: No need to set .owner here. The core will do it. Remove .owner field if calls are used which set it automatically. Patch generated by scripts/coccinelle/api/platform_no_drv_owner.cocci. Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-10-30drm/imx: hdmi: fix HDMI setup to allow modes larger than FullHDLucas Stach1-4/+12
This worked before the dw-hdmi bridge code was changed to validate the setup data more strictly. Add back support for modes with a pixel clock up to 216MHz. Even higher clocks should work, but we are missing the required setup data for now. Also change the mode validate callbacks to disallow modes with higher pixelclocks, so we don't end up failing the modeset later on. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-10-30gpu: ipu-v3: fix div_ratio typeAndrzej Hajda1-1/+1
The variable can be negative. The problem has been detected using proposed semantic patch scripts/coccinelle/tests/unsigned_lesser_than_zero.cocci [1]. [1]: http://permalink.gmane.org/gmane.linux.kernel/2038576 Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-10-30gpu: ipu-v3: csi: add support for 8 bpp grayscale sensors.Philippe De Muyter1-0/+1
Enable the MEDIA_BUS_FMT_Y8_1X8 format. Signed-off-by: Philippe De Muyter <phdm@macqel.be> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-10-30drm/imx: enable ARGB4444 16-bit color formatLucas Stach1-0/+2
This patch allows to use the ARGB4444 color format on planes. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-10-30gpu: ipu-v3: add support for ARGB4444 16-bit color formatLucas Stach2-0/+12
This patch adds support for the ARGB4444 color format. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-10-30drm/imx: ipuv3-plane: enable support for RGBX8888 and RGBA8888 pixel formatsPhilipp Zabel1-0/+6
This patch allows to use the RGBX and RGBA 8:8:8:8 formats. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-10-30gpu: ipu-v3: add support for RGBX8888 and RGBA8888 pixel formatsPhilipp Zabel1-4/+28
This patch adds support for the RGBA8888, RGBX8888, BGRA8888, and BGRX8888 in-memory formats. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-10-30drm/imx: enable 15-bit RGB with 1-bit alpha formatsPhilipp Zabel1-0/+8
This patch enables the ARGB1555, ABGR1555, RGBA5551, and BGRA5551 formats to be used on planes. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-10-30gpu: ipu-v3: add support for 15-bit RGB with 1-bit alpha formatsPhilipp Zabel2-0/+48
This patch adds support for ARGB1555, ABGR1555, RGBA5551, and BGRA5551 in-memory formats. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2015-10-30MAINTAINERS: Add IPUv3 core driver to the i.MX DRM driver sectionPhilipp Zabel1-0/+1
The ipu-v3 core driver is maintained in and merged through the same trees as the imx-drm drivers that are using it. This patch adds the drivers/gpu/ipu-v3/ directory to the i.MX DRM driver section. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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