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2022-05-05clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macroPhil Edworthy3-22/+19
We only ever use ARRAY_SIZE() to populate the number of parents, so move this into the macro to always detect it automatically. This also makes the tables of clocks a little simpler. Similarly for the DEF_SD_MUX macro. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Link: https://lore.kernel.org/r/20220503115557.53370-6-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoCPhil Edworthy1-5/+8
Document the device tree binding for the Renesas RZ/V2M (r9a09g011) SoC. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20220503115557.53370-4-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05Merge tag 'renesas-r9a09g011-dt-binding-defs-tag' into renesas-clk-for-v5.19Geert Uytterhoeven1-0/+352
Renesas RZ/V2M DT Binding Definitions Clock definitions for the Renesas RZ/V2M (R9A09G011) SoC, shared by driver and DT source files.
2022-05-05clk: renesas: r9a07g044: Fix OSTM1 module clock nameGeert Uytterhoeven1-1/+1
Fix a typo in the name of the "ostm1_pclk" clock. This change has no run-time impact. Fixes: 161450134ae9bab3 ("clk: renesas: r9a07g044: Add OSTM clock and reset entries") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/e0eff1f57378ec29d0d3f1a7bdd7e380583f736b.1651494871.git.geert+renesas@glider.be
2022-05-05clk: renesas: r9a07g043: Add clock and reset entries for ADCBiju Das1-0/+6
Add clock and reset entries for ADC block in CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220501083450.26541-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: r9a07g043: Add TSU clock and reset entryBiju Das1-0/+6
Add TSU clock and reset entry to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220501083450.26541-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: r9a07g043: Add RSPI clock and reset entriesBiju Das1-0/+9
Add RSPI{0,1,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220501083450.26541-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus ↵Biju Das1-0/+18
Controller Add clock and reset entries for SPI Multi I/O Bus Controller. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220501083450.26541-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: r9a07g044: Add DSI clock and reset entriesBiju Das1-1/+16
Add DSI clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-10-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: r9a07g044: Add LCDC clock and reset entriesBiju Das1-1/+8
Add LCDC clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-9-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: r9a07g044: Add M4 Clock supportBiju Das1-1/+18
Add support for M4 clock which is sourced from pll2_533_div2. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-8-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: r9a07g044: Add M3 Clock supportBiju Das1-1/+4
Add support for M3 clock which is sourced from DSI divider connected to PLL5_4 mux. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks supportBiju Das1-1/+4
Add support for {M2, M2_DIV2} clocks which is sourced from pll3_533. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: r9a07g044: Add M1 clock supportBiju Das1-1/+10
Add support for M1 clock which is sourced from FOUTPOSTDIV. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: rzg2l: Add DSI divider clk supportBiju Das2-0/+136
M3 clock is sourced from DSI Divider (DSIDIVA * DSIDIVB) This patch add support for DSI divider clk by combining DSIDIVA and DSIDIVB. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: rzg2l: Add PLL5_4 clk mux supportBiju Das2-0/+103
Add PLL5_4 clk mux support to select clock from clock sources FOUTPOSTDIV and FOUT1PH0. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05clk: renesas: rzg2l: Add FOUTPOSTDIV clk supportBiju Das2-0/+235
PLL5 generates FOUTPOSTDIV clk and is sourced by LCDC/DSI modules. The FOUTPOSTDIV is connected to PLL5_4 MUX. Video clock is sourced from DSI divider which is connected to PLL5_4 MUX. This patch adds support for generating FOUTPOSTDIV clk. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220430114156.6260-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-05dt-bindings: clock: Add r9a09g011 CPG Clock DefinitionsPhil Edworthy1-0/+352
Define RZ/V2M (R9A09G011) Clock Pulse Generator module clock outputs (CPG_CLK_ON* registers), and reset definitions (CPG_RST_* registers) in Section 48.5 ("Register Description") of the RZ/V2M Hardware User's Manual (Rev. 1.10, Sep. 2021). Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220503115557.53370-3-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-29clk: renesas: cpg-mssr: Add support for R-Car V4HYoshihiro Shimoda5-0/+231
Initial CPG support for R-Car V4H (r8a779g0). Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20220428135058.597586-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-29Merge tag 'renesas-r8a779g0-dt-binding-defs-tag' into renesas-clk-for-v5.19Geert Uytterhoeven2-0/+135
Renesas R-Car V4H DT Binding Definitions Clock and Power Domain definitions for the Renesas R-Car V4H (R8A779G0) SoC, shared by driver and DT source files.
2022-04-29clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4Yoshihiro Shimoda4-16/+24
R-Car V4H (r8a779g0) has PLL4 so that add CLK_TYPE_GEN4_PLL4. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20220425064201.459633-5-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28clk: renesas: r9a07g043: Add WDT clock and reset entriesBiju Das1-0/+10
Add WDT{0,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220425095244.156720-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28clk: renesas: r9a07g043: Add OSTM clock and reset entriesBiju Das1-0/+9
Add OSTM{0,1,2} clock and reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220425095244.156720-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28clk: renesas: r9a07g043: Add clock and reset entries for CANFDBiju Das1-0/+5
Add clock and reset entries for CANFD in CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220425095244.156720-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28clk: renesas: r9a07g043: Add USB clocks/resetsBiju Das1-0/+12
Add clock/reset entries for USB PHY control, USB2.0 host and device. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220425095244.156720-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28clk: renesas: r9a07g043: Add SSIF-2 clock and reset entriesBiju Das1-0/+20
Add SSIF-2{0,1,2,3} clock and reset entries in CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220425095244.156720-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28clk: renesas: r9a07g043: Add I2C clocks/resetsBiju Das1-0/+12
Add I2C{0,1,2,3} clock and reset entries. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220425095244.156720-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28clk: renesas: r9a06g032: Fix the RTC hclock descriptionMiquel Raynal1-1/+1
It needs to be un-gated, but also a reset must be released and an idle flag should also be disabled. The driver already supports all these operations, so update the description of the RTC hclock to fit these requirements. Fixes: 4c3d88526eba2143 ("clk: renesas: Renesas R9A06G032 clock driver") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20220421090016.79517-3-miquel.raynal@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-25dt-bindings: clock: renesas,cpg-mssr: Document r8a779g0Yoshihiro Shimoda1-0/+1
Add binding documentation for the R-Car V4H (R8A779G0) Clock Pulse Generator. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220420084255.375700-7-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-25clk: renesas: r8a779f0: Add UFS clockYoshihiro Shimoda1-0/+1
Add the module clock used by the UFS host controller on the Renesas R-Car S4-8 (R8A779F0) SoC. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20220411124932.3765571-1-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-25dt-bindings: clock: Add r8a779g0 CPG Core Clock DefinitionsYoshihiro Shimoda1-0/+90
Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20220425064201.459633-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-25dt-bindings: power: Add r8a779g0 SYSC power domain definitionsYoshihiro Shimoda1-0/+45
Add power domain indices for R-Car V4H (r8a779g0). Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220425064201.459633-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13clk: renesas: r9a07g043: Add SDHI clock and reset entriesBiju Das1-0/+35
Add SDHI{0,1} mux, clock and reset entries to CPG driver Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402074626.25624-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13clk: renesas: r9a07g043: Add GbEthernet clock/resetBiju Das1-0/+10
Add ETH{0,1} clock/reset entries to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402074626.25624-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13clk: renesas: r9a07g043: Add ethernet clock sourcesBiju Das1-0/+13
Ethernet reference clock can be sourced from PLL5_500 or PLL6. Add support for ethernet source clock selection using SEL_PLL_6_2 mux. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402074626.25624-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13clk: renesas: r9a07g043: Add GPIO clock and reset entriesBiju Das1-0/+5
Add GPIO clock and reset entries in CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220402074626.25624-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13clk: renesas: Add support for RZ/G2UL SoCBiju Das5-1/+171
The clock structure for RZ/G2UL is almost identical to RZ/G2L SoC with fewer IP blocks. The IP blocks such as WDT1, GPT, H264, GPU and POEG are not present on RZ/G2UL. This patch adds minimal clock and reset entries required to boot the system on Renesas RZ/G2UL SMARC EVK and binds it with the RZ/G2L CPG core driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220412161314.13800-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-13Merge tag 'renesas-r9a07g043-dt-binding-defs-tag' into renesas-clk-for-v5.19Geert Uytterhoeven1-0/+184
Renesas RZ/G2UL DT Binding Definitions Clock and reset definitions for the Renesas RZ/G2UL (R9A07G043) SoC, shared by driver and DT source files.
2022-04-13clk: renesas: Move RPC core clocksGeert Uytterhoeven12-57/+51
The RPC and RPCD2 core clocks were added to the sections for internal core clocks, while they are core clock outputs, visible from DT. Move them to the correct sections. Rename the ".rpc" clock on R-Car S4 to "rpc". Fixup nearby whitespace to increase uniformity. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/a938b938f00939b9206d7fbaba78e2ef09915f5f.1649681891.git.geert+renesas@glider.be
2022-04-13clk: renesas: rzg2l: Simplify multiplication/shift logicGeert Uytterhoeven1-1/+1
"a * (1 << b)" == "a << b". No change in generated code. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/71e1cf2e30fb2d7966fc8ec6bab23eb7e24aa1c4.1645460687.git.geert+renesas@glider.be
2022-04-13dt-bindings: clock: Add R9A07G043 CPG Clock and Reset DefinitionsBiju Das1-0/+184
Define RZ/G2UL (R9A07G043U) Clock Pulse Generator Core Clock and module clock outputs, as listed in Table 7.1.4.2 ("Clock List r0.51") and also add Reset definitions referring to registers CPG_RST_* in Section 7.2.3 ("Register configuration") of the RZ/G2UL Hardware User's Manual (Rev. 0.51, Nov. 2021). Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220402073037.23947-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-11clk: renesas: r8a77995: Add RPC clocksGeert Uytterhoeven2-1/+13
Describe the various clocks used by the SPI Multi I/O Bus Controller (RPC-IF) on the R-Car D3 SoC: RPCSRC internal clock, RPC{,D2} clocks derived from it, and RPC-IF module clock. The RPCSRC clock divider on R-Car D3 is very similar to the one on R-Car E3, but uses a different pre-divider for the PLL0 parent. Add a new macro to describe it, reusing the existing clock type for R-Car E3. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/3fd1e886b7737cd0e199603bae81d01be9dcf3aa.1648546700.git.geert+renesas@glider.be
2022-04-11clk: renesas: r8a77990: Add RPC clocksGeert Uytterhoeven1-0/+9
Describe the various clocks used by the SPI Multi I/O Bus Controller (RPC-IF) on the R-Car E3 SoC: RPCSRC internal clock, RPC{,D2} clocks derived from it, and RPC-IF module clock. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/3295013f27f1e4b8fbf3f79b950d65157ea95ef2.1648546700.git.geert+renesas@glider.be
2022-04-04dt-bindings: clock: renesas: Document RZ/G2UL SoCBiju Das1-3/+4
Document the device tree binding for the Renesas RZ/G2UL Type-1 and Type-2 SoC. RZ/G2UL Type-2 has fewer clocks than RZ/G2UL Type-1 SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220315142915.17764-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04clk: renesas: rzg2l: Remove unused notifiersPhil Edworthy1-2/+0
notifiers is not used. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Link: https://lore.kernel.org/r/20220304143241.8523-1-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-04Linux 5.18-rc1Linus Torvalds1-2/+2
2022-04-03Merge tag 'trace-v5.18-2' of ↵Linus Torvalds15-167/+44
git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace Pull more tracing updates from Steven Rostedt: - Rename the staging files to give them some meaning. Just stage1,stag2,etc, does not show what they are for - Check for NULL from allocation in bootconfig - Hold event mutex for dyn_event call in user events - Mark user events to broken (to work on the API) - Remove eBPF updates from user events - Remove user events from uapi header to keep it from being installed. - Move ftrace_graph_is_dead() into inline as it is called from hot paths and also convert it into a static branch. * tag 'trace-v5.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace: tracing: Move user_events.h temporarily out of include/uapi ftrace: Make ftrace_graph_is_dead() a static branch tracing: Set user_events to BROKEN tracing/user_events: Remove eBPF interfaces tracing/user_events: Hold event_mutex during dyn_event_add proc: bootconfig: Add null pointer check tracing: Rename the staging files for trace_events
2022-04-03Merge tag 'clk-for-linus' of ↵Linus Torvalds2-136/+14
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fix from Stephen Boyd: "A single revert to fix a boot regression seen when clk_put() started dropping rate range requests. It's best to keep various systems booting so we'll kick this out and try again next time" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: Revert "clk: Drop the rate range on clk_put()"
2022-04-03Merge tag 'x86-urgent-2022-04-03' of ↵Linus Torvalds6-187/+200
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fixes from Thomas Gleixner: "A set of x86 fixes and updates: - Make the prctl() for enabling dynamic XSTATE components correct so it adds the newly requested feature to the permission bitmap instead of overwriting it. Add a selftest which validates that. - Unroll string MMIO for encrypted SEV guests as the hypervisor cannot emulate it. - Handle supervisor states correctly in the FPU/XSTATE code so it takes the feature set of the fpstate buffer into account. The feature sets can differ between host and guest buffers. Guest buffers do not contain supervisor states. So far this was not an issue, but with enabling PASID it needs to be handled in the buffer offset calculation and in the permission bitmaps. - Avoid a gazillion of repeated CPUID invocations in by caching the values early in the FPU/XSTATE code. - Enable CONFIG_WERROR in x86 defconfig. - Make the X86 defconfigs more useful by adapting them to Y2022 reality" * tag 'x86-urgent-2022-04-03' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/fpu/xstate: Consolidate size calculations x86/fpu/xstate: Handle supervisor states in XSTATE permissions x86/fpu/xsave: Handle compacted offsets correctly with supervisor states x86/fpu: Cache xfeature flags from CPUID x86/fpu/xsave: Initialize offset/size cache early x86/fpu: Remove unused supervisor only offsets x86/fpu: Remove redundant XCOMP_BV initialization x86/sev: Unroll string mmio with CC_ATTR_GUEST_UNROLL_STRING_IO x86/config: Make the x86 defconfigs a bit more usable x86/defconfig: Enable WERROR selftests/x86/amx: Update the ARCH_REQ_XCOMP_PERM test x86/fpu/xstate: Fix the ARCH_REQ_XCOMP_PERM implementation
2022-04-03Merge tag 'core-urgent-2022-04-03' of ↵Linus Torvalds5-69/+1
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull RT signal fix from Thomas Gleixner: "Revert the RT related signal changes. They need to be reworked and generalized" * tag 'core-urgent-2022-04-03' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: Revert "signal, x86: Delay calling signals in atomic on RT enabled kernels"
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