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2023-01-19arm64: dts: qcom: sc8280xp: rename qup2_uart17 to uart17Brian Masney4-20/+20
In preparation for adding the missing SPI and I2C nodes to sc8280xp.dtsi, it was decided to rename all of the existing qupX_ uart, spi, and i2c nodes to drop the qupX_ prefix. Let's go ahead and rename qup2_uart17 to uart17. Note that some nodes are moved in the file by this patch to preserve the expected sort order in the file. Signed-off-by: Brian Masney <bmasney@redhat.com> Link: https://lore.kernel.org/lkml/20221212182314.1902632-1-bmasney@redhat.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230103182229.37169-4-bmasney@redhat.com
2023-01-19arm64: dts: qcom: sm6115: Pad addresses to 8 hex digitsKonrad Dybcio1-3/+3
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-18-konrad.dybcio@linaro.org
2023-01-19arm64: dts: qcom: msm8994-kitakami: Pad addresses to 8 hex digitsKonrad Dybcio1-1/+1
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-17-konrad.dybcio@linaro.org
2023-01-19arm64: dts: qcom: sm8450: Pad addresses to 8 hex digitsKonrad Dybcio1-24/+24
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-16-konrad.dybcio@linaro.org
2023-01-19arm64: dts: qcom: msm8994-octagon: Pad addresses to 8 hex digitsKonrad Dybcio1-26/+26
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-15-konrad.dybcio@linaro.org
2023-01-19arm64: dts: qcom: sc7280: Pad addresses to 8 hex digitsKonrad Dybcio1-23/+23
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-14-konrad.dybcio@linaro.org
2023-01-19arm64: dts: qcom: sc7180: Pad addresses to 8 hex digitsKonrad Dybcio1-10/+10
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-13-konrad.dybcio@linaro.org
2023-01-19arm64: dts: qcom: sm8350: Pad addresses to 8 hex digitsKonrad Dybcio1-8/+8
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-12-konrad.dybcio@linaro.org
2023-01-19arm64: dts: qcom: sm8250: Pad addresses to 8 hex digitsKonrad Dybcio1-27/+27
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-11-konrad.dybcio@linaro.org
2023-01-19arm64: dts: qcom: sdm845: Pad addresses to 8 hex digitsKonrad Dybcio1-23/+23
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-10-konrad.dybcio@linaro.org
2023-01-19arm64: dts: qcom: sm6350: Pad addresses to 8 hex digitsKonrad Dybcio1-8/+8
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-9-konrad.dybcio@linaro.org
2023-01-19arm64: dts: qcom: sm8150: Pad addresses to 8 hex digitsKonrad Dybcio1-34/+34
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-8-konrad.dybcio@linaro.org
2023-01-19arm64: dts: qcom: sc8280xp: Pad addresses to 8 hex digitsKonrad Dybcio1-1/+1
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-7-konrad.dybcio@linaro.org
2023-01-19arm64: dts: qcom: ipq6018: Use lowercase hexKonrad Dybcio1-1/+1
One value escaped my previous lowercase hexification. Take care of it. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-6-konrad.dybcio@linaro.org
2023-01-19arm64: dts: qcom: ipq6018: Add/remove some newlinesKonrad Dybcio1-14/+12
Some lines were broken very aggresively, presumably to fit under 80 chars and some places could have used a newline, particularly between subsequent nodes. Address all that and remove redundant comments near PCIe ranges while at it so as not to exceed 100 chars needlessly. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-5-konrad.dybcio@linaro.org
2023-01-19arm64: dts: qcom: ipq6018: Sort nodes properlyKonrad Dybcio1-260/+260
Order nodes by unit address if one exists and alphabetically otherwise. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-4-konrad.dybcio@linaro.org
2023-01-19arm64: dts: qcom: ipq6018: Fix up indentationKonrad Dybcio1-22/+22
The dwc3 subnode was indented using spaces for some reason and other properties were not exactly properly indented. Fix it. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-3-konrad.dybcio@linaro.org
2023-01-19arm64: dts: qcom: ipq6018: Pad addresses to 8 hex digitsKonrad Dybcio1-12/+12
Some addresses were 7-hex-digits long, or less. Fix that. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102094642.74254-2-konrad.dybcio@linaro.org
2023-01-19arm64: dts: qcom: sm8550-mtp: Add PCIe PHYs and controllers nodesAbel Vesa1-0/+29
Enable PCIe controllers and PHYs nodes on SM8550 MTP board. Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230118230526.1499328-3-abel.vesa@linaro.org
2023-01-19arm64: dts: qcom: sm8550: Add PCIe PHYs and controllers nodesAbel Vesa1-3/+210
Add PCIe controllers and PHY nodes. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230118230526.1499328-2-abel.vesa@linaro.org
2023-01-19arm64: dts: qcom: sm8550-mtp: enable adsp, cdsp & mdssNeil Armstrong1-0/+18
Add the aDSP, cDSP and MPSS firmware and "Devicetree" firmware paths for the SM8550 MTP platform. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221115-topic-sm8550-upstream-dts-remoteproc-v3-3-815a1753de34@linaro.org
2023-01-19arm64: dts: qcom: sm8550: add adsp, cdsp & mdss nodesNeil Armstrong1-0/+336
This adds support for the aDSP, cDSP and MPSS Subsystems found in the SM8550 SoC. The aDSP, cDSP and MPSS needs: - smp2p nodes to get event back from the subsystems - remoteproc nodes with glink-edge subnodes providing all needed resources to start and run the subsystems In addition, the MPSS Subsystem needs a rmtfs_mem dedicated memory zone. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221115-topic-sm8550-upstream-dts-remoteproc-v3-2-815a1753de34@linaro.org
2023-01-19arm64: dts: qcom: sm8550: Add interconnect path to SCM nodeAbel Vesa1-0/+1
Add the interconnect path to SCM dts node. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221115-topic-sm8550-upstream-dts-remoteproc-v3-1-815a1753de34@linaro.org
2023-01-19arm64: dts: qcom: sm8550-mtp: add DSI panelNeil Armstrong1-0/+54
Add nodes for the Visionox VTDR6130 found on the SM8550-MTP device. TLMM states are also added for the Panel reset GPIO and Tearing Effect signal for when the panel is running in DSI Command mode. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104-topic-sm8550-upstream-dts-display-v4-3-1729cfc0e5db@linaro.org
2023-01-19arm64: dts: qcom: sm8550-mtp: enable display hardwareNeil Armstrong1-0/+22
Enable MDSS/DPU/DSI0 on SM8550-MTP device. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104-topic-sm8550-upstream-dts-display-v4-2-1729cfc0e5db@linaro.org
2023-01-19arm64: dts: qcom: sm8550: add display hardware devicesNeil Armstrong1-0/+300
Add devices tree nodes describing display hardware on SM8550: - Display Clock Controller - MDSS - MDP - two DSI controllers and DSI PHYs This does not provide support for DP controllers present on the SM8550. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104-topic-sm8550-upstream-dts-display-v4-1-1729cfc0e5db@linaro.org
2023-01-19Merge branch ↵Bjorn Andersson2-0/+206
'20230103-topic-sm8550-upstream-dispcc-v3-1-8a03d348c572@linaro.org' into HEAD Merge the DT binding in order to get the dispcc include file.
2023-01-19dt-bindings: clock: document SM8550 DISPCC clock controllerNeil Armstrong2-0/+206
Document device tree bindings for display clock controller for Qualcomm SM8550 SoC. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230103-topic-sm8550-upstream-dispcc-v3-1-8a03d348c572@linaro.org
2023-01-19arm64: dts: qcom: sm8550: fix xo clock source in cpufreq-hw nodePavankumar Kondeti1-1/+1
Currently, available frequencies for all CPUs are appearing as 2x of the actual frequencies. Use xo clock source as bi_tcxo in the cpufreq-hw node to fix this. Signed-off-by: Pavankumar Kondeti <quic_pkondeti@quicinc.com> Tested-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230117093533.3710000-1-quic_pkondeti@quicinc.com
2023-01-19arm64: dts: qcom: msm8916-samsung-j5-common: Add MUIC supportMarkuss Broks2-8/+50
The MUIC installed is a part of SM5703 MFD, and it seems to work the same as the SM5502 MUIC unit. Signed-off-by: Markuss Broks <markuss.broks@gmail.com> [Apply for msm8916-samsung-j5x] Signed-off-by: Lin, Meng-Bo <linmengbo0689@protonmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230106143051.547302-1-linmengbo0689@protonmail.com
2023-01-19arm64: dts: qcom: msm8916-samsung-j5-common: Add Hall sensorLin, Meng-Bo1-0/+26
Samsung Galaxy J5 2015 and 2016 have a Hall sensor on GPIO pin 52. Add GPIO Hall sensor for them. Signed-off-by: Lin, Meng-Bo <linmengbo0689@protonmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230106143037.547248-1-linmengbo0689@protonmail.com
2023-01-19arm64: dts: qcom: msm8916-samsung-j5-common: Add new device treesLin, Meng-Bo2-0/+12
After moving msm8916-samsung-j5.dts to msm8916-samsung-j5-common.dtsi, Add new J5 2016 device tree. [Add j5x device tree] Co-developed-by: Josef W Menad <JosefWMenad@protonmail.ch> Signed-off-by: Josef W Menad <JosefWMenad@protonmail.ch> [Use &pm8916_usbin as USB extcon and add chassis-type for j5x] Co-developed-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> [Use common init device tree] Signed-off-by: Lin, Meng-Bo <linmengbo0689@protonmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230106143024.547194-1-linmengbo0689@protonmail.com
2023-01-19arm64: dts: qcom: msm8916-samsung-j5-common: Add initial common device treeLin, Meng-Bo2-195/+203
The smartphones below are using the MSM8916 SoC, which are released in 2015-2016: Samsung Galaxy J5 2015 (SM-J500*) Samsung Galaxy J5 2016 (SM-J510*) Move msm8916-samsung-j5.dts to msm8916-samsung-j5-common.dtsi, and add a common device tree for with initial support for: - GPIO keys - SDHCI (internal and external storage) - USB Device Mode - UART (on USB connector via the SM5703 MUIC) - WCNSS (WiFi/BT) - Regulators The two devices (all other variants of J5 released in 2015 and J5X released in 2016) are very similar, with some differences in display and GPIO pins. The common parts are shared in msm8916-samsung-j5-common.dtsi to reduce duplication. This patch rewrites J5 2015 devices, later patches will add support for other models. Signed-off-by: Lin, Meng-Bo <linmengbo0689@protonmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230106143010.547140-1-linmengbo0689@protonmail.com
2023-01-19arm64: dts: qcom: sm7225-fairphone-fp4: enable IPALuca Weiss1-0/+7
IPA is used for mobile data. Enable it. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104193759.3286014-3-elder@linaro.org
2023-01-19arm64: dts: qcom: sm6350: add IPA nodeLuca Weiss1-0/+47
IPA is used for mobile data. Add a node describing it. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104193759.3286014-2-elder@linaro.org
2023-01-19arm64: dts: qcom: sm6350: Set up DDR & L3 scalingKonrad Dybcio2-0/+159
Add the CPU OPP tables including core frequency and L3 bus frequency. The L3 throughput values were chosen by studying the frequencies available in HW LUT and picking the highest one that's less than the CPU frequency. DDR clock rates come from the vendor kernel. Available values from the HW LUT: 300000000 556800000 652800000 806400000 844800000 940800000 1132800000 1209600000 1286400000 1401600000 1459200000 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104171643.1004054-3-konrad.dybcio@linaro.org
2023-01-19arm64: dts: qcom: sm6350: Add OSM L3 nodeKonrad Dybcio1-0/+10
Enable the OSM block responsible for scaling the L3 cache. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104171643.1004054-2-konrad.dybcio@linaro.org
2023-01-19arm64: dts: qcom: qcs404: specify per-sensor calibration cellsDmitry Baryshkov1-5/+140
Specify pre-parsed per-sensor calibration nvmem cells in the tsens device node rather than parsing the whole data blob in the driver. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230101194034.831222-19-dmitry.baryshkov@linaro.org
2023-01-19arm64: dts: qcom: msm8976: specify per-sensor calibration cellsDmitry Baryshkov1-4/+149
Specify pre-parsed per-sensor calibration nvmem cells in the tsens device node rather than parsing the whole data blob in the driver. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230101194034.831222-18-dmitry.baryshkov@linaro.org
2023-01-19arm64: dts: qcom: msm8916: specify per-sensor calibration cellsDmitry Baryshkov1-6/+79
Specify pre-parsed per-sensor calibration nvmem cells in the tsens device node rather than parsing the whole data blob in the driver. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230101194034.831222-17-dmitry.baryshkov@linaro.org
2023-01-19arm64: dts: qcom: msm8956: use SoC-specific compat for tsensDmitry Baryshkov1-0/+4
The slope values used during tsens calibration differ between msm8976 and msm8956 SoCs. Use SoC-specific compat value for the msm8956 SoC. Fixes: 0484d3ce0902 ("arm64: dts: qcom: Add DTS for MSM8976 and MSM8956 SoCs") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230101194034.831222-16-dmitry.baryshkov@linaro.org
2023-01-19arm64: dts: qcom: use qcom,gsi-loader for IPAAlex Elder14-19/+24
Depending on the platform, either the modem or the AP must load GSI firmware for IPA before it can be used. To date, this has been indicated by the presence or absence of a "modem-init" property. That mechanism has been deprecated. Instead, we indicate how GSI firmware should be loaded by the value of the "qcom,gsi-loader" property. Update all arm64 platforms that use IPA to use the "qcom,gsi-loader" property to specify how the GSI firmware is loaded. Update the affected nodes so the status property is last. Signed-off-by: Alex Elder <elder@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> [bjorn: Moved sc7280 change herobrine-lte-sku] Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221231002716.2367375-3-elder@linaro.org
2023-01-19dt-bindings: qcom: Document bindings for msm8916-samsung-j5xLin, Meng-Bo1-0/+1
Document the new samsung-j5x device tree bindings used in its device tree. Signed-off-by: Lin, Meng-Bo <linmengbo0689@protonmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230106142956.547081-1-linmengbo0689@protonmail.com
2023-01-19ARM: dts: qcom: use qcom,gsi-loader for IPAAlex Elder2-4/+4
Depending on the platform, either the modem or the AP must load GSI firmware for IPA before it can be used. To date, this has been indicated by the presence or absence of a "modem-init" property. That mechanism has been deprecated. Instead, we indicate how GSI firmware should be loaded by the value of the "qcom,gsi-loader" property. Update all ARM platforms that use IPA to use the "qcom,gsi-loader" property to specify how the GSI firmware is loaded. Update the affected nodes so the status property is last. Signed-off-by: Alex Elder <elder@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221231002716.2367375-2-elder@linaro.org
2023-01-19ARM: dts: qcom-apq8084: specify per-sensor calibration cellsDmitry Baryshkov1-6/+307
Specify pre-parsed per-sensor calibration nvmem cells in the tsens device node rather than parsing the whole data blob in the driver. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230101194034.831222-21-dmitry.baryshkov@linaro.org
2023-01-19ARM: dts: qcom-msm8974: specify per-sensor calibration cellsDmitry Baryshkov1-6/+307
Specify pre-parsed per-sensor calibration nvmem cells in the tsens device node rather than parsing the whole data blob in the driver. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230101194034.831222-20-dmitry.baryshkov@linaro.org
2023-01-19arm64: dts: qcom: sc7280-idp: add amp pin config functionKrzysztof Kozlowski1-0/+1
Bindings expect each pin config to come with a "function" property: sc7280-crd-r3.dtb: pinctrl@f100000: amp-en-state: 'oneOf' conditional failed, one must be fixed: 'function' is a required property 'bias-pull-down', 'drive-strength', 'pins' do not match any of the regexes: '-pins$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221230135645.56401-9-krzysztof.kozlowski@linaro.org
2023-01-19arm64: dts: qcom: msm8916-samsung-a2015: correct motor pinctrl node nameKrzysztof Kozlowski1-1/+1
Correct typo in motor pinctrl node name: msm8916-samsung-a5u-eur.dtb: pinctrl@1000000: 'motor-en-default-stae' does not match any of the regexes: '-state$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221230135645.56401-8-krzysztof.kozlowski@linaro.org
2023-01-19arm64: dts: qcom: msm8992-bullhead: Disable dfps_data_memPetr Vorel1-0/+3
It's disabled on downstream [1] thus not shown on downstream dmesg. Removing it fixes warnings on v6.1: [ 0.000000] OF: reserved mem: OVERLAP DETECTED! [ 0.000000] dfps_data_mem@3400000 (0x0000000003400000--0x0000000003401000) overlaps with memory@3400000 (0x0000000003400000--0x0000000004600000) [1] https://android.googlesource.com/kernel/msm.git/+/android-7.0.0_r0.17/arch/arm64/boot/dts/lge/msm8992-bullhead.dtsi#137 Fixes: 976d321f32dc ("arm64: dts: qcom: msm8992: Make the DT an overlay on top of 8994") Signed-off-by: Petr Vorel <petr.vorel@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221226185440.440968-3-pevik@seznam.cz
2023-01-19arm64: dts: qcom: msm8992-bullhead: Fix cont_splash_mem sizePetr Vorel1-2/+2
Original google firmware reports 12 MiB: [ 0.000000] cma: Found cont_splash_mem@0, memory base 0x0000000003400000, size 12 MiB, limit 0xffffffffffffffff which is actually 12*1024*1024 = 0xc00000. This matches the aosp source [1]: &cont_splash_mem { reg = <0 0x03400000 0 0xc00000>; }; Fixes: 3cb6a271f4b0 ("arm64: dts: qcom: msm8992-bullhead: Fix cont_splash_mem mapping") Fixes: 976d321f32dc ("arm64: dts: qcom: msm8992: Make the DT an overlay on top of 8994") [1] https://android.googlesource.com/kernel/msm.git/+/android-7.0.0_r0.17/arch/arm64/boot/dts/lge/msm8992-bullhead.dtsi#141 Signed-off-by: Petr Vorel <petr.vorel@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221226185440.440968-2-pevik@seznam.cz
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