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2023-04-25Merge branch 'clk-imx' into clk-nextStephen Boyd16-47/+517
* clk-imx: (25 commits) clk: imx: imx8ulp: update clk flag for system critical clock clk: imx: imx8ulp: Add tpm5 clock as critical gate clock clk: imx: imx8ulp: keep MU0_B clock enabled always clk: imx: imx8ulp: Add divider closest support to get more accurate clock rate clk: imx: imx8ulp: Fix XBAR_DIVBUS and AD_SLOW clock parents clk: imx: imx93: Add nic and A55 clk dt-bindings: clock: imx93: add NIC, A55 and ARM PLL CLK clk: imx: imx93: add mcore_booted module paratemter clk: imx: fracn-gppll: Add 300MHz freq support for imx9 clk: imx: fracn-gppll: support integer pll clk: imx: fracn-gppll: disable hardware select control clk: imx: fracn-gppll: fix the rate table clk: imx: imx8mp: change the 'nand_usdhc_bus' clock to non-critical clk: imx: imx8mp: Add LDB root clock dt-bindings: clock: imx8mp: Add LDB clock entry clk: imx: imx8mp: correct DISP2 pixel clock type clk: imx: drop duplicated macro clk: imx: clk-gpr-mux: Provide clock name in error message clk: imx: Let IMX8MN_CLK_DISP_PIXEL set parent rate clk: imx8mm: Let IMX8MM_CLK_LCDIF_PIXEL set parent rate ...
2023-04-25Merge branches 'clk-of', 'clk-samsung', 'clk-rockchip' and 'clk-qcom' into ↵Stephen Boyd84-1086/+19934
clk-next * clk-of: clk: add missing of_node_put() in "assigned-clocks" property parsing * clk-samsung: clk: samsung: exynos850: Make PMU_ALIVE_PCLK critical clk: samsung: Convert to platform remove callback returning void clk: samsung: exynos5433: Extract PM support to common ARM64 layer clk: samsung: Extract parent clock enabling to common function clk: samsung: Extract clocks registration to common function clk: samsung: exynos850: Add AUD and HSI main gate clocks clk: samsung: exynos850: Implement CMU_G3D domain clk: samsung: clk-pll: Implement pll0818x PLL type clk: samsung: Set dev in samsung_clk_init() clk: samsung: Don't pass reg_base to samsung_clk_register_pll() clk: samsung: Remove np argument from samsung_clk_init() dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D * clk-rockchip: clk: rockchip: rk3588: make gate linked clocks critical clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparent * clk-qcom: (57 commits) clk: qcom: gcc-sc8280xp: Add EMAC GDSCs clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clk clk: qcom: add the GPUCC driver for sa8775p dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handling clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in lpass_cc_sc7280_desc clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode property clk: qcom: rpm: Use managed `of_clk_add_hw_provider()` clk: qcom: Add Global Clock Controller driver for IPQ9574 dt-bindings: clock: Add ipq9574 clock and reset definitions clk: qcom: gpucc-sm6375: Configure CX_GDSC disable wait value clk: qcom: gcc-sm6115: Mark RCGs shared where applicable clk: qcom: dispcc-qcm2290: Add MDSS_CORE reset dt-bindings: clock: dispcc-qcm2290: Add MDSS_CORE reset clk: qcom: apss-ipq-pll: add support for IPQ5332 dt-bindings: clock: qcom,a53pll: add IPQ5332 compatible clk: qcom: apss-ipq-pll: refactor the driver to accommodate different PLL types dt-bindings: mailbox: qcom,apcs-kpss-global: fix SDX55 'if' match dt-bindings: mailbox: qcom,apcs-kpss-global: correct SDX55 clocks ...
2023-04-25Merge branches 'clk-starfive', 'clk-fractional' and 'clk-devmof' into clk-nextStephen Boyd40-955/+2353
- Shrink size of clk_fractional_divider a little - Convert various clk drivers to devm_of_clk_add_hw_provider() * clk-starfive: clk: starfive: Delete the redundant dev_set_drvdata() in JH7110 clock drivers clk: starfive: Avoid casting iomem pointers MAINTAINERS: generalise StarFive clk/reset entries reset: starfive: Add StarFive JH7110 reset driver clk: starfive: Add StarFive JH7110 always-on clock driver clk: starfive: Add StarFive JH7110 system clock driver reset: starfive: jh71x0: Use 32bit I/O on 32bit registers reset: starfive: Rename "jh7100" to "jh71x0" for the common code reset: starfive: Extract the common JH71X0 reset code reset: starfive: Factor out common JH71X0 reset code reset: Create subdirectory for StarFive drivers reset: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE clk: starfive: Rename "jh7100" to "jh71x0" for the common code clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h clk: starfive: Factor out common JH7100 and JH7110 code clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator dt-bindings: clock: Add StarFive JH7110 system clock and reset generator * clk-fractional: clk: Remove mmask and nmask fields in struct clk_fractional_divider clk: rockchip: Remove values for mmask and nmask in struct clk_fractional_divider clk: imx: Remove values for mmask and nmask in struct clk_fractional_divider clk: Compute masks for fractional_divider clk when needed. * clk-devmof: clk: uniphier: Use managed `of_clk_add_hw_provider()` clk: si5351: Use managed `of_clk_add_hw_provider()` clk: si570: Use managed `of_clk_add_hw_provider()` clk: si514: Use managed `of_clk_add_hw_provider()` clk: lmk04832: Use managed `of_clk_add_hw_provider()` clk: hsdk-pll: Use managed `of_clk_add_hw_provider()` clk: cdce706: Use managed `of_clk_add_hw_provider()` clk: axs10x: Use managed `of_clk_add_hw_provider()` clk: axm5516: Use managed `of_clk_add_hw_provider()` clk: axi-clkgen: Use managed `of_clk_add_hw_provider()`
2023-04-25Merge branches 'clk-xilinx', 'clk-broadcom' and 'clk-platform' into clk-nextStephen Boyd41-155/+564
- BCM63268 timer clock and reset controller - Convert platform clk drivers to remove_new * clk-xilinx: clocking-wizard: Support higher frequency accuracy clk: zynqmp: pll: Remove the limit * clk-broadcom: clk: bcm: Add BCM63268 timer clock and reset driver dt-bindings: clock: Add BCM63268 timer binding dt-bindings: reset: add BCM63268 timer reset definitions dt-bindings: clk: add BCM63268 timer clock definitions * clk-platform: (25 commits) clk: xilinx: Convert to platform remove callback returning void clk: x86: Convert to platform remove callback returning void clk: uniphier: Convert to platform remove callback returning void clk: ti: Convert to platform remove callback returning void clk: tegra: Convert to platform remove callback returning void clk: stm32: Convert to platform remove callback returning void clk: mvebu: Convert to platform remove callback returning void clk: mmp: Convert to platform remove callback returning void clk: keystone: Convert to platform remove callback returning void clk: hisilicon: Convert to platform remove callback returning void clk: stm32mp1: Convert to platform remove callback returning void clk: scpi: Convert to platform remove callback returning void clk: s2mps11: Convert to platform remove callback returning void clk: pwm: Convert to platform remove callback returning void clk: palmas: Convert to platform remove callback returning void clk: hsdk-pll: Convert to platform remove callback returning void clk: fixed-rate: Convert to platform remove callback returning void clk: fixed-mmio: Convert to platform remove callback returning void clk: fixed-factor: Convert to platform remove callback returning void clk: axm5516: Convert to platform remove callback returning void ...
2023-04-25Merge branches 'clk-mediatek', 'clk-sunplus', 'clk-loongson' and ↵Stephen Boyd205-4897/+9286
'clk-socfpga' into clk-next - Frequency Hopping (FHCTL) on MediaTek MT6795, MT8173, MT8192 and MT8195 SoCs - Converted most Mediatek clock drivers to struct platform_driver - MediaTek clock drivers can be built as modules - Mediatek MT8188 SoC clk drivers - Clock driver for Sunplus SP7021 SoC - Reimplement Loongson-1 clk driver with DT support - Clk driver support for Loongson-2 SoCs - Migrate socfpga clk driver to of_clk_add_hw_provider() * clk-mediatek: (84 commits) clk: mediatek: fhctl: Mark local variables static clk: mediatek: Use right match table, include mod_devicetable clk: mediatek: Add MT8188 adsp clock support clk: mediatek: Add MT8188 imp i2c wrapper clock support clk: mediatek: Add MT8188 wpesys clock support clk: mediatek: Add MT8188 vppsys1 clock support clk: mediatek: Add MT8188 vppsys0 clock support clk: mediatek: Add MT8188 vencsys clock support clk: mediatek: Add MT8188 vdosys1 clock support clk: mediatek: Add MT8188 vdosys0 clock support clk: mediatek: Add MT8188 vdecsys clock support clk: mediatek: Add MT8188 mfgcfg clock support clk: mediatek: Add MT8188 ipesys clock support clk: mediatek: Add MT8188 imgsys clock support clk: mediatek: Add MT8188 ccusys clock support clk: mediatek: Add MT8188 camsys clock support clk: mediatek: Add MT8188 infrastructure clock support clk: mediatek: Add MT8188 peripheral clock support clk: mediatek: Add MT8188 topckgen clock support clk: mediatek: Add MT8188 apmixedsys clock support ... * clk-sunplus: clk: Add Sunplus SP7021 clock driver * clk-loongson: clk: clk-loongson2: add clock controller driver support dt-bindings: clock: add loongson-2 boot clock index MAINTAINERS: remove obsolete file entry in MIPS/LOONGSON1 ARCHITECTURE MIPS: loongson32: Update the clock initialization clk: loongson1: Re-implement the clock driver clk: loongson1: Remove the outdated driver dt-bindings: clock: Add Loongson-1 clock * clk-socfpga: clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling clk: socfpga: use of_clk_add_hw_provider and improve error handling clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling clk: socfpga: use of_clk_add_hw_provider and improve error handling clk: socfpga: arria10: use of_clk_add_hw_provider and improve error handling clk: socfpga: use of_clk_add_hw_provider and improve error handling
2023-04-25Merge branches 'clk-cleanup', 'clk-aspeed', 'clk-dt', 'clk-renesas' and ↵Stephen Boyd26-265/+1216
'clk-skyworks' into clk-next - Support for i3c clks on Aspeed ast2600 SoCs - Clock driver for Skyworks Si521xx I2C PCIe clock generators * clk-cleanup: clk: microchip: fix potential UAF in auxdev release callback clk: sifive: make SiFive clk drivers depend on ARCH_ symbols clk: stm32h7: Remove an unused field in struct stm32_fractional_divider clk: tegra20: fix gcc-7 constant overflow warning clock: milbeaut: use devm_platform_get_and_ioremap_resource() clk: Print an info line before disabling unused clocks clk: ti: Use of_address_to_resource() clk: remove unnecessary (void*) conversions clk: at91: clk-sam9x60-pll: fix return value check clk: visconti: remove unused visconti_pll_provider::regmap * clk-aspeed: dt-bindings: clock: ast2600: Expand comment on reset definitions clk: ast2600: Add comment about combined clock + reset handling dt-bindings: clock: ast2600: remove IC36 & I3C7 clock definitions clk: ast2600: Add full configs for I3C clocks dt-bindings: clock: ast2600: Add top-level I3C clock clk: ast2600: allow empty entries in aspeed_g6_gates * clk-dt: clk: mediatek: clk-pllfh: fix missing of_node_put() in fhctl_parse_dt() clk: Use of_property_present() for testing DT property presence * clk-renesas: clk: renesas: r8a77980: Add I2C5 clock clk: rs9: Add support for 9FGV0441 clk: rs9: Support device specific dif bit calculation dt-bindings: clk: rs9: Add 9FGV0441 clk: rs9: Check for vendor/device ID clk: renesas: Convert to platform remove callback returning void clk: renesas: r9a06g032: Improve clock tables clk: renesas: r9a06g032: Document structs clk: renesas: r9a06g032: Drop unused fields clk: renesas: r9a06g032: Improve readability clk: renesas: r8a77980: Add Z2 clock clk: renesas: r8a77970: Add Z2 clock clk: renesas: r8a77995: Fix VIN parent clock clk: renesas: r8a77980: Add VIN clocks clk: renesas: r8a779g0: Add VIN clocks clk: renesas: r8a779g0: Add ISPCS clocks clk: renesas: r8a779g0: Add CSI-2 clocks clk: renesas: r8a779g0: Add thermal clock clk: renesas: r8a779g0: Add Audio clocks clk: renesas: cpg-mssr: Update MSSR register range for R-Car V4H * clk-skyworks: clk: si521xx: Clock driver for Skyworks Si521xx I2C PCIe clock generators dt-bindings: clk: si521xx: Add Skyworks Si521xx I2C PCIe clock generators
2023-04-25Merge tag 'qcom-clk-for-6.4' of ↵Stephen Boyd63-837/+19422
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom Pull Qualcomm clk driver updates from Bjorn Andersson: New drivers for Global clock controller on SM7150, IPQ9574, MSM8917 and IPQ5332 are added. New GPU clock controllers for SM6115, SM6125, SM6375 and SA8775P are added. The APSS IPQ PLL driver is refactored to support different PLL types, support for the Stromer Plus PLL type is added, and support for IPQ5332 is introduced. Helpers for settings sleep, wake and retain bits of CBCR registers are introduced and used in some of the newly introduced GPU clock drivers. The platform_driver remove callbacks is transitioned to remove_new, as part of the system wide cleanup effort. In the Display clock controller for QCM2290, the MDSS_CORE reset is introduced and the non-existent DSI1PHY clock is removed. IPQ4019 Global clock controller is transitioned to parent_data. USB GDSCs in SM6375, MSM8996 and MSM8998 are changed to use retention as disabled state, to avoid collapsing them during suspend. The CX GDSC in the SM6375 GPU clock controller has it's disable-wait value corrected. QCM2290 SDCC2 src clock moves to floor_ops. The two EMAC GDSCs are added for SC8280XP. Relevant RCGs in the SM6115 Global clock controller are moved to use shared_ops. PCIe PIPE clock operations on SM8350 are updated, to ensure the mux is parked when the parent PLL is disabled. GDSCs are added to the SC7280 LPASS audio clock controller. The RPM clock controller is transitioned to use the managed version of of_clk_add_hw_provider(). Missing XO clocks are added to MSM8226 and MSM8974. DeviceTree bindings are added for the various newly supported clock controllers, the binding for KPSS ACC and GCC drivers are converted to YAML and a few fixes are introduced. * tag 'qcom-clk-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (57 commits) clk: qcom: gcc-sc8280xp: Add EMAC GDSCs clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clk clk: qcom: add the GPUCC driver for sa8775p dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handling clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in lpass_cc_sc7280_desc clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode property clk: qcom: rpm: Use managed `of_clk_add_hw_provider()` clk: qcom: Add Global Clock Controller driver for IPQ9574 dt-bindings: clock: Add ipq9574 clock and reset definitions clk: qcom: gpucc-sm6375: Configure CX_GDSC disable wait value clk: qcom: gcc-sm6115: Mark RCGs shared where applicable clk: qcom: dispcc-qcm2290: Add MDSS_CORE reset dt-bindings: clock: dispcc-qcm2290: Add MDSS_CORE reset clk: qcom: apss-ipq-pll: add support for IPQ5332 dt-bindings: clock: qcom,a53pll: add IPQ5332 compatible clk: qcom: apss-ipq-pll: refactor the driver to accommodate different PLL types dt-bindings: mailbox: qcom,apcs-kpss-global: fix SDX55 'if' match dt-bindings: mailbox: qcom,apcs-kpss-global: correct SDX55 clocks ...
2023-04-24clk: qcom: gcc-sc8280xp: Add EMAC GDSCsAndrew Halaney2-0/+20
Add the EMAC GDSCs to allow the EMAC hardware to be enabled. Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Andrew Halaney <ahalaney@redhat.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230413191541.1073027-2-ahalaney@redhat.com
2023-04-18Merge tag 'v6.4-rockchip-clk1' of ↵Stephen Boyd2-17/+27
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull a couple Rockchip clk driver updates from Heiko Stübner: Reparenting fix for the clock supplying camera modules on the rk3399 and more critical (bus-)clocks on the rk3588. * tag 'v6.4-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: rk3588: make gate linked clocks critical clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparent
2023-04-18clk: starfive: Delete the redundant dev_set_drvdata() in JH7110 clock driversHal Feng2-4/+0
The dev_set_drvdata() is no longer needed after we used a wrapper struct to get the data in auxiliary driver. Cc: Xingyu Wu <xingyu.wu@starfivetech.com> Fixes: d1aae0663023 ("clk: starfive: Avoid casting iomem pointers") Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Link: https://lore.kernel.org/r/20230417074115.30786-3-hal.feng@starfivetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-04-18clk: rockchip: rk3588: make gate linked clocks criticalSebastian Reichel1-16/+26
RK3588 has a couple of hardware blocks called Native Interface Unit (NIU) that gate the clocks to devices behind them. Effectively this means that some clocks require two parent clocks being enabled. Downstream implemented this by using a separate clock driver ("clk-link") for them, which enables the second clock using PM framework. In the upstream kernel we are currently missing support for the second parent. The information about it is in the GATE_LINK() macro as linkname, but that is not used. Thus the second parent clock is not properly enabled. So far this did not really matter, since these clocks are mostly required for the more advanced IP blocks, that are not yet supported upstream. As this is about to change we need a fix. There are three options available: 1. Properly implement support for having two parent clocks in the clock framework. 2. Mark the affected clocks CLK_IGNORE_UNUSED, so that they are not disabled. This wastes some power, but keeps the hack contained within the clock driver. Going from this to the first solution is easy once that has been implemented. 3. Enabling the extra clock in the consumer driver. This leaks some implementation details into DT. This patch implements the second option as an intermediate solution until the first one is available. I used an alias for CLK_IS_CRITICAL, so that it's easy to see which clocks are not really critical once the clock framework supports a better way to implement this. Tested-by: Vincent Legoll <vincent.legoll@gmail.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20230403193250.108693-2-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2023-04-14clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clkKonrad Dybcio1-3/+0
There's only one DSI PHY on this SoC. Remove the ghost entry for the clock produced by a secondary one. Fixes: cc517ea3333f ("clk: qcom: Add display clock controller driver for QCM2290") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230412-topic-qcm_dispcc-v1-2-bf2989a75ae4@linaro.org
2023-04-14clk: qcom: add the GPUCC driver for sa8775pShazad Hussain3-0/+635
Add the clock driver for the Qualcomm Graphics Clock control module. Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> [Bartosz: make ready for upstream] Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230411125910.401075-3-brgl@bgdev.pl
2023-04-14dt-bindings: clock: qcom: describe the GPUCC clock for SA8775PBartosz Golaszewski2-0/+52
Add the compatible for the Qualcomm Graphics Clock control module present on sa8775p platforms. It matches the generic QCom GPUCC description. Add device-specific DT bindings defines as well. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230411125910.401075-2-brgl@bgdev.pl
2023-04-14clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handlingDmitry Baryshkov1-34/+13
On SM8350 platform the PCIe PIPE clocks require additional handling to function correctly. They are to be switched to the tcxo source before turning PCIe GDSCs off and should be switched to PHY PIPE source once they are working. Switch PCIe PHY clocks to use clk_regmap_phy_mux_ops, which provide support for this dance. Fixes: 44c20c9ed37f ("clk: qcom: gcc: Add clock driver for SM8350") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230412134829.3686467-1-dmitry.baryshkov@linaro.org
2023-04-14clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in ↵Mohammad Rafi Shaik1-0/+2
lpass_cc_sc7280_desc Add GDSCs in lpass_cc_sc7280_desc struct. When qcom,adsp-pil-mode is enabled, GDSCs required to solve dependencies in lpass_audiocc probe(). Fixes: 0cbcfbe50cbf ("clk: qcom: lpass: Handle the regmap overlap of lpasscc and lpass_aon") Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230407092255.119690-4-quic_mohs@quicinc.com
2023-04-14clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registrationSrinivasa Rao Mandadapu1-6/+10
The qdsp6ss memory region is being shared by ADSP remoteproc device and lpasscc clock device, hence causing memory conflict. To avoid this, when qdsp6ss clocks are being enabled in remoteproc driver, skip qdsp6ss clock registration if "qcom,adsp-pil-mode" is enabled and also assign max_register value. Fixes: 4ab43d171181 ("clk: qcom: Add lpass clock controller driver for SC7280") Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230407092255.119690-3-quic_mohs@quicinc.com
2023-04-14dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode propertySrinivasa Rao Mandadapu1-0/+7
When this property is set, the remoteproc is used to boot the LPASS and therefore qdsp6ss clocks would be used to bring LPASS out of reset, hence they are directly controlled by the remoteproc. This is a cleanup done to handle overlap of regmap of lpasscc and adsp remoteproc blocks. Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230407092255.119690-2-quic_mohs@quicinc.com
2023-04-14clk: starfive: Avoid casting iomem pointersStephen Boyd3-6/+35
Let's use a wrapper struct for the auxiliary_device made in jh7110_reset_controller_register() so that we can stop casting iomem pointers. The casts trip up tools like sparse, and make for some awkward casts that are largely unnecessary. While we're here, change the allocation from devm and actually free the auxiliary_device memory in the release function. This avoids any use after free problems where the parent device driver is unbound from the device but the auxiliuary_device is still in use accessing devm freed memory. Cc: Tommaso Merciai <tomm.merciai@gmail.com> Cc: Emil Renner Berthing <emil.renner.berthing@canonical.com> Cc: Hal Feng <hal.feng@starfivetech.com> Cc: Conor Dooley <conor.dooley@microchip.com> Cc: Xingyu Wu <xingyu.wu@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Fixes: edab7204afe5 ("clk: starfive: Add StarFive JH7110 system clock driver") Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20230413205528.4044216-1-sboyd@kernel.org
2023-04-14clk: microchip: fix potential UAF in auxdev release callbackConor Dooley1-2/+1
Similar to commit 1c11289b34ab ("peci: cpu: Fix use-after-free in adev_release()"), the auxiliary device is not torn down in the correct order. If auxiliary_device_add() fails, the release callback will be called twice, resulting in a UAF. Due to timing, the auxdev code in this driver "took inspiration" from the aforementioned commit, and thus its bugs too! Moving auxiliary_device_uninit() to the unregister callback instead avoids the issue. CC: stable@vger.kernel.org Fixes: b56bae2dd6fd ("clk: microchip: mpfs: add reset controller") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230413-critter-synopsis-dac070a86cb4@spud Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-04-13Merge tag 'clk-imx-6.4' of ↵Stephen Boyd16-46/+535
git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx Pull i.MX clk driver updates from Abel Vesa: - Add clock generic devm_clk_hw_register_gate_parent_data. - Add audiomix block control for i.MX8MP. - Add support for determine_rate to composite-8m. - Add new macro for composite-8m to allow custom flags. - Let the LCDIF Pixel clock of i.MX8MM and i.MX8MN set parent rate. - Provide clock name in error message for clk-gpr-mux on get parent failure. - Drop duplicate imx_clk_mux_flags macro. - Register the i.MX8MP Media Disp2 Pix clock as bus clock. - Add Media LDB root clock to i.MX8MP. - Make i.MX8MP nand_usdhc_bus clock as non-critical. - Fix the rate table for fracn-gppll. - Disable HW control for the fracn-gppll in order to be controlled by register write. - Add support for interger PLL in fracn-gppll. - Add mcore_booted module parameter to i.MX93 provider. - Add NIC, A55 and ARM PLL clocks to i.MX93. - Fix i.MX8ULP XBAR_DIVBUS and AD_SLOW clock parents. - Use "divider closest" clock type for PLL4_PFD dividers on i.MX8ULP to get more accurate clock rates. - Mark the MU0_Bi and TPM5 clocks on i.MX8ULP as critical. - Update some of the critical clocks flags to allow glitchless on-the-fly rate change. * tag 'clk-imx-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux: (25 commits) clk: imx: imx8ulp: update clk flag for system critical clock clk: imx: imx8ulp: Add tpm5 clock as critical gate clock clk: imx: imx8ulp: keep MU0_B clock enabled always clk: imx: imx8ulp: Add divider closest support to get more accurate clock rate clk: imx: imx8ulp: Fix XBAR_DIVBUS and AD_SLOW clock parents clk: imx: imx93: Add nic and A55 clk dt-bindings: clock: imx93: add NIC, A55 and ARM PLL CLK clk: imx: imx93: add mcore_booted module paratemter clk: imx: fracn-gppll: Add 300MHz freq support for imx9 clk: imx: fracn-gppll: support integer pll clk: imx: fracn-gppll: disable hardware select control clk: imx: fracn-gppll: fix the rate table clk: imx: imx8mp: change the 'nand_usdhc_bus' clock to non-critical clk: imx: imx8mp: Add LDB root clock dt-bindings: clock: imx8mp: Add LDB clock entry clk: imx: imx8mp: correct DISP2 pixel clock type clk: imx: drop duplicated macro clk: imx: clk-gpr-mux: Provide clock name in error message clk: imx: Let IMX8MN_CLK_DISP_PIXEL set parent rate clk: imx8mm: Let IMX8MM_CLK_LCDIF_PIXEL set parent rate ...
2023-04-12clk: qcom: rpm: Use managed `of_clk_add_hw_provider()`Lars-Peter Clausen1-8/+2
Use the managed `devm_of_clk_add_hw_provider()` instead of `of_clk_add_hw_provider()`. This makes sure the provider gets automatically removed on unbind and allows to completely eliminate the drivers `remove()` callback. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230410014502.27929-7-lars@metafoo.de
2023-04-11clk: mediatek: fhctl: Mark local variables staticTom Rix1-2/+2
smatch reports drivers/clk/mediatek/clk-fhctl.c:17:27: warning: symbol 'fhctl_offset_v1' was not declared. Should it be static? drivers/clk/mediatek/clk-fhctl.c:30:27: warning: symbol 'fhctl_offset_v2' was not declared. Should it be static? These variables are only used in one file so should be static. Signed-off-by: Tom Rix <trix@redhat.com> Link: https://lore.kernel.org/r/20230406010935.1944976-1-trix@redhat.com Fixes: 8da312d6574c ("clk: mediatek: fhctl: Add support for older fhctl register layout") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-04-10clk: sifive: make SiFive clk drivers depend on ARCH_ symbolsConor Dooley1-3/+3
As part of converting RISC-V SOC_FOO symbols to ARCH_FOO to match the use of such symbols on other architectures, convert the SiFive clk drivers to use the new symbol. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230406-groovy-trustable-15853ac0a130@spud Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-04-10clk: uniphier: Use managed `of_clk_add_hw_provider()`Lars-Peter Clausen1-8/+2
Use the managed `devm_of_clk_add_hw_provider()` instead of `of_clk_add_hw_provider()`. This makes sure the provider gets automatically removed on unbind and allows to completely eliminate the drivers `remove()` callback. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20230410014502.27929-11-lars@metafoo.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-04-10clk: si5351: Use managed `of_clk_add_hw_provider()`Lars-Peter Clausen1-8/+2
Use the managed `devm_of_clk_add_hw_provider()` instead of `of_clk_add_hw_provider()`. This makes sure the provider gets automatically removed on unbind and allows to completely eliminate the drivers `remove()` callback. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20230410014502.27929-10-lars@metafoo.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-04-10clk: si570: Use managed `of_clk_add_hw_provider()`Lars-Peter Clausen1-11/+3
Use the managed `devm_of_clk_add_hw_provider()` instead of `of_clk_add_hw_provider()`. This makes sure the provider gets automatically removed on unbind and allows to completely eliminate the drivers `remove()` callback. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20230410014502.27929-9-lars@metafoo.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-04-10clk: si514: Use managed `of_clk_add_hw_provider()`Lars-Peter Clausen1-8/+2
Use the managed `devm_of_clk_add_hw_provider()` instead of `of_clk_add_hw_provider()`. This makes sure the provider gets automatically removed on unbind and allows to completely eliminate the drivers `remove()` callback. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20230410014502.27929-8-lars@metafoo.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-04-10clk: lmk04832: Use managed `of_clk_add_hw_provider()`Lars-Peter Clausen1-3/+2
Use the managed `devm_of_clk_add_hw_provider()` instead of `of_clk_add_hw_provider()`. This makes sure the provider gets automatically removed on unbind. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20230410014502.27929-6-lars@metafoo.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-04-10clk: hsdk-pll: Use managed `of_clk_add_hw_provider()`Lars-Peter Clausen1-8/+2
Use the managed `devm_of_clk_add_hw_provider()` instead of `of_clk_add_hw_provider()`. This makes sure the provider gets automatically removed on unbind and allows to completely eliminate the drivers `remove()` callback. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20230410014502.27929-5-lars@metafoo.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-04-10clk: cdce706: Use managed `of_clk_add_hw_provider()`Lars-Peter Clausen1-9/+2
Use the managed `devm_of_clk_add_hw_provider()` instead of `of_clk_add_hw_provider()`. This makes sure the provider gets automatically removed on unbind and allows to completely eliminate the drivers `remove()` callback. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20230410014502.27929-4-lars@metafoo.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-04-10clk: axs10x: Use managed `of_clk_add_hw_provider()`Lars-Peter Clausen1-8/+2
Use the managed `devm_of_clk_add_hw_provider()` instead of `of_clk_add_hw_provider()`. This makes sure the provider gets automatically removed on unbind and allows to completely eliminate the drivers `remove()` callback. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20230410014502.27929-3-lars@metafoo.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-04-10clk: axm5516: Use managed `of_clk_add_hw_provider()`Lars-Peter Clausen1-7/+1
Use the managed `devm_of_clk_add_hw_provider()` instead of `of_clk_add_hw_provider()`. This makes sure the provider gets automatically removed on unbind and allows to completely eliminate the drivers `remove()` callback. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20230410014502.27929-2-lars@metafoo.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-04-10clk: axi-clkgen: Use managed `of_clk_add_hw_provider()`Lars-Peter Clausen1-8/+2
Use the managed `devm_of_clk_add_hw_provider()` instead of `of_clk_add_hw_provider()`. This makes sure the provider gets automatically removed on unbind and allows to completely eliminate the drivers `remove()` callback. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20230410014502.27929-1-lars@metafoo.de Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-04-10Merge tag 'renesas-clk-for-v6.4-tag2' of ↵Stephen Boyd1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull one more Renesas clk driver update from Geert Uytterhoeven: - Add I2C5 clock on R-Car V3H * tag 'renesas-clk-for-v6.4-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a77980: Add I2C5 clock
2023-04-09clk: imx: imx8ulp: update clk flag for system critical clockJacky Bai1-7/+7
In order to support bus fabric clock frequency changed on the fly, need to update some bus clocks'flags to make sure these clocks'frequency and parent can be changed on the fly. For these clocks, HW can make sure no glitch will be introduced when changing on the fly. In order to support DDR DFS, the HW register bit for DDR_SEL and DDR_DIV clock will be modified by TF-A. So need to update these two clock's flag to make sure that the linux kernel side can correct these clocks' SW state to reflect the actual HW state. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230331063814.2462059-6-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-09clk: imx: imx8ulp: Add tpm5 clock as critical gate clockJacky Bai1-1/+1
The TPM5 is used for broadcast timer purpose and registered with TIMER_OF_DECLARE. As the clock driver is not ready at that stage, so the TPM5 clock is configured in bootloader(TF-A). if we just remove the TPM5 clock from linux will introduce a risk that the TPM5's parent clock will be gated, then lead to TPM's channel control config can NOT be written into register successfully. Due to the above reason, we still need to add the TPM5 clock into linux clock but register it as a simple critical gate clock to make sure its parent is always on. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230331063814.2462059-5-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-09clk: imx: imx8ulp: keep MU0_B clock enabled alwaysJacky Bai1-1/+1
Keep the A35<->M33 MU0_B clock enabled always for low power communication. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230331063814.2462059-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-09clk: imx: imx8ulp: Add divider closest support to get more accurate clock rateJacky Bai2-8/+17
If a divider's parent clock has fractional part, it will hard to round out a more accurate clock rate for this divider, add the 'CLK_DIVIDER_ROUND_CLOSEST' flags for such divider to get a more accurate clock rate. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230331063814.2462059-3-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-09clk: imx: imx8ulp: Fix XBAR_DIVBUS and AD_SLOW clock parentsPeng Fan1-2/+2
XBAR_DIVBUS and AD_SLOW should set parent to XBAR_AD_DIVPLAT and XBAR_DIVBUS respectively, not the NIC_AD. otherwise we will get wrong clock rate. Fixes: c43a801a5789 ("clk: imx: Add clock driver for imx8ulp") Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230331063814.2462059-2-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-09clk: imx: imx93: Add nic and A55 clkPeng Fan1-2/+15
The A55 clock logic as below: A55_PLL ----------------->\ A55_SEL-->A55_CORE A55_CCM_ROOT--->A55_GATE->/ Add A55 CPU clk to support freq change. Add NIC CLK to reflect the clk status Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-8-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-09dt-bindings: clock: imx93: add NIC, A55 and ARM PLL CLKPeng Fan1-1/+5
Add i.MX93 NIC, A55 and ARM PLL CLK. Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-7-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-09clk: imx: imx93: add mcore_booted module paratemterPeng Fan2-1/+9
Add mcore_booted boot parameter which could simplify AMP clock management. To i.MX93, there is CCM(clock control Module) to generate clock root clock, anatop(analog PLL module) to generate PLL, and LPCG (clock gating) to gate clocks to peripherals. As below: anatop->ccm->lpcg->peripheral Linux handles the clock management and the auxiliary core is under control of Linux. Although there is per hardware domain control for LPCG and CCM, auxiliary core normally only use LPCG hardware domain control to avoid linux gate off the clk to peripherals and leave CCM ana anatop to Linux. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-6-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-09clk: imx: fracn-gppll: Add 300MHz freq support for imx9Jacky Bai1-1/+2
Add 300MHz frequency config support on i.MX93 PLL. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-5-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-09clk: imx: fracn-gppll: support integer pllPeng Fan2-7/+68
The fracn gppll could be configured in FRAC or INTEGER mode during hardware design. The current driver only support FRAC mode, while this patch introduces INTEGER support. When the PLL is INTEGER pll, there is no mfn, mfd, the calculation is as below: Fvco_clk = (Fref / DIV[RDIV] ) * DIV[MFI] Fclko_odiv = Fvco_clk / DIV[ODIV] In this patch, we reuse the FRAC pll logic with some condition check to simplify the driver Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-09clk: imx: fracn-gppll: disable hardware select controlPeng Fan1-0/+6
When programming PLL, should disable Hardware control select to make PLL controlled by register, not hardware inputs through OSCPLL. Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-3-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-09clk: imx: fracn-gppll: fix the rate tablePeng Fan1-7/+9
The Fvco should be range 2.4GHz to 5GHz, the original table voilate the spec, so update the table to fix it. Fixes: c196175acdd3 ("clk: imx: clk-fracn-gppll: Add more freq config for video pll") Fixes: 044034efbeea ("clk: imx: clk-fracn-gppll: fix mfd value") Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-2-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-09clk: imx: imx8mp: change the 'nand_usdhc_bus' clock to non-criticalHaibo Chen1-1/+1
The 'nand_usdhc_bus' clock is only need to be enabled when usdhc or nand module is active, so change it to non-critical clock type. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20230403094633.3366446-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-09clk: imx: imx8mp: Add LDB root clockLiu Ying1-0/+1
This patch adds "media_ldb_root_clk" clock for the LDB in the MEDIAMIX subsystem. Reviewed-by: Sandor Yu <Sandor.yu@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20230403094633.3366446-3-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2023-04-09dt-bindings: clock: imx8mp: Add LDB clock entryPeng Fan1-2/+2
Add LDB clock entry for i.MX8MP Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403094633.3366446-2-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-02 18:43:31 +0300