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2022-06-22drm/amdgpu: Remove break for VMID loop TLB flush on MESGraham Sider2-2/+2
Loop through all VMIDs for gmc_v10_0_flush_gpu_tlb_pasid and gmc_v11_0_flush_gpu_tlb_pasid (only if using MES for gmc_v10). This is required for MES due to use_different_vmid_compute causing SDMA queues to be assigned different VMIDs than compute for the same PASID. Signed-off-by: Graham Sider <Graham.Sider@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-22drm/amdgpu/vcn: adjust unified queue code formatRuijing Dong2-10/+10
Fixed some errors and warnings found by checkpatch.pl. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Ruijing Dong <ruijing.dong@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-22drm/amdgpu/vcn: support unified queue only in vcn4Ruijing Dong1-423/+140
- remove multiple queue support - add unified queue related functions Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Ruijing Dong <ruijing.dong@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-22drm/amdgpu/vcn: add unified queue ib testRuijing Dong2-3/+100
- add unified queue headers - add unified queue ib tests Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Ruijing Dong <ruijing.dong@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amd/display: Drop unnecessary guard from DC resourceRodrigo Siqueira1-2/+0
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amdgpu/display: make FP handling in Makefiles consistentAlex Deucher6-12/+16
Use the same pattern as the DML Makefile and while we are here add a missing x86 guard around the msse flags for DCN3.2.x. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15Revert "drm/amdgpu/display: Protect some functions with CONFIG_DRM_AMD_DC_DCN"Alex Deucher1-4/+0
This reverts commit d8e4fb9112e88d8d87ffbc38fa511e7118042d4f. This is no longer necessary as newer patches require these functions without CONFIG_DRM_AMD_DC_DCN. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amdkfd: fix warning when CONFIG_HSA_AMD_P2P is not setAlex Deucher1-2/+5
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.c:1542:11: warning: variable 'i' set but not used [-Wunused-but-set-variable] Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amdgpu: remove redundant enable_mes and enable_mes_kiqYifan Zhang1-8/+0
enable_mes and enable_mes_kiq are set in both device init and MES IP init. Leave the ones in MES IP init, since it is a more accurate way to judge from GC IP version. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amd/display: Blank for uclk OC in dm instead of dcJoshua Aberback2-30/+14
[Why] All displays need to be blanked during the uclk OC interface so that we can guarantee pstate switching support. If the display config doesn't support pstate switching, only using core_link_disable_stream will not enable it as the front-end is untouched. We need to go through the full plane removal sequence to properly program the pipe to allow pstate switching. [How] - guard clk_mgr functions with non-NULL checks Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amd/display: Add null check to dc_submit_i2c_oemMartin Leung1-4/+7
[why] dc_submit_i2c_oem could be called with ddc null [how] add null check and fail the call instead Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Martin Leung <martin.leung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amd/display: FVA timing adjustmentCharlene Liu1-0/+1
[why] need to add timing adjustment for fva. [how] add hook to optc and hwseq. Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amd/display: Add vrr_active_variable to dc_stream_updateHarry VanZyllDeJong4-3/+6
[WHY] The display driver on some OSes need to track it in order to perform memory clock switching decisions. [HOW] Propagate the vrr active state to dirty bit so that on mode set it disables dynamic memory clock switching. Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Harry VanZyllDeJong <harry.vanzylldejong@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amd/display: Pass vrr mode to dcnFelipe Clark1-0/+1
[WHY] New features will require knowing the vrr mode for their enablement. [HOW] Pass the state via a member of dc_stream. Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Felipe Clark <Felipe.Clark@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amd/display: Adding VTEM to dcAhmad Othman6-2/+23
[Why] Video Timing Extended Metadata packet (VTEM) is required for features like VRR and FVA [How] Adding support for VTEM transmission to stream encoders in DCN20 and DCN30 as part of FVA support Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Ahmad Othman <ahmad.othman@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amd/display: Copy hfvsif_infopacket when stream updateNicholas Kazlauskas1-0/+3
[Why & How] Miss to copy hfvsif_infopacket when copying stream updates. Check and copy it. Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amd/display: Add support for HF-VSIFAhmad Othman4-4/+20
[Why] - Currently there is no support for HF-VSIF - The current support of VSIF is limited to H14b infoframe [How] - refactor VSIF - Added new builder for HF-VSIF - Added the HF-VSIF packet to DisplayTarget - Updates DC to apply HF-VSIF updates when updating streams Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Ahmad Othman <ahmad.othman@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amd/display: Firmware assisted MCLK switch and FSFelipe Clark14-22/+51
[WHY] Memory clock switching has great potential for power savings. [HOW] The driver code was modified to notify the DMCUB firmware that it should stretch the vertical blank of frames when a memory clock switch is about to start so that no blackouts happen on the screen due to unavailability of the frame buffer. The driver logic to determine when such firmware assisted strategy can be initiated is also implemented and consists on checking prerequisites of the feature. Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Felipe Clark <felipe.clark@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amd/display: DAL ACR, dc part, fix missing dcn30Ian Chen2-8/+25
[Why] - missing in dcn30 function - Fix a divide by 0 when ACR trigger [How] - Add IS_SMU_TIMEOUT() to dcn30_smu_send_msg_with_param - Add zero check in dcn20_update_clocks_update_dentist Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Ian Chen <ian.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amd/display: Fix commentsSamson Tam5-25/+37
[Why & how] Fix format and typo of comments. Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Samson Tam <Samson.Tam@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amd/display: Drop unused privacy_mask setters and gettersOliver Logush1-6/+0
[Why and How] dwbc_funcs.set/get_privacy_mask isn't being used anymore, drop it Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Oliver Logush <oliver.logush@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amd/display: 3.2.190Aric Cyr1-1/+1
This version brings along the following: - DP fixes - Exiting idle optimizations on mouse updates Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amd/display: update topology_update_input_v3 structQingqing Zhuo3-0/+17
[Why] DIO parameters were missing in topology_update_intput_v3 struct. [How] Add DIO parameters in v3 struct and update in functions perspectively. Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amd/display: Add debug option for exiting idle optimizations on cursor ↵Alvin Lee2-2/+4
updates [Description] - Have option to exit idle opt on cursor updates for debug and optimizations purposes Reviewed-by: Samson Tam <Samson.Tam@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amd/display: dsc validate fail not pass to atomic checkhersen wu3-16/+35
[Why] when 4k@144hz dp connect to dp1.4 dsc mst hub, requested bandwidth exceeds caps of dsc hub. but dsc bw valid functions, increase_dsc_bpp, try_disable_dsc, pre_validate_dsc, compute_mst_dsc_configs_for_state, do not return false to atomic check. this cause user mode initiate mode set to kernel, then cause kernel assert, system hang. [How] dsc bandwidth valid functions return pass or fail to atomic check. Reviewed-by: Wayne Lin <Wayne.Lin@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: hersen wu <hersenxs.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amd/display: Fix monitor flash issueShah Dharati1-1/+1
[Why & How] For a some specific monitors, when connected on boot or hot plug, monitor flash for 1/2 seconds can happen during first HDCP query operation. Ading some delay in the init sequence for these monitors fixes the issue, so it is implemented as monitor specific patch. Co-authored-by: Shah Dharati <dharshah@amd.com> Reviewed-by: Hansen Dsouza <Hansen.Dsouza@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Shah Dharati <dharshah@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amd/display: lower lane count first when CR done partially fails in EQWenjing Liu2-6/+9
[why] According to DP specs, in EQ DONE phase of link training, we should lower lane count when at least one CR DONE bit is set to 1, while lower link rate when all CR DONE bits are 0s. However in our code, we will treat both cases as latter. This is not exactly correct based on the specs expectation. [how] Check lane0 CR DONE bit when it is still set but CR DONE fails, we treat it as a partial CR DONE failure in EQ DONE phase, we will follow the same fallback flow as when ED DONE fails in EQ DONE phase. Reviewed-by: George Shen <George.Shen@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amdkfd: Add available memory ioctlDaniel Phillips4-6/+81
Add a new KFD ioctl to return the largest possible memory size that can be allocated as a buffer object using kfd_ioctl_alloc_memory_of_gpu. It attempts to use exactly the same accept/reject criteria as that function so that allocating a new buffer object of the size returned by this new ioctl is guaranteed to succeed, barring races with other allocating tasks. This IOCTL will be used by libhsakmt: https://www.mail-archive.com/amd-gfx@lists.freedesktop.org/msg75743.html Signed-off-by: Daniel Phillips <Daniel.Phillips@amd.com> Signed-off-by: David Yat Sin <David.YatSin@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15Revert "drm/amdgpu/gmc11: enable AGP aperture"Chengming Gui4-11/+9
This reverts commit 2cfe34e18970d26bff73c63f16c76dae22138d19. Enable AGP aperture cause SDMA page fault for gfx11.0.2, so temp disable AGP aperture until SDMA FW resolved this. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Gui <Jack.Gui@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amd/pm: enable MACO support for SMU 13.0.0Evan Quan3-51/+7
Enable BAMACO reset support for SMU 13.0.0. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amd/pm: enable UCLK DS feature for SMU 13.0.0Evan Quan1-0/+2
The feature is ready with latest PMFW and IFWI. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amd/display: dml: move some variables to heapAurabindo Pillai2-10/+10
[Why&How] To reduce stack usage, move some variables into heap in the DML function dml32_ModeSupportAndSystemConfigurationFull() Fixes: dda4fb85e433 ("drm/amd/display: DML changes for DCN32/321") Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amd/display: Use pre-allocated temp struct for bounding box updateLeo Li4-56/+82
[Why] There is a theoretical problem in prior patches for reducing the stack size of *update_bw_bounding_box() functions. By modifying the soc.clock_limits[n] struct directly, this can cause unintended behavior as the for loop attempts to swap rows in clock_limits[n]. A temporary struct is still required to make sure we stay functinoally equivalent. [How] Add a temporary clock_limits table to the SOC struct, and use it when swapping rows. Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amdgpu: Fix GTT size reporting in amdgpu_ioctlMichel Dänzer1-2/+0
The commit below changed the TTM manager size unit from pages to bytes, but failed to adjust the corresponding calculations in amdgpu_ioctl. Fixes: dfa714b88eb0 ("drm/amdgpu: remove GTT accounting v2") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1930 Bug: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6642 Tested-by: Martin Roukala <martin.roukala@mupuf.org> Tested-by: Mike Lothian <mike@fireburn.co.uk> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <mdaenzer@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amdgpu/pm: remove the repeated EnableGfxImu message sendingTim Huang1-9/+4
The EnableGfxImu message will be issued in the set_gfx_power_up_by_imu. Signed-off-by: Tim Huang <tim.huang@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amdgpu/pm: correct the firmware flag address for SMU IP v13.0.4Tim Huang2-2/+11
For SMU IP v13.0.4, the smnMP1_FIRMWARE_FLAGS address is different, we need this to correct the reading address. Signed-off-by: Tim Huang <tim.huang@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amd/display: ignore modifiers when checking for format supportAurabindo Pillai1-7/+46
[Why&How] There are cases where swizzle modes are set but modifiers arent. For such a userspace, we need not check modifiers while checking compatibilty in the drm hook for checking plane format. Ignore checking modifiers but check the DCN generation for the supported swizzle mode. v2: squash in unused variable removal (Alex) Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amd: disable GPA mode in backdoor loadYifan Zhang1-0/+3
GPA mode should be disabled in direct load. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amdgpu/discovery: enable vcn/jpeg v4_0_2Yifan Zhang1-0/+1
Enable vcn/jpeg 4_0_2. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Tim Huang <Tim.Huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-15drm/amd/pm: fix driver reload SMC firmware fail issue for smu13Yang Wang3-0/+11
issue calltrace: [ 402.773695] [drm] failed to load ucode SMC(0x2C) [ 402.773754] [drm] psp gfx command LOAD_IP_FW(0x6) failed and response status is (0x0) [ 402.773762] [drm:psp_load_smu_fw [amdgpu]] *ERROR* PSP load smu failed! [ 402.966758] [drm:psp_v13_0_ring_destroy [amdgpu]] *ERROR* Fail to stop psp ring [ 402.966949] [drm:psp_hw_init [amdgpu]] *ERROR* PSP firmware loading failed [ 402.967116] [drm:amdgpu_device_fw_loading [amdgpu]] *ERROR* hw_init of IP block <psp> failed -22 [ 402.967252] amdgpu 0000:03:00.0: amdgpu: amdgpu_device_ip_init failed [ 402.967255] amdgpu 0000:03:00.0: amdgpu: Fatal error during GPU init if not reset mp1 state during kernel driver unload, it will cause psp load pmfw fail at the second time. add PPSMC_MSG_PrepareMp1ForUnload support for smu_v13_0_0/smu_v13_0_7 Signed-off-by: Yang Wang <KevinYang.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-10drm/amd/pm: support BAMACO reset on smu_v13_0_7Kenneth Feng2-2/+56
support BAMACO reset on smu_v13_0_7, take BAMACO as a subset of BACO for the low latency, and it only happens on specific platforms. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-10drm/amd/pm: enable gfxoff on smu_v13_0_7Kenneth Feng1-0/+3
enable gfxoff on smu_v13_0_7 Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-10drm/amd/pm: update the driver if header for smu_v13_0_7Kenneth Feng2-19/+45
update the driver if header for smu_v13_0_7 Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-10drm/amdgpu: Stop any pending reset if another in progress.Andrey Grodzovsky1-0/+27
We skip rest requests if another one is already in progress. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-10drm/amdgpu: Rename amdgpu_device_gpu_recover_imp back to ↵Andrey Grodzovsky9-9/+9
amdgpu_device_gpu_recover We removed the wrapper that was queueing the recover function into reset domain queue who was using this name. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-10drm/amdgpu: Add work_struct for GPU reset from kfd.Andrey Grodzovsky3-32/+15
We need to have a work_struct to cancel this reset if another already in progress. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-10drm/amdgpu: Add work_struct for GPU reset from debugfsAndrey Grodzovsky2-2/+19
We need to have a work_struct to cancel this reset if another already in progress. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-10drm/admgpu: Serialize RAS recovery work directly into reset domain queue.Andrey Grodzovsky1-2/+4
Save the extra usless work schedule. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-10drm/amdgpu: Cache result of last reset at reset domain level.Andrey Grodzovsky3-2/+6
Will be read by executors of async reset like debugfs. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-06-10Revert "workqueue: remove unused cancel_work()"Andrey Grodzovsky2-0/+10
This reverts commit 6417250d3f894e66a68ba1cd93676143f2376a6f. amdpgu need this function in order to prematurly stop pending reset works when another reset work already in progress. Acked-by: Tejun Heo <tj@kernel.org> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Lai Jiangshan<jiangshanlai@gmail.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-29 00:28:38 +0300