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2017-09-07Merge branch 'pci/host-mediatek' into nextBjorn Helgaas4-200/+975
* pci/host-mediatek: PCI: mediatek: Use PCI_NUM_INTX PCI: mediatek: Add MSI support for MT2712 and MT7622 PCI: mediatek: Use bus->sysdata to get host private data dt-bindings: PCI: Add support for MT2712 and MT7622 PCI: mediatek: Add controller support for MT2712 and MT7622 dt-bindings: PCI: Cleanup MediaTek binding text dt-bindings: PCI: Rename MediaTek binding PCI: mediatek: Switch to use platform_get_resource_byname() PCI: mediatek: Add a structure to abstract the controller generations PCI: mediatek: Rename port->index and mtk_pcie_parse_ports() PCI: mediatek: Use readl_poll_timeout() to wait for Gen2 training PCI: mediatek: Explicitly request exclusive reset control
2017-09-07Merge branch 'pci/host-layerscape' into nextBjorn Helgaas5-49/+92
* pci/host-layerscape: PCI: layerscape: Add support for ls1088a PCI: layerscape: Add support for ls2088a PCI: artpec6: Stop enabling writes to DBI read-only registers PCI: layerscape: Remove unnecessary class code fixup PCI: dwc: Enable write permission for Class Code, Interrupt Pin updates PCI: dwc: Add accessors for write permission of DBI read-only registers PCI: layerscape: Disable outbound windows configured by bootloader PCI: layerscape: Refactor ls1021_pcie_host_init() PCI: layerscape: Move generic init functions earlier in file PCI: layerscape: Add class code and multifunction fixups for ls1021a PCI: layerscape: Move STRFMR1 access out from the DBI write-enable bracket PCI: layerscape: Call dw_pcie_setup_rc() from ls_pcie_host_init()
2017-09-07Merge branch 'pci/host-kirin' into nextBjorn Helgaas1-1/+1
* pci/host-kirin: PCI: kirin: Constify dw_pcie_host_ops structure
2017-09-07Merge branch 'pci/host-keystone' into nextBjorn Helgaas3-18/+4
* pci/host-keystone: PCI: keystone: Use PCI_NUM_INTX PCI: keystone: Remove duplicate MAX_*_IRQS defs PCI: keystone-dw: Remove unused ks_pcie, pci variables
2017-09-07Merge branch 'pci/host-iproc' into nextBjorn Helgaas4-152/+259
* pci/host-iproc: PCI: iproc: Clean up whitespace PCI: iproc: Rename PCI_EXP_CAP to IPROC_PCI_EXP_CAP PCI: iproc: Add 500ms delay during device shutdown PCI: iproc: Work around Stingray CRS defects PCI: iproc: Factor out memory-mapped config access address calculation PCI: iproc: Remove unused struct iproc_pcie *pcie
2017-09-07Merge branch 'pci/host-imx6' into nextBjorn Helgaas1-3/+4
* pci/host-imx6: PCI: imx6: Explicitly request exclusive reset control
2017-09-07Merge branch 'pci/host-hv' into nextBjorn Helgaas1-1/+7
* pci/host-hv: PCI: hv: Do not sleep in compose_msi_msg()
2017-09-07Merge branch 'pci/host-hisi' into nextBjorn Helgaas1-4/+1
* pci/host-hisi: PCI: hisi: Constify dw_pcie_host_ops structure PCI: hisi: Remove unused variable driver
2017-09-07Merge branch 'pci/host-faraday' into nextBjorn Helgaas1-3/+3
* pci/host-faraday: PCI: faraday: Use PCI_NUM_INTX PCI: faraday: Fix of_irq_get() error check
2017-09-07Merge branch 'pci/host-exynos' into nextBjorn Helgaas1-4/+4
* pci/host-exynos: PCI: exynos: Fix platform_get_irq() error handling
2017-09-07Merge branch 'pci/host-dra7xx' into nextBjorn Helgaas1-4/+4
* pci/host-dra7xx: PCI: dra7xx: Fix platform_get_irq() error handling PCI: dra7xx: Propagate platform_get_irq() errors in dra7xx_pcie_probe() PCI: dra7xx: Use PCI_NUM_INTX
2017-09-07Merge branch 'pci/host-designware' into nextBjorn Helgaas14-28/+73
* pci/host-designware: PCI: dwc: Clear MSI interrupt status after it is handled, not before PCI: qcom: Allow ->post_init() to fail PCI: qcom: Don't unroll init if ->init() fails PCI: dwc: designware: Handle ->host_init() failures PCI: dwc: designware: Test PCIE_ATU_ENABLE bit specifically PCI: dwc: designware: Make dw_pcie_prog_*_atu_unroll() static
2017-09-07Merge branch 'pci/host-artpec6' into nextBjorn Helgaas1-2/+2
* pci/host-artpec6: PCI: artpec6: Fix platform_get_irq() error handling
2017-09-07Merge branch 'pci/host-armada' into nextBjorn Helgaas1-3/+5
* pci/host-armada: PCI: armada8k: Fix platform_get_irq() error handling PCI: armada8k: Check the return value from clk_prepare_enable()
2017-09-07Merge branch 'pci/host-altera' into nextBjorn Helgaas2-11/+8
* pci/host-altera: PCI: altera: Fix platform_get_irq() error handling PCI: altera: Use size=4 IRQ domain for legacy INTx PCI: altera: Remove unused num_of_vectors variable
2017-09-07Merge branch 'pci/host-aardvark' into nextBjorn Helgaas1-3/+2
* pci/host-aardvark: PCI: aardvark: Use PCI_NUM_INTX
2017-09-07Merge branch 'pci/irq-intx' into nextBjorn Helgaas2-8/+55
* pci/irq-intx: PCI: Add pci_irqd_intx_xlate() PCI: Move enum pci_interrupt_pin to linux/pci.h
2017-09-05PCI: altera: Fix platform_get_irq() error handlingFabio Estevam2-4/+4
platform_get_irq() returns a negative number on failure, so adjust the logic to detect such condition and propagate the real error value on failure. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Ley Foon Tan <lftan@altera.com>
2017-09-05PCI: artpec6: Fix platform_get_irq() error handlingFabio Estevam1-2/+2
platform_get_irq() returns a negative number on failure, so adjust the logic to detect such condition and propagate the real error value on failure. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Niklas Cassel <niklas.cassel@axis.com>
2017-09-05PCI: armada8k: Fix platform_get_irq() error handlingFabio Estevam1-2/+2
platform_get_irq() returns a negative number on failure, so adjust the logic to detect such condition and propagate the real error value on failure. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2017-09-05PCI: dra7xx: Fix platform_get_irq() error handlingFabio Estevam1-1/+1
When platform_get_irq() fails we should propagate the real error value instead of always returning -EINVAL. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-09-05PCI: exynos: Fix platform_get_irq() error handlingFabio Estevam1-4/+4
platform_get_irq() returns a negative number on failure, so adjust the logic to detect such condition and propagate the real error value on failure. Reported-by: Bjorn Helgaas <helgaas@kernel.org> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jingoohan1@gmail.com>
2017-09-05PCI: iproc: Clean up whitespaceBjorn Helgaas1-116/+115
Use tabs (not spaces) for indentation. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-09-05PCI: iproc: Rename PCI_EXP_CAP to IPROC_PCI_EXP_CAPBjorn Helgaas1-10/+9
PCI_EXP_CAP is an iProc-specific value, so rename it to IPROC_PCI_EXP_CAP to make it obvious that it's not related to the generic values like PCI_EXP_RTCTL, etc. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-09-05PCI: iproc: Add 500ms delay during device shutdownOza Pawandeep3-15/+33
During soft reset (e.g., "reboot" from Linux) on some iProc-based SOCs, the LCPLL clock and PERST both go off simultaneously. This seems in accordance with the PCIe Card Electromechanical spec, r2.0, sec 2.2.3, which says the clock goes inactive after PERST# goes active, but doesn't specify how long the clock should be valid after PERST#. However, we have observed that with the iProc Stingray, some Intel NVMe endpoints, e.g., the P3700 400GB series, are not detected correctly upon the next boot sequence unless the clock remains valid for some time after PERST# is asserted. Delay 500ms after asserting PERST# before performing a reboot. The 500ms is experimentally determined. Signed-off-by: Oza Pawandeep <oza.oza@broadcom.com> [bhelgaas: changelog, add spec reference, fold in iproc_pcie_shutdown() export from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com>
2017-08-30PCI: mediatek: Use PCI_NUM_INTXHonghui Zhang1-3/+2
Switch from using custom INTX_NUM macro to the generic PCI_NUM_INTX definition for the number of INTx interrupts. Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> [bhelgaas: use subject/changelog from similar patches] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-30PCI: mediatek: Add MSI support for MT2712 and MT7622Honghui Zhang1-1/+155
MT2712 and MT7622's PCIe host controller support MSI, but only 32-bit MSI addresses are supported. It connects to GIC with the same IRQ number as the INTx IRQ, so it shares the same IRQ with INTx IRQ. Add MSI support for MT2712 and MT7622. Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> [bhelgaas: changes to follow rcar & tegra: rename to mtk_pcie_msi_alloc(), add mtk_pcie_msi_free(), free hwirq if irq_create_mapping() fails, call irq_dispose_mapping() from mtk_msi_teardown_irq()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Ryder Lee <ryder.lee@mediatek.com>
2017-08-30PCI: mediatek: Use bus->sysdata to get host private dataHonghui Zhang1-2/+1
75983c6d1f38 ("PCI: mediatek: Add controller support for MT2712 and MT7622") has put the mtk_pcie * into bus->sysdata. Take advantage of that to get the private data and simplify the code. Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Ryder Lee <ryder.lee@mediatek.com>
2017-08-30dt-bindings: PCI: Add support for MT2712 and MT7622Ryder Lee1-7/+161
Add controller support for MT2712/MT7622 and update related properties. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org>
2017-08-30PCI: mediatek: Add controller support for MT2712 and MT7622Ryder Lee2-7/+460
MT2712 and MT7622 using a new IP block of Gen2 controller which has two root ports and shares the same probing flow with MT2701/MT7623. Both MT2712 and MT7622 have the same per-port control registers, but there are slight differences between them: - MT7622 has more clocks than MT2712. - MT7622 has shared control registers which are used to enable LTSSM and ASPM while MT2712 does not. Add host controller support for MT2712/MT7622. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> [bhelgaas: folded in fix from http://lkml.kernel.org/r/1502715868-17651-2-git-send-email-honghui.zhang@mediatek.com] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-30dt-bindings: PCI: Cleanup MediaTek binding textRyder Lee1-16/+16
To accommodate other SoC generations, regroup specific properties by SoC, and remove redundant descriptions. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> [bhelgaas: split into a rename patch and a cleanup patch] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org>
2017-08-30dt-bindings: PCI: Rename MediaTek bindingRyder Lee1-0/+0
To accommodate other SoC generations, rename mediatek,mt7623-pcie.txt to mediatek-pcie.txt. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> [bhelgaas: split rename to separate patch so updates are obvious] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org>
2017-08-30PCI: mediatek: Switch to use platform_get_resource_byname()Ryder Lee1-7/+10
This is a transitional patch. We currently use platfarm_get_resource() for retrieving the IOMEM resources, but there might be some chips don't have subsys/shared registers part, which depends on platform design, and these will be introduced in further patches. Switch this function to use the platform_get_resource_byname() so that the binding can be agnostic of the resource order. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-30PCI: mediatek: Add a structure to abstract the controller generationsHonghui Zhang1-5/+26
Introduce a structure "mtk_pcie_soc" to abstract the differences between controller generations, and the .startup() hook is used to encapsulate some SoC-dependent related setting. In doing so, the common code which will be reused by future chips. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-30PCI: mediatek: Rename port->index and mtk_pcie_parse_ports()Honghui Zhang1-25/+25
Rename "port->index" to "port->slot" since the ports are hardwired at PCI_SLOT. Also rename "mtk_pcie_parse_ports()" to "mtk_pcie_parse_port()" since it parses one port each time. No functional change in this patch. Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-30PCI: mediatek: Use readl_poll_timeout() to wait for Gen2 trainingRyder Lee1-30/+22
Wait for Gen2 training with readl_poll_timeout(), and simplify the hardware assert logical by merging it into a new mtk_pcie_startup_port() interface. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2017-08-30PCI: mediatek: Explicitly request exclusive reset controlPhilipp Zabel1-1/+1
Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting reset lines") started to transition the reset control request API calls to explicitly state whether the driver needs exclusive or shared reset control behavior. Convert all drivers requesting exclusive resets to the explicit API call so the temporary transition helpers can be removed. No functional changes. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Ryder Lee <ryder.lee@mediatek.com> Cc: Matthias Brugger <matthias.bgg@gmail.com>
2017-08-30PCI: layerscape: Add support for ls1088aHou Zhiqiang2-0/+2
Add support for ls1088a. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>
2017-08-30PCI: layerscape: Add support for ls2088aHou Zhiqiang2-0/+10
The ls2088a PCIe controller's register addresses are different from ls2080a, so add a match entry to identify ls2088a PCIe. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>
2017-08-30PCI: artpec6: Stop enabling writes to DBI read-only registersHou Zhiqiang1-6/+0
Previously we enabled writes to the DBI read-only registers so the Class Code fix in dw_pcie_setup_rc() would work. But now dw_pcie_setup_rc() enables write permission itself, so we don't need to do it here. Stop enabling writes to the DBI read-only registers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-30PCI: layerscape: Remove unnecessary class code fixupHou Zhiqiang1-9/+0
Now that the Class Code fixup in dw_pcie_setup_rc() works, remove the fixup from the Layerscape driver. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-30PCI: dwc: Enable write permission for Class Code, Interrupt Pin updatesHou Zhiqiang1-0/+6
dw_pcie_setup_rc() contains fixes to update the Class Code and Interrupt Pin registers, but the fixes don't actually work because these registers are read-only. Enable write permission before updating the Class Code and Interrupt Pin. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Joao Pinto <jpinto@synopsys.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-30PCI: dwc: Add accessors for write permission of DBI read-only registersHou Zhiqiang2-3/+27
The read-only DBI registers can be written only when the "Write to RO Registers Using DBI" (DBI_RO_WR_EN) field of MISC_CONTROL_1_OFF is set. Add accessors to enable and disable write permission, and use them instead of accessing MISC_CONTROL_1_OFF directly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Joao Pinto <jpinto@synopsys.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-30PCI: layerscape: Disable outbound windows configured by bootloaderHou Zhiqiang1-0/+17
Disable all the outbound windows to avoid one transaction hitting multiple outbound windows. dw_pcie_setup_rc() will reconfigure the outbound windows, which may conflict with windows configured by the bootloader. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-30PCI: layerscape: Refactor ls1021_pcie_host_init()Hou Zhiqiang1-10/+1
ls1021_pcie_host_init() duplicated the code in the generic ls_pcie_host_init(). Call ls_pcie_host_init() instead of duplicating the code. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-29PCI: layerscape: Move generic init functions earlier in fileHou Zhiqiang1-32/+32
We will use the generic ls_pcie_link_up() and ls_pcie_host_init() from device-specific routines. Move the generic functions earlier in the file so we won't need forward declarations. This is strictly a code move with no functional change intended. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-29PCI: layerscape: Add class code and multifunction fixups for ls1021aHou Zhiqiang1-0/+5
The current code depends on class code and multifunction fixups done by the bootloader. Perform these fixups in ls1021_pcie_host_init() to remove this dependency. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-29PCI: layerscape: Move STRFMR1 access out from the DBI write-enable bracketHou Zhiqiang1-1/+2
The STRFMR1 is not a DBI read-only register, so move it out from the write-enable bracket. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-29PCI: layerscape: Call dw_pcie_setup_rc() from ls_pcie_host_init()Hou Zhiqiang1-0/+2
We called dw_pcie_setup_rc() from the ls1021a host init function, but not from the common ls_pcie_host_init() function, so platforms other than ls1021a still depended on initialization by the bootloader. Call dw_pcie_setup_rc() from ls_pcie_host_init() to reduce dependencies on the bootloader. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Roy Zang <tie-fei.zang@freescale.com>
2017-08-29PCI: iproc: Work around Stingray CRS defectsOza Pawandeep1-1/+81
Configuration Request Retry Status ("CRS") completions are a required part of PCIe. A PCIe device may respond to config a request with a CRS completion to indicate that it needs more time to initialize. A Root Port that receives a CRS completion may automatically retry the request, or it may treat the request as a failed transaction. For a failed read, it will likely synthesize all 1's data, i.e., 0xffffffff, to complete the read to the CPU. CRS Software Visibility ("CRS SV") is an optional feature. Per PCIe r3.1, sec 2.3.2, if supported and enabled, a Root Port that receives a CRS completion for a config read of the Vendor ID will synthesize 0x0001 data (an invalid Vendor ID) instead of retrying or failing the transaction. The 0x0001 data makes the CRS completion visible to software, so it can perform other tasks while waiting for the device. The iProc "Stingray" PCIe controller does not support CRS completions correctly. From the Stingray PCIe Controller spec: 4.7.3.3. Retry Status On Configuration Cycle Endpoints are allowed to generate retry status on configuration cycles. In this case, the RC needs to re-issue the request. The IP does not handle this because the number of configuration cycles needed will probably be less than the total number of non-posted operations needed. When a retry status is received on the User RX interface for a configuration request that was sent on the User TX interface, it will be indicated with a completion with the CMPL_STATUS field set to 2=CRS, and the user will have to find the address and data values and send a new transaction on the User TX interface. When the internal configuration space returns a retry status during a configuration cycle (user_cscfg = 1) on the Command/Status interface, the pcie_cscrs will assert with the pcie_csack signal to indicate the CRS status. When the CRS Software Visibility Enable register in the Root Control register is enabled, the IP will return the data value to 0x0001 for the Vendor ID value and 0xffff (all 1’s) for the rest of the data in the request for reads of offset 0 that return with CRS status. This is true for both the User RX Interface and for the Command/Status interface. When CRS Software Visibility is enabled, the CMPL_STATUS field of the completion on the User RX Interface will not be 2=CRS and the pcie_cscrs signal will not assert on the Command/Status interface. The Stingray hardware never reissues configuration requests when it receives CRS completions. Contrary to what sec 4.7.3.3 above says, when it receives a CRS completion, it synthesizes 0xffff0001 data regardless of the address of the read or the value of the CRS SV enable bit. This is broken in two ways: 1) When CRS SV is disabled, the Root Port should never synthesize the 0x0001 value. If it receives a CRS completion, it should fail the transaction and synthesize all 1's data. 2) When CRS SV is enabled, the Root Port should only synthesize 0x0001 data if it receives a CRS completion for a read of the Vendor ID. If it receives a CRS completion for any other read, it should fail the transaction and synthesize all 1's data. This breaks pci_flr_wait(), which reads the Command register and expects to see all 1's data if the read fails because of CRS completions. On Stingray, it sees the incorrect 0xffff0001 data instead. It also breaks config registers that contain the 0xffff0001 value. If we read such a register, software can't distinguish a CRS completion from the actual value read from the device. On Stingray, if we read 0xffff0001 data, assume this indicates a CRS completion and retry the read for 500ms. If we time out, return all 1's (0xffffffff) data. Note that this corrupts registers that happen to contain 0xffff0001. Stingray advertises CRS SV support in its Root Capabilities register, and the CRS SV enable bit is writable (even though the hardware ignores it). Mask out PCI_EXP_RTCAP_CRSVIS so software doesn't try to use CRS SV. Signed-off-by: Oza Pawandeep <oza.oza@broadcom.com> [bhelgaas: changelog, add probe-time warning about corruption, don't advertise CRS SV support, remove duplicate pci_generic_config_read32(), fix alignment based on patch from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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