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2023-06-21mips: pci-mt7620: do not print NFTS register value as error logShiji Yang1-3/+0
These codes are used to read NFTS_TIMEOUT_DELAY register value and write it into kernel log after writing the register. they are only used for debugging during driver development, so there is no need to keep them now. Tested on MT7628AN router Motorola MWR03. Signed-off-by: Shiji Yang <yangshiji66@outlook.com> Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-21MAINTAINERS: add Mediatek MTMIPS Clock maintainerSergio Paracuellos1-0/+6
Adding myself as maintainer for Mediatek MTMIPS clock driver. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-21mips: ralink: get cpu rate from new driver codeSergio Paracuellos1-9/+52
At very early stage on boot, there is a need to set 'mips_hpt_frequency'. This timer frequency is a half of the CPU frequency. To get clocks properly set we need to call to 'of_clk_init()' and properly get cpu clock frequency afterwards. Depending on the SoC, CPU clock index and compatible differs, so use them to get the proper clock frm the clock provider. Hence, adapt code to be aligned with new clock driver. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-21mips: ralink: remove reset related codeSergio Paracuellos3-67/+0
A proper clock driver for ralink SoCs has been added. This driver is also a reset provider for the SoC. Hence there is no need to have reset related code in 'arch/mips/ralink' folder anymore. The only code that remains is the one related with mips_reboot_setup where a PCI reset is performed. We maintain this because I cannot test old ralink board with PCI to be sure all works if we remove also this code. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-21mips: ralink: mt7620: remove clock related codeSergio Paracuellos3-264/+0
A proper clock driver for ralink SoCs has been added. Hence there is no need to have clock related code in 'arch/mips/ralink' folder anymore. Since this is the last clock related code removal, remove also remaining prototypes in 'common.h' header file. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-21mips: ralink: rt3883: remove clock related codeSergio Paracuellos2-52/+0
A properly clock driver for ralink SoCs has been added. Hence there is no need to have clock related code in 'arch/mips/ralink' folder anymore. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-21mips: ralink: rt305x: remove clock related codeSergio Paracuellos2-99/+0
A properly clock driver for ralink SoCs has been added. Hence there is no need to have clock related code in 'arch/mips/ralink' folder anymore. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-21mips: ralink: rt288x: remove clock related codeSergio Paracuellos2-41/+0
A properly clock driver for ralink SoCs has been added. Hence there is no need to have clock related code in 'arch/mips/ralink' folder anymore. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-21clk: ralink: add clock and reset driver for MTMIPS SoCsSergio Paracuellos3-0/+1123
Until now, clock related code for old ralink SoCs was based in fixed clocks using 'clk_register_fixed_rate' and 'clkdev_create' directly doing in code and not using device tree at all for their definition. Including this driver is an effort to be able to define proper clocks using device tree and also cleaning all the clock and reset related code from 'arch/mips/ralink' dir. This clock and reset driver covers all the ralink SoCs but MT7621 which is the newest and provides gating and some differences that make it different from its predecesors. It has its own driver since some time ago. The ralink SoCs we are taking about are RT2880, RT3050, RT3052, RT3350, RT3352, RT3883, RT5350, MT7620, MT7628 and MT7688. Mostly the code in this new driver has been extracted from 'arch/mips/ralink' and cleanly put using kernel clock driver APIs. The clock plans for this SoCs only talks about relation between CPU frequency and BUS frequency. This relation is different depending on the particular SoC. CPU clock is derived from XTAL frequencies. Depending on the SoC we have the following frequencies: * RT2880 SoC: - XTAL: 40 MHz. - CPU: 250, 266, 280 or 300 MHz. - BUS: CPU / 2 MHz. * RT3050, RT3052, RT3350: - XTAL: 40 MHz. - CPU: 320 or 384 MHz. - BUS: CPU / 3 MHz. * RT3352: - XTAL: 40 MHz. - CPU: 384 or 400 MHz. - BUS: CPU / 3 MHz. - PERIPH: 40 MHz. * RT3383: - XTAL: 40 MHz. - CPU: 250, 384, 480 or 500 MHz. - BUS: Depends on RAM Type and CPU: + RAM DDR2: 125. ELSE 83 MHz. + RAM DDR2: 128. ELSE 96 MHz. + RAM DDR2: 160. ELSE 120 MHz. + RAM DDR2: 166. ELSE 125 MHz. * RT5350: - XTAL: 40 MHz. - CPU: 300, 320 or 360 MHz. - BUS: CPU / 3, CPU / 4, CPU / 3 MHz. - PERIPH: 40 MHz. * MT7628 and MT7688: - XTAL: 20 MHz or 40 MHz. - CPU: 575 or 580 MHz. - BUS: CPU / 3. - PCMI2S: 480 MHz. - PERIPH: 40 MHz. * MT7620: - XTAL: 20 MHz or 40 MHz. - PLL: XTAL, 480, 600 MHz. - CPU: depends on PLL and some mult and dividers. - BUS: depends on PLL and some mult and dividers. - PERIPH: 40 or XTAL MHz. MT7620 is a bit more complex deriving CPU clock from a PLL and an bunch of register reads and predividers. To derive CPU and BUS frequencies in the MT7620 SoC 'mt7620_calc_rate()' helper is used. In the case XTAL can have different frequencies and we need a different clock frequency for peripherals 'periph' clock in introduced. The rest of the peripherals present in the SoC just follow their parent frequencies. With this information the clk driver will provide all the clock and reset functionality from a set of hardcoded clocks allowing to define a nice device tree without fixed clocks. Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-21dt-bindings: clock: add mtmips SoCs system controllerSergio Paracuellos1-0/+64
Adds device tree binding documentation for system controller node present in Mediatek MIPS and Ralink SOCs. This node is a clock and reset provider for the rest of the world. This covers RT2880, RT3050, RT3052, RT3350, RT3883, RT5350, MT7620, MT7628 and MT7688 SoCs. Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-20kvm/mips: update MAINTAINERSYu Zhao1-1/+0
Aleksandar Markovic was last seen in Oct 2020 [1] and cannot be reached for multiple days because of "Recipient inbox full". [1] https://lore.kernel.org/all/1602103041-32017-4-git-send-email-aleksandar.qemu.devel@gmail.com/ Signed-off-by: Yu Zhao <yuzhao@google.com> Acked-by: Huacai Chen <chenhuacai@kernel.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-20MIPS: PCI: Convert to platform remove callback returning voidUwe Kleine-König1-5/+3
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Eventually after all drivers are converted, .remove_new() is renamed to .remove(). Trivially convert this driver from always returning zero in the remove callback to the void returning variant. While destroying alignment of the assignments in bridge_driver, do it consistently and use a single space before =. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-20MIPS: Loongson64: loongson3_defconfig: Enable amdgpu drm driverSui Jingfeng1-0/+7
As it's usuable on LS3A4000 platform. Tested with RX550, glmark2 got about 4235 score. Signed-off-by: Sui Jingfeng <suijingfeng@loongson.cn> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-20MIPS: Mark core_vpe_count() as __initNathan Chancellor1-1/+1
After commit 96cb8ae28c65 ("MIPS: Rework smt cmdline parameters"), modpost complains when building with clang: WARNING: modpost: vmlinux.o: section mismatch in reference: core_vpe_count (section: .text) -> smp_max_threads (section: .init.data) This warning occurs when core_vpe_count() is not inlined, as it appears that a non-init function is referring to an init symbol. However, this is not a problem in practice because core_vpe_count() is only called from __init functions, cps_smp_setup() and cps_prepare_cpus(). Resolve the warning by marking core_vpe_count() as __init, as it is only called in an init context so it can refer to init functions and symbols and have its memory freed on boot. Fixes: 96cb8ae28c65 ("MIPS: Rework smt cmdline parameters") Signed-off-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-20MIPS: mm: Remove special handling for OCTEON CPUsThomas Bogendoerfer1-20/+4
Macro cpu_has_mips_r2_exec_hazard correctly handles OCTEON CPUs, so we don't need the extra switch cases for them. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09mips: dts: ralink: mt7628a: Unify pinctrl-single pin group nodesTony Lindgren1-20/+20
We want to unify the pinctrl-single pin group nodes to use naming "pins". Otherwise non-standad pin group names will add make dtbs checks errors when the pinctrl-single yaml binding gets merged. Cc: Conor Dooley <conor+dt@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09MIPS: Select CONFIG_GENERIC_IDLE_POLL_SETUPJiaxun Yang2-2/+3
hlt,nohlt paramaters are useful when debugging cpuidle related issues. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09MIPS: Rework smt cmdline parametersJiaxun Yang5-15/+25
Provide a generic smt parameters interface aligned with s390 to allow users to limit smt usage and threads per core. It replaced previous undocumented "nothreads" parameter for smp-cps which is ambiguous and does not cover smp-mt. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09mips: asm-offsets: add missing prototypesArnd Bergmann1-0/+14
Building with -Werror and W=1 fails entirely because of warnings in asm-offsets.c: arch/mips/kernel/asm-offsets.c:26:6: error: no previous prototype for 'output_ptreg_defines' [-Werror=missing-prototypes] arch/mips/kernel/asm-offsets.c:78:6: error: no previous prototype for 'output_task_defines' [-Werror=missing-prototypes] arch/mips/kernel/asm-offsets.c:92:6: error: no previous prototype for 'output_thread_info_defines' [-Werror=missing-prototypes] arch/mips/kernel/asm-offsets.c:108:6: error: no previous prototype for 'output_thread_defines' [-Werror=missing-prototypes] arch/mips/kernel/asm-offsets.c:136:6: error: no previous prototype for 'output_thread_fpu_defines' [-Werror=missing-prototypes] Nothing actually calls these functions, so just add prototypes to shut up the warnings. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09MIPS: cpu-features: Use boot_cpu_type for CPU type based featuresJiaxun Yang1-2/+2
Some CPU feature macros were using current_cpu_type to mark feature availability. However current_cpu_type will use smp_processor_id, which is prohibited under preemptable context. Since those features are all uniform on all CPUs in a SMP system, use boot_cpu_type instead of current_cpu_type to fix preemptable kernel. Cc: stable@vger.kernel.org Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09mips: dts: ralink: Add support for TP-Link HC220 G5 v1 boardLiviu Dudau2-1/+86
This WiFi AP is based on a MT7621 SoC with 128MiB RAM, 128MiB NAND, a MT7603 2.4GHz WiFi and a MT7613 5GHz WiFi chips integrated on the board, connected to the main SoC over PCIe. The device uses NMBM over NAND, which is not currently supported in the mainline, so NAND node is skipped in this revision. Signed-off-by: Liviu Dudau <liviu@dudau.co.uk> Reviewed-by: Arınç ÜNAL <arinc.unal@arinc9.com> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09dt-bindings: mips: Add bindings for TP-Link HC220 G5 v1 boardLiviu Dudau1-0/+1
Add bindings for the compatible string used for the TP-Link's HC220 G5 V1 board, a wireless AP based on MT7621. Signed-off-by: Liviu Dudau <liviu@dudau.co.uk> Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09MIPS: configs: CI20: Enable WiFi / BluetoothPaul Cercueil1-2/+27
Enable the required drivers for the WiFi / Bluetooth functionality. I enabled WEXT compatibility as well since the CI20 is typically used with a very old userspace. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09MIPS: configs: CI20: Regenerate defconfigPaul Cercueil1-12/+6
Just a "make ci20_defconfig menuconfig savedefconfig" Without changing anything in the menuconfig. No functional change. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09MIPS: DTS: CI20: Enable support for WiFi / BluetoothPaul Cercueil1-15/+73
Wire the WiFi/Bluetooth chip properly in the Device Tree. - Provide it with the correct regulators and clocks; - Change the MMC I/O bus to 1.8V which seems to be enough; - Change the MMC I/O bus frequency to 25 MHz as 50 MHz causes errors; - Fix the Bluetooth powerdown GPIO being inverted and add reset GPIO; - Convert host-wakeup-gpios to IRQ. With these changes, the WiFi works properly with the latest firmware provided by linux-firmware. The Bluetooth does not work very well here, as I cannot get my wireless keyboard to pair; but it does detect it, and it does see the key presses when I type the pairing code. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09MIPS: DTS: CI20: Parent MSCMUX clock to MPLLPaul Cercueil1-2/+3
This makes it possible to clock the SD cards much higher, as the MPLL is running at 1.2 GHz by default. The previous parent was the EXT clock, which caused the SD cards to be clocked at 24 MHz maximum. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09MIPS: DTS: CI20: Misc. cleanupsPaul Cercueil1-4/+4
- Use the standard "ecc-engine" property instead of the custom "ingenic,bch-controller" to get a handle to the BCH controller. - Respect cell sizes in the Ethernet controller node. - Use proper macro for interrupt type instead of hardcoding magic values. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09MIPS: DTS: CI20: Do not force-enable CIM and WiFi regulatorsPaul Cercueil1-3/+0
These regulators should be enabled by their respective drivers. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09MIPS: DTS: CI20: Add parent supplies to ACT8600 regulatorsPaul Cercueil1-0/+7
Provide parent regulators to the ACT8600 regulators that need one. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09MIPS: DTS: CI20: Fix ACT8600 regulator node namesPaul Cercueil1-19/+8
The Device Tree was using invalid node names for the ACT8600 regulators. To be fair, it is not the original committer's fault, as the documentation did gives invalid names as well. In theory, the fix should have been to modify the driver to accept the alternative names. However, even though the act8865 driver spits warnings, the kernel seemed to work fine with what is currently supported upstream. For that reason, I think it is okay to just update the DTS. I removed the "regulator-name" too, since they really didn't bring any information. The node names are enough. Fixes: 73f2b940474d ("MIPS: CI20: DTS: Add I2C nodes") Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09MIPS: DTS: CI20: Fix regulatorsPaul Cercueil1-6/+6
The regulators don't have any "reg" property, and therefore shouldn't use an unit address in their node names. They also don't need to specify the GPIO_ACTIVE_LOW flag, which will be ignored anyway, as they are active-high. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09MIPS: DTS: qi_lb60: Don't use unit address for regulatorsPaul Cercueil1-3/+3
The regulators don't have any "reg" property, and therefore shouldn't use an unit address in their node names. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09mips: ingenic: Enable EXT/2 divider on JZ4750/55/60 if EXT is 24 MHzPaul Cercueil1-0/+57
The JZ4750, JZ4755 and JZ4760 (non-B version) support using a 24 MHz external crystal oscillator instead of the typical 12 MHz one. However, most of the SoC's IP blocks only work with a 12 MHz clock. Thanksfully, there is a /2 divider we can enable when a 24 MHz external crystal is present. Force-enable this /2 divider when the oscillator is 24 MHz, so that the SoC always uses a 12 MHz clock internally. It is done here, and not in the clocks driver, because we need the EXT clock to be 12 MHz for the early console to work, and the clocks driver probes way too late. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09mips: ingenic: Remove useless __maybe_unusedPaul Cercueil1-2/+2
These flags are useless in this case as the code referencing these data structures is always seen by the compiler (and not behind #ifdef guards). Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09MIPS: uaccess: emulate Ingenic LXW/LXH/LXHU uaccessSiarhei Volkau2-0/+74
The LXW, LXH, LXHU opcodes are part of the MXU ASE found in Ingenic XBurst based SoCs. While technically part of the MXU ASE, they do not touch any of the SIMD registers, and can be used even when the MXU ASE is disabled. This patch makes it possible to emulate unaligned access for those instructions. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09Revert "MIPS: unhide PATA_PLATFORM"Maciej W. Rozycki1-1/+0
Revert commit 75b18aac6fa3 ("MIPS: unhide PATA_PLATFORM") now that HAVE_PATA_PLATFORM is set selectively for all the relevant platforms. Verified with `db1xxx_defconfig' and `sb1250_swarm_defconfig' by making sure PATA_PLATFORM is still there in `.config' with this change applied, and with `malta_defconfig' by making sure it's now gone. Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09MIPS: Alchemy: Enable PATA_PLATFORM supportMaciej W. Rozycki1-0/+1
We have limited demand for platform PATA support across MIPS platforms: $ find arch/mips -type f | sort | xargs grep -l pata_platform_info arch/mips/alchemy/devboards/db1200.c arch/mips/alchemy/devboards/db1300.c arch/mips/sibyte/swarm/platform.c $ certainly not high enough to justify enabling support for PATA_PLATFORM port-wide. SiByte platforms are handled selectively already, so just make a similar arrangement for Alchemy DB1XXX platforms. Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09Merge tag 'mips-fixes_6.4_1' into mips-nextThomas Bogendoerfer4-16/+26
- fixes to get alchemy platform back in shape - fix for initrd detection
2023-06-09mips: Fix spacing issueFranziska Naepelt1-7/+7
Fix some indentation issues and remove the following checkpatch issue: - ERROR: need consistent spacing around '-' (ctx:WxV) Co-Developed-by: Ladislav Michl <oss-lists@triops.cz> Signed-off-by: Franziska Naepelt <franziska.naepelt@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09MIPS: generic: Allow R5 CPUs to be selectedJiaxun Yang1-0/+2
Since we do have P5600 bitfile for boston board, we should allow generic kernel to be compiled for R5 CPUs. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-06-09mips: provide unxlate_dev_mem_ptr() in asm/io.hArnd Bergmann2-7/+1
The unxlate_dev_mem_ptr() function has no prototype on the mips architecture, which does not include asm-generic/io.h, so gcc warns about the __weak definition: drivers/char/mem.c:94:29: error: no previous prototype for 'unxlate_dev_mem_ptr' [-Werror=missing-prototypes] Since everyone else already gets the generic definition or has a custom one, there is not really much point in having a __weak version as well. Remove this one, and instead add a trivial macro to the mips header. Once we convert mips to use the asm-generic header, this can go away again. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-05-23mips: Move initrd_start check after initrd address sanitisation.Liviu Dudau1-4/+5
PAGE_OFFSET is technically a virtual address so when checking the value of initrd_start against it we should make sure that it has been sanitised from the values passed by the bootloader. Without this change, even with a bootloader that passes correct addresses for an initrd, we are failing to load it on MT7621 boards, for example. Signed-off-by: Liviu Dudau <liviu@dudau.co.uk> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-05-23MIPS: Alchemy: fix dbdma2Manuel Lauss1-12/+15
Various fixes for the Au1200/Au1550/Au1300 DBDMA2 code: - skip cache invalidation if chip has working coherency circuitry. - invalidate KSEG0-portion of the (physical) data address. - force the dma channel doorbell write out to bus immediately with a sync. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-05-23MIPS: Restore Au1300 supportManuel Lauss1-0/+5
The Au1300, at least the one I have to test, uses the NetLogic vendor ID, but commit 95b8a5e0111a ("MIPS: Remove NETLOGIC support") also dropped Au1300 detection. Restore Au1300 detection. Tested on DB1300 with Au1380 chip. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-05-23MIPS: unhide PATA_PLATFORMManuel Lauss1-0/+1
Alchemy DB1200/DB1300 boards can use the pata_platform driver. Unhide the config entry in all of MIPS. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-05-23mips: dts: ingenic: x1000: Add AIC device tree nodeAidan MacDonald1-0/+18
Add a node for the on-board I2S audio controller. Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-05-23MIPS: Loongson32: Remove reset.cKeguang Zhang4-68/+1
Commit 2a31bf20808a ("watchdog: loongson1_wdt: Implement restart handler") implmented .restart ops, Then, _machine_restart is no longer needed. The _machine_halt and pm_power_off are also unnecessary, which contain no hardware operations. Therefore, remove the entire reset.c and related header file. Update the Makefile accordingly. Signed-off-by: Keguang Zhang <keguang.zhang@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-05-23mips: dts: ingenic: Remove unnecessary AIC clocksAidan MacDonald3-13/+6
The "ext" and "pll half" clocks don't belong in the DT. They are not consumed directly by the AIC and are only used as the parent clocks of the "i2s" clock. An operating system should be able to figure out that information itself because it presumably knows the layout of the clock tree. Removing these from the DT should be safe from a compatibility point of view because the jz4740-i2s driver in Linux does not, and never did depend on them. Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com> Link: https://lore.kernel.org/all/20221028103418.17578-1-aidanmacdonald.0x0@gmail.com/ Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2023-05-22Linux 6.4-rc3Linus Torvalds1-1/+1
2023-05-22Merge tag 'uml-for-linus-6.4-rc3' of ↵Linus Torvalds5-7/+23
git://git.kernel.org/pub/scm/linux/kernel/git/uml/linux Pull UML fix from Richard Weinberger: - Fix modular build for UML watchdog * tag 'uml-for-linus-6.4-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/uml/linux: um: harddog: fix modular build
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