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2020-10-20Merge branches 'clk-semicolon', 'clk-axi-clkgen', 'clk-qoriq', 'clk-baikal', ↵Stephen Boyd9-68/+155
'clk-const' and 'clk-mmp2' into clk-next * clk-semicolon: clk: meson: use semicolons rather than commas to separate statements clk: mvebu: ap80x-cpu: use semicolons rather than commas to separate statements clk: uniphier: use semicolons rather than commas to separate statements * clk-axi-clkgen: clk: axi-clkgen: Set power bits for fractional mode clk: axi-clkgen: Add support for fractional dividers * clk-qoriq: clk: qoriq: modify MAX_PLL_DIV to 32 * clk-baikal: clk: baikal-t1: Mark Ethernet PLL as critical * clk-const: clk: pxa: Constify static struct clk_ops * clk-mmp2: clk: mmp2: Fix the display clock divider base
2020-10-20Merge branches 'clk-simplify', 'clk-ti', 'clk-tegra', 'clk-rockchip' and ↵Stephen Boyd35-104/+1915
'clk-mediatek' into clk-next - Small non-critical fixes for TI clk driver - Support Mediatek MT8167 clks * clk-simplify: clk: mediatek: fix platform_no_drv_owner.cocci warnings clk: mediatek: mt7629: simplify the return expression of mtk_infrasys_init clk: mediatek: mt6797: simplify the return expression of mtk_infrasys_init * clk-ti: clk: ti: dra7: add missing clkctrl register for SHA2 instance clk: ti: clockdomain: fix static checker warning clk: ti: autoidle: add checks against NULL pointer reference clk: keystone: sci-clk: add 10% slack to set_rate clk: keystone: sci-clk: cache results of last query rate operation clk: keystone: sci-clk: fix parsing assigned-clock data during probe * clk-tegra: clk: tegra: Drop !provider check in tegra210_clk_emc_set_rate() * clk-rockchip: clk: rockchip: Initialize hw to error to avoid undefined behavior clk: rockchip: rk3399: Support module build clk: rockchip: fix the clk config to support module build clk: rockchip: Export some clock common APIs for module drivers clk: rockchip: Export rockchip_register_softrst() clk: rockchip: Export rockchip_clk_register_ddrclk() clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls clk: rockchip: rk3308: drop unused mux_timer_src_p * clk-mediatek: clk: mediatek: Add MT8167 clock support dt-bindings: clock: mediatek: add bindings for MT8167 clocks clk: mediatek: add UART0 clock support
2020-10-20Merge branches 'clk-renesas', 'clk-amlogic', 'clk-allwinner', 'clk-samsung', ↵Stephen Boyd34-136/+2182
'clk-doc' and 'clk-unused' into clk-next - Remove various unused variables in clk drivers * clk-renesas: clk: renesas: rcar-gen3: Update description for RZ/G2 clk: renesas: cpg-mssr: Add support for R-Car V3U clk: renesas: cpg-mssr: Add register pointers into struct cpg_mssr_priv clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag dt-bindings: clock: renesas,cpg-mssr: Document r8a779a0 dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions dt-bindings: power: Add r8a779a0 SYSC power domain definitions clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r) clk: renesas: r8a7742: Add clk entry for VSPR * clk-amlogic: clk: meson: make shipped controller configurable clk: meson: g12a: mark fclk_div2 as critical clk: meson: axg-audio: fix g12a tdmout sclk inverter clk: meson: axg-audio: separate axg and g12a regmap tables clk: meson: add sclk-ws driver * clk-allwinner: clk: sunxi-ng: sun8i: r40: Use sigma delta modulation for audio PLL clk: sunxi-ng: add support for the Allwinner A100 CCU dt-bindings: clk: sunxi-ccu: add compatible string for A100 CCU and R-CCU * clk-samsung: clk: s2mps11: initialize driver via module_platform_driver clk: samsung: Use cached clk_hws instead of __clk_lookup() calls clk: samsung: exynos5420/5250: Add IDs to the CPU parent clk definitions clk: samsung: Add clk ID definitions for the CPU parent clocks clk: samsung: exynos5420: Avoid __clk_lookup() calls when enabling clocks clk: samsung: exynos5420: Add definition of clock ID for mout_sw_aclk_g3d clk: samsung: Keep top BPLL mux on Exynos542x enabled * clk-doc: clk: davinci: add missing kerneldoc clk: fixed: add missing kerneldoc * clk-unused: clk: socfpga: agilex: Remove unused variable 'cntr_mux' clk: si5341: drop unused 'err' variable clk: mmp: pxa1928: drop unused 'clk' variable clk: at91: drop unused at91sam9g45_pcr_layout
2020-10-14clk: mmp2: Fix the display clock divider baseLubomir Rintel1-2/+2
The LCD clock dividers are apparently based on one. No datasheet, determined empirically, but seems to be confirmed by line 19 of lcd.fth in OLPC laptop's Open Firmware [1]: h# 00000700 value pmua-disp-clk-sel \ PLL1 / 7 -> 113.86 MHz [1] https://raw.githubusercontent.com/quozl/openfirmware/65a08a73b2cac/cpu/arm/olpc/lcd.fth Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lore.kernel.org/r/20200925233914.227786-1-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-14clk: pxa: Constify static struct clk_opsRikard Falkeborn1-4/+4
Constify a couple of static struct clk_ops that are not modified. Their only usage is inside the macros and their address is passed to clk_register_composite() which takes pointers to const struct clk_ops. This allows the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200922184715.1854-1-rikard.falkeborn@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-14clk: baikal-t1: Mark Ethernet PLL as criticalSerge Semin1-6/+8
We've discovered that disabling the so called Ethernet PLL causes reset of the devices consuming its outgoing clock. The resets happen automatically even if each underlying clock gate is turned off. Due to that we can't disable the Ethernet PLL until the kernel is prepared for the corresponding resets. So for now just mark the PLL clock provider as critical. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: linux-mips@vger.kernel.org Link: https://lore.kernel.org/r/20200920110335.18034-1-Sergey.Semin@baikalelectronics.ru Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-14clk: qoriq: modify MAX_PLL_DIV to 32Zhao Qiang1-1/+1
On LS2088A, Watchdog need clk divided by 32, so modify MAX_PLL_DIV to 32 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Link: https://lore.kernel.org/r/20200916030311.17280-1-qiang.zhao@nxp.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-14clk: axi-clkgen: Set power bits for fractional modeLars-Peter Clausen1-0/+7
Using the fractional dividers requires some additional power bits to be set. The fractional power bits are not documented and the current heuristic for setting them seems be insufficient for some cases. Just always set all the fractional power bits when in fractional mode. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-2-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-14clk: axi-clkgen: Add support for fractional dividersLars-Peter Clausen1-51/+129
The axi-clkgen has (optional) fractional dividers on the output clock divider and feedback clock divider path. Utilizing the fractional dividers allows for a better resolution of the output clock, being able to synthesize more frequencies. Rework the driver support to support the fractional register fields, both for setting a new rate as well as reading back the current rate from the hardware. For setting the rate if no perfect divider settings were found in non-fractional mode try again in fractional mode and see if better settings can be found. This appears to be the recommended mode of operation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-14clk: meson: use semicolons rather than commas to separate statementsJulia Lawall1-1/+1
Replace commas with semicolons. What is done is essentially described by the following Coccinelle semantic patch (http://coccinelle.lip6.fr/): // <smpl> @@ expression e1,e2; @@ e1 -, +; e2 ... when any // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Link: https://lore.kernel.org/r/1601233948-11629-11-git-send-email-Julia.Lawall@inria.fr Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-14clk: mvebu: ap80x-cpu: use semicolons rather than commas to separate statementsJulia Lawall1-1/+1
Replace commas with semicolons. What is done is essentially described by the following Coccinelle semantic patch (http://coccinelle.lip6.fr/): // <smpl> @@ expression e1,e2; @@ e1 -, +; e2 ... when any // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Link: https://lore.kernel.org/r/1601233948-11629-10-git-send-email-Julia.Lawall@inria.fr Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-14clk: uniphier: use semicolons rather than commas to separate statementsJulia Lawall2-2/+2
Replace commas with semicolons. What is done is essentially described by the following Coccinelle semantic patch (http://coccinelle.lip6.fr/): // <smpl> @@ expression e1,e2; @@ e1 -, +; e2 ... when any // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Link: https://lore.kernel.org/r/1601233948-11629-2-git-send-email-Julia.Lawall@inria.fr Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-14clk: mediatek: Add MT8167 clock supportFabien Parent8-0/+1505
Add the following clock support for MT8167 SoC: topckgen, apmixedsys, infracfg, audsys, imgsys, mfgcfg, vdecsys. Signed-off-by: Fabien Parent <fparent@baylibre.com> Link: https://lore.kernel.org/r/20200918132303.2831815-2-fparent@baylibre.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-14dt-bindings: clock: mediatek: add bindings for MT8167 clocksFabien Parent8-0/+138
Add binding documentation for topckgen, apmixedsys, infracfg, audsys, imgsys, mfgcfg, vdecsys on MT8167 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200918132303.2831815-1-fparent@baylibre.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-09clk: mediatek: add UART0 clock supportHanks Chen1-0/+2
Add MT6779 UART0 clock support. Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support") Signed-off-by: Wendell Lin <wendell.lin@mediatek.com> Signed-off-by: Hanks Chen <hanks.chen@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-08clk: rockchip: Initialize hw to error to avoid undefined behaviorStephen Boyd1-1/+1
We can get down to this return value from ERR_CAST() without initializing hw. Set it to -ENOMEM so that we always return something sane. Fixes the following smatch warning: drivers/clk/rockchip/clk-half-divider.c:228 rockchip_clk_register_halfdiv() error: uninitialized symbol 'hw'. drivers/clk/rockchip/clk-half-divider.c:228 rockchip_clk_register_halfdiv() warn: passing zero to 'ERR_CAST' Cc: Elaine Zhang <zhangqing@rock-chips.com> Cc: Heiko Stuebner <heiko@sntech.de> Fixes: 956060a52795 ("clk: rockchip: add support for half divider") Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-24Merge tag 'v5.10-rockchip-clk1' of ↵Stephen Boyd9-85/+232
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull Rockchip clk driver updates from Heiko Stuebner: Ability to build the clock driver as module and removal of an unused parent-names struct. * tag 'v5.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: rk3399: Support module build clk: rockchip: fix the clk config to support module build clk: rockchip: Export some clock common APIs for module drivers clk: rockchip: Export rockchip_register_softrst() clk: rockchip: Export rockchip_clk_register_ddrclk() clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls clk: rockchip: rk3308: drop unused mux_timer_src_p
2020-09-24clk: tegra: Drop !provider check in tegra210_clk_emc_set_rate()Stephen Boyd1-1/+1
The provider variable is already dereferenced earlier in this function. Drop the check for NULL as it is impossible. Found with smatch drivers/clk/tegra/clk-tegra210-emc.c:131 tegra210_clk_emc_set_rate() warn: variable dereferenced before check 'provider' (see line 124) Cc: Joseph Lo <josephl@nvidia.com> Cc: Thierry Reding <treding@nvidia.com> Fixes: 0ac65fc946d3 ("clk: tegra: Implement Tegra210 EMC clock") Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200922191641.2305144-1-sboyd@kernel.org Acked-by: Thierry Reding <treding@nvidia.com>
2020-09-22clk: ti: dra7: add missing clkctrl register for SHA2 instanceTero Kristo2-0/+2
DRA7 SoC has two SHA instances. Add the clkctrl entry for the second one. Signed-off-by: Tero Kristo <t-kristo@ti.com> Link: https://lore.kernel.org/r/20200907082600.454-4-t-kristo@ti.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: ti: clockdomain: fix static checker warningTero Kristo1-0/+2
Fix a memory leak induced by not calling clk_put after doing of_clk_get. Reported-by: Dan Murphy <dmurphy@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Link: https://lore.kernel.org/r/20200907082600.454-3-t-kristo@ti.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: ti: autoidle: add checks against NULL pointer referenceTero Kristo1-2/+12
The clk pointer passed to omap2_clk_(deny|allow)_idle can be NULL, so add checks for this. Reported-by: Dan Murphy <dmurphy@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Link: https://lore.kernel.org/r/20200907082600.454-2-t-kristo@ti.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: keystone: sci-clk: add 10% slack to set_rateTero Kristo1-1/+2
Currently, we request exact clock rates from the firmware to be set with set_rate. Due to some rounding errors and internal functionality of the firmware itself, this can fail. Thus, add some slack to the set_rate functionality so that we are always guaranteed to pass. The firmware always attempts to use frequency as close to the target freq as possible despite the slack given here. Signed-off-by: Tero Kristo <t-kristo@ti.com> Link: https://lore.kernel.org/r/20200907085740.1083-4-t-kristo@ti.com Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: keystone: sci-clk: cache results of last query rate operationTero Kristo1-0/+14
Cache results of the latest query rate operation. This optimizes the firmware interface a bit, avoiding unnecessary calls to firmware if we know the result already; the firmware interface is pretty expensive to use for query rate functionality. Signed-off-by: Tero Kristo <t-kristo@ti.com> Link: https://lore.kernel.org/r/20200907085740.1083-3-t-kristo@ti.com Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: keystone: sci-clk: fix parsing assigned-clock data during probeTero Kristo1-1/+1
The DT clock probe loop incorrectly terminates after processing "clocks" only, fix this by re-starting the loop when all entries for current DT property have been parsed. Fixes: 8e48b33f9def ("clk: keystone: sci-clk: probe clocks from DT instead of firmware") Reported-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Link: https://lore.kernel.org/r/20200907085740.1083-2-t-kristo@ti.com Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: mediatek: fix platform_no_drv_owner.cocci warningsZou Wei1-1/+0
./drivers/clk/mediatek/clk-mt6765.c:912:3-8: No need to set .owner here. The core will do it. Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Fixes: 1aca9939bf72 ("clk: mediatek: Add MT6765 clock support") Signed-off-by: Zou Wei <zou_wei@huawei.com> Link: https://lore.kernel.org/r/1600761065-71353-1-git-send-email-zou_wei@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: mediatek: mt7629: simplify the return expression of mtk_infrasys_initLiu Shixin1-7/+2
Simplify the return expression. Signed-off-by: Liu Shixin <liushixin2@huawei.com> Link: https://lore.kernel.org/r/20200921082426.2591042-1-liushixin2@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: mediatek: mt6797: simplify the return expression of mtk_infrasys_initLiu Shixin1-6/+2
Simplify the return expression. Signed-off-by: Liu Shixin <liushixin2@huawei.com> Link: https://lore.kernel.org/r/20200921082425.2590990-1-liushixin2@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: socfpga: agilex: Remove unused variable 'cntr_mux'YueHaibing1-13/+0
drivers/clk/socfpga/clk-agilex.c:24:37: warning: ‘cntr_mux’ defined but not used [-Wunused-const-variable=] static const struct clk_parent_data cntr_mux[] = { ^~~~~~~~ There is no caller in tree, so can remove it. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20200915020950.4688-1-yuehaibing@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: si5341: drop unused 'err' variableKrzysztof Kozlowski1-3/+1
'err' is assigned but never read: /drivers/clk/clk-si5341.c: In function ‘si5341_output_get_parent’: drivers/clk/clk-si5341.c:886:6: warning: variable ‘err’ set but not used [-Wunused-but-set-variable] Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200916161740.14173-5-krzk@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: mmp: pxa1928: drop unused 'clk' variableKrzysztof Kozlowski1-2/+1
'clk' is assigned but never read: drivers/clk/mmp/clk-of-pxa1928.c: In function ‘pxa1928_pll_init’: drivers/clk/mmp/clk-of-pxa1928.c:71:14: warning: variable ‘clk’ set but not used [-Wunused-but-set-variable] Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200916161740.14173-4-krzk@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: at91: drop unused at91sam9g45_pcr_layoutKrzysztof Kozlowski1-7/+0
The at91sam9g45_pcr_layout is not used so drop it to fix build warning: drivers/clk/at91/at91sam9g45.c:49:36: warning: 'at91sam9g45_pcr_layout' defined but not used [-Wunused-const-variable=] Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20200916161740.14173-1-krzk@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: davinci: add missing kerneldocKrzysztof Kozlowski1-0/+1
Add missing kerneldoc to fix compile warning: drivers/clk/davinci/da8xx-cfgchip.c:578: warning: Function parameter or member 'dev' not described in 'da8xx_cfgchip_register_usb1_clk48' Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: David Lechner <david@lechnology.com> Link: https://lore.kernel.org/r/20200916161740.14173-3-krzk@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: fixed: add missing kerneldocKrzysztof Kozlowski2-0/+2
Add missing kerneldoc to fix compile warnings like: drivers/clk/clk-fixed-factor.c:211: warning: Function parameter or member 'node' not described in 'of_fixed_factor_clk_setup' Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200916161740.14173-2-krzk@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: s2mps11: initialize driver via module_platform_driverKrzysztof Kozlowski1-12/+1
The driver was using subsys_initcall() because in old times deferred probe was not supported everywhere and specific ordering was needed. Since probe deferral works fine and specific ordering is discouraged (hides dependencies between drivers and couples their boot order), the driver can be converted to regular module_platform_driver. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200921203558.19554-1-krzk@kernel.org Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22Merge tag 'clk-v5.10-samsung' of ↵Stephen Boyd9-46/+68
https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung Pull Samsung clk driver updates from Sylwester Nawrocki: Minor refactoring removing most of the __clk_lookup() calls. * tag 'clk-v5.10-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk: clk: samsung: Use cached clk_hws instead of __clk_lookup() calls clk: samsung: exynos5420/5250: Add IDs to the CPU parent clk definitions clk: samsung: Add clk ID definitions for the CPU parent clocks clk: samsung: exynos5420: Avoid __clk_lookup() calls when enabling clocks clk: samsung: exynos5420: Add definition of clock ID for mout_sw_aclk_g3d clk: samsung: Keep top BPLL mux on Exynos542x enabled
2020-09-22clk: rockchip: rk3399: Support module buildElaine Zhang2-1/+57
support CLK_OF_DECLARE and builtin_platform_driver_probe double clk init method. add module author, description and license to support building Soc Rk3399 clock driver as module. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200914022316.24045-1-zhangqing@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-09-22clk: rockchip: fix the clk config to support module buildElaine Zhang3-20/+101
use CONFIG_COMMON_CLK_ROCKCHIP for Rk common clk drivers. use CONFIG_CLK_RKXX for Rk soc clk driver. Mark CONFIG_CLK_RK3399 to "tristate", to support building Rk3399 SoC clock driver as module. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200914022304.23908-1-zhangqing@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-09-22clk: rockchip: Export some clock common APIs for module driversElaine Zhang1-22/+30
This is used by the Rockchip clk driver, export it to allow that driver to be compiled as a module. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200914022225.23613-5-zhangqing@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-09-22clk: rockchip: Export rockchip_register_softrst()Elaine Zhang1-3/+4
This is used by the Rockchip clk driver, export it to allow that driver to be compiled as a module.. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200914022225.23613-4-zhangqing@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-09-22clk: rockchip: Export rockchip_clk_register_ddrclk()Elaine Zhang1-0/+1
This is used by the Rockchip clk driver, export it to allow that driver to be compiled as a module.. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200914022225.23613-3-zhangqing@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-09-22clk: rockchip: Use clk_hw_register_composite instead of ↵Elaine Zhang2-39/+40
clk_register_composite calls clk_hw_register_composite it's already exported. Preparation for compilation of rK common clock drivers into modules. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200914022225.23613-2-zhangqing@rock-chips.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-09-22clk: rockchip: rk3308: drop unused mux_timer_src_pKrzysztof Kozlowski1-1/+0
The parent names 'mux_timer_src_p' is not used: In file included from drivers/clk/rockchip/clk-rk3308.c:13:0: drivers/clk/rockchip/clk-rk3308.c:136:7: warning: ‘mux_timer_src_p’ defined but not used [-Wunused-const-variable=] Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200916161740.14173-6-krzk@kernel.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-09-21Merge tag 'sunxi-clk-for-5.10-1' of ↵Stephen Boyd12-14/+1834
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull Allwinner clk driver updates from Maxime Ripard: Our usual PR for the Allwinner SoCs, this time adding support for the Allwinner A100 SoC, and adding support for the sigma-delta modulation on the audio PLL for the R40. * tag 'sunxi-clk-for-5.10-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: sun8i: r40: Use sigma delta modulation for audio PLL clk: sunxi-ng: add support for the Allwinner A100 CCU dt-bindings: clk: sunxi-ccu: add compatible string for A100 CCU and R-CCU
2020-09-21Merge tag 'clk-meson-v5.10-1' of https://github.com/BayLibre/clk-meson into ↵Stephen Boyd5-39/+274
clk-amlogic Pull amlogic clk driver updates from Jerome Brunet: - g12: update audio clock inverter and fdiv2 flag - config: allow to disable unnecessary amlogic clock controllers * tag 'clk-meson-v5.10-1' of https://github.com/BayLibre/clk-meson: clk: meson: make shipped controller configurable clk: meson: g12a: mark fclk_div2 as critical clk: meson: axg-audio: fix g12a tdmout sclk inverter clk: meson: axg-audio: separate axg and g12a regmap tables clk: meson: add sclk-ws driver
2020-09-21Merge tag 'clk-renesas-for-v5.10-tag2' of ↵Stephen Boyd17-62/+508
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Add support for the new R-Car V3U (R8A779A0) SoC - Add support for the VSP for Resizing clock on RZ/G1H, - Fix VSP clock names to match corrected hardware documentation. - Minor fixes and improvements * tag 'clk-renesas-for-v5.10-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: rcar-gen3: Update description for RZ/G2 clk: renesas: cpg-mssr: Add support for R-Car V3U clk: renesas: cpg-mssr: Add register pointers into struct cpg_mssr_priv clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag dt-bindings: clock: renesas,cpg-mssr: Document r8a779a0 dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions dt-bindings: power: Add r8a779a0 SYSC power domain definitions clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r) clk: renesas: r8a7742: Add clk entry for VSPR
2020-09-17clk: renesas: rcar-gen3: Update description for RZ/G2Lad Prabhakar1-1/+1
The rcar-gen3-cpg driver is also used on Renesas RZ/G2 SoC's, update the description for the CLK_RCAR_GEN3_CPG config symbol to reflect this. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> Link: https://lore.kernel.org/r/20200911101703.20521-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-09-17clk: renesas: cpg-mssr: Add support for R-Car V3UYoshihiro Shimoda5-1/+316
Initial support for R-Car V3U (r8a779a0), including core, module clocks, resets, and register access, because register specification differs from R-Car Gen2/3. Inspired by patches in the BSP by LUU HOAI. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1599810232-29035-4-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-09-17Merge tag 'renesas-r8a779a0-dt-binding-defs-tag' into clk-renesas-for-v5.10Geert Uytterhoeven2-0/+114
Renesas R-Car V3U DT Binding Definitions Clock and Power Domain definitions for the Renesas R-Car V3U (R8A779A0) SoC, shared by driver and DT source files.
2020-09-17clk: renesas: cpg-mssr: Add register pointers into struct cpg_mssr_privYoshihiro Shimoda1-35/+47
To support other register layouts in the future, add register pointers of {control,status,reset,reset_clear}_regs into struct cpg_mssr_priv. After that, we can remove unused macros like MSTPSR(). No behavioral changes. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1599810232-29035-3-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-09-17clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flagYoshihiro Shimoda3-19/+22
Geert suggested defining multiple register layout variants using an enum [1] to support further devices like R-Car V3U. So, use enum clk_reg_layout instead of a boolean .stbyctrl flag. No behavioral change. [1] https://lore.kernel.org/linux-renesas-soc/CAMuHMdVAgN69p9FFnQdO4iHk2CHkeNaVui2Q-FOY6_BFVjQ-Nw@mail.gmail.com/ Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1599810232-29035-2-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-25 21:22:48 +0300