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2021-12-20Merge tag 'samsung-drivers-5.17' of ↵Arnd Bergmann10-2/+487
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/drivers Samsung SoC drivers changes for v5.17 1. Exynos ChipID: add Exynos7885 support. 2. Exynos PMU: add Exynos850 support. 3. Minor bindings cleanup. 4. Add Exynos USIv2 (Universal Serial Interface) driver. The USI block is a shared IP block between I2C, UART/serial and SPI. Basically one has to choose which feature the USI block will support and later the regular I2C/serial/SPI driver will bind and work. This merges also one commit with dt-binding headers from my dts64 pull request. Together with a future serial driver change, this will break the ABI. Affected: Serial on ExynosAutov9 SADK and out-of-tree ExynosAutov9 boards Why: To properly and efficiently support the USI with new hierarchy of USI-{serial,SPI,I2C} devicetree nodes. Rationale: Recently added serial and USI support was short-sighted and did not allow to smooth support of other features (SPI and I2C). Adding support for USI-SPI and USI-I2C would effect in code duplication. Adding support for different USI versions (currently supported is USIv2 but support for v1 is planned) would cause even more code duplication and create a solution difficult to maintain. Since USI-serial and ExynosAutov9 have been added recently, are considered fresh development features and there are no supported products using them, the code/solution is being refactored in non-backwards compatible way. The compatibility is not broken yet. It will be when serial driver changes are accepted. The ABI break was discussed with only known users of ExynosAutov9 and received their permission. * tag 'samsung-drivers-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: dt-bindings: soc: samsung: keep SoC driver bindings together soc: samsung: Add USI driver dt-bindings: soc: samsung: Add Exynos USI bindings soc: samsung: exynos-pmu: Add Exynos850 support dt-bindings: samsung: pmu: Document Exynos850 soc: samsung: exynos-chipid: add Exynos7885 SoC support soc: samsung: exynos-chipid: describe which SoCs go with compatibles Link: https://lore.kernel.org/r/20211220115405.30434-2-krzysztof.kozlowski@canonical.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-20Merge tag 'imx-drivers-5.17' of ↵Arnd Bergmann4-4/+125
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers i.MX drivers update for 5.17: - A number of patches from Adam Ford to update gpcv2 and blk-ctrl driver to keep i.MX8MM VPU-H1 and i.MX8MN GPUMIX bus clocks active, and add i.MX8MN display related domain support. - Add optional continuous burst clock support for imx-weim bus driver. - Call pm_runtime_put_sync_suspend() instead of pm_runtime_put() in gpcv2 driver to prevent a sequence issue seen with i.MX8MM GPU and MIX domain. * tag 'imx-drivers-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: soc: imx: imx8m-blk-ctrl: add i.MX8MN DISP blk-ctrl dt-bindings: power: imx8mn: add defines for DISP blk-ctrl domains soc: imx: gpcv2: Add dispmix and mipi domains to imx8mn soc: imx: gpcv2: keep i.MX8MN gpumix bus clock enabled bus: imx-weim: optionally enable continuous burst clock soc: imx: gpcv2: keep i.MX8MM VPU-H1 bus clock active soc: imx: gpcv2: Synchronously suspend MIX domains Link: https://lore.kernel.org/r/20211218071427.26745-1-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-20Merge tag 'at91-soc-5.17' of ↵Arnd Bergmann1-0/+2
git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/drivers AT91 SoC #1 for 5.17: - one low priority fix about of_node_put() missing in PM code * tag 'at91-soc-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: at91: pm: Add of_node_put() before goto Link: https://lore.kernel.org/r/20211217164134.28566-1-nicolas.ferre@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-20Merge tag 'tegra-for-5.17-soc' of ↵Arnd Bergmann7-25/+326
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers soc/tegra: Changes for v5.17-rc1 This set of changes contains some preparatory work that is shared by several branches and trees to support DVFS via power domains. There's also a bit of cleanup and improvements to reboot on chips that use PSCI. * tag 'tegra-for-5.17-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: pmc: Rename core power domain soc/tegra: pmc: Rename 3d power domains soc/tegra: regulators: Prepare for suspend soc/tegra: fuse: Use resource-managed helpers soc/tegra: fuse: Reset hardware soc/tegra: pmc: Add reboot notifier soc/tegra: Don't print error message when OPPs not available Link: https://lore.kernel.org/r/20211217162253.1801077-1-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-20Merge tag 'tegra-for-5.17-drivers' of ↵Arnd Bergmann9-67/+369
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers drivers: Changes for v5.17-rc1 This is an assortment of driver patches that rely on some of the changes in the for-5.17/soc branch. These have all been acked by the respective maintainers and go through the Tegra tree to more easily handle the build dependency. * tag 'tegra-for-5.17-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: media: staging: tegra-vde: Support generic power domain spi: tegra20-slink: Add OPP support mtd: rawnand: tegra: Add runtime PM and OPP support mmc: sdhci-tegra: Add runtime PM and OPP support pwm: tegra: Add runtime PM and OPP support bus: tegra-gmi: Add runtime PM and OPP support usb: chipidea: tegra: Add runtime PM and OPP support soc/tegra: Add devm_tegra_core_dev_init_opp_table_common() soc/tegra: Enable runtime PM during OPP state-syncing Link: https://lore.kernel.org/r/20211217162253.1801077-2-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-20Merge tag 'ti-driver-soc-fixes-for-v5.17' of ↵Arnd Bergmann4-13/+14
git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into arm/drivers SoC: Keystone driver update for v5.17 * k3-socinfo: Add entry for J721S2 SoC family * Misc fixups for tisci, pruss, knav_dma * tag 'ti-driver-soc-fixes-for-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: soc: ti: knav_dma: Fix NULL vs IS_ERR() checking in dma_init soc: ti: k3-socinfo: Add entry for J721S2 SoC family firmware: ti_sci: rm: remove unneeded semicolon soc: ti: pruss: fix referenced node in error message Link: https://lore.kernel.org/r/20211217154921.cagzppcensxx6wm4@pension Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-18dt-bindings: soc: samsung: keep SoC driver bindings togetherKrzysztof Kozlowski3-2/+3
Recently added Samsung Exynos USI driver devicetree bindings were added under ../bindings/soc/samsung/exynos-usi.yaml, so move there also two other bindings for Exynos SoC drivers: the PMU and ChipID. Update Samsung Exynos MAINTAINERS entry to include this new path. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20211213112057.16709-1-krzysztof.kozlowski@canonical.com
2021-12-18soc: samsung: Add USI driverSam Protsenko3-0/+301
USIv2 IP-core is found on modern ARM64 Exynos SoCs (like Exynos850) and provides selectable serial protocol (one of: UART, SPI, I2C). USIv2 registers usually reside in the same register map as a particular underlying protocol it implements, but have some particular offset. E.g. on Exynos850 the USI_UART has 0x13820000 base address, where UART registers have 0x00..0x40 offsets, and USI registers have 0xc0..0xdc offsets. Desired protocol can be chosen via SW_CONF register from System Register block of the same domain as USI. Before starting to use a particular protocol, USIv2 must be configured properly: 1. Select protocol to be used via System Register 2. Clear "reset" flag in USI_CON 3. Configure HWACG behavior (e.g. for UART Rx the HWACG must be disabled, so that the IP clock is not gated automatically); this is done using USI_OPTION register 4. Keep both USI clocks (PCLK and IPCLK) running during USI registers modification This driver implements the above behavior. Of course, USIv2 driver should be probed before UART/I2C/SPI drivers. It can be achieved by embedding UART/I2C/SPI nodes inside of the USI node (in Device Tree); driver then walks underlying nodes and instantiates those. Driver also handles USI configuration on PM resume, as register contents can be lost during CPU suspend. This driver is designed with different USI versions in mind. So it should be relatively easy to add new USI revisions to it later. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20211204195757.8600-3-semen.protsenko@linaro.org Tested-by: Chanho Park <chanho61.park@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-12-17Merge tag 'renesas-drivers-for-v5.17-tag2' of ↵Arnd Bergmann10-380/+596
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers Renesas driver updates for v5.17 (take two) - Core support for the R-Car S4-8 (R8A779F0) SoC, including System Controller (SYSC) and Reset (RST) support. * tag 'renesas-drivers-for-v5.17-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: rcar-rst: Add support for R-Car S4-8 soc: renesas: Identify R-Car S4-8 soc: renesas: r8a779f0-sysc: Add r8a779f0 support soc: renesas: rcar-gen4-sysc: Introduce R-Car Gen4 SYSC driver dt-bindings: clock: Add r8a779f0 CPG Core Clock Definitions dt-bindings: power: Add r8a779f0 SYSC power domain definitions Link: https://lore.kernel.org/r/cover.1639736722.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-17soc: imx: imx8m-blk-ctrl: add i.MX8MN DISP blk-ctrlAdam Ford1-1/+76
This adds the description for the i.MX8MN disp blk-ctrl. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-17dt-bindings: power: imx8mn: add defines for DISP blk-ctrl domainsAdam Ford1-0/+5
This adds the defines for the power domains provided by the DISP blk-ctrl. Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-17soc: imx: gpcv2: Add dispmix and mipi domains to imx8mnAdam Ford1-0/+25
The dispmix will be needed for the blkctl driver, so add it to the gpcv2. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-17soc: imx: gpcv2: keep i.MX8MN gpumix bus clock enabledAdam Ford1-0/+1
Like the i.MX8MM, keep the gpumix clocks running when the domain is active. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-16media: staging: tegra-vde: Support generic power domainDmitry Osipenko1-11/+52
Currently driver supports legacy power domain API, this patch adds generic power domain support. This allows us to utilize a modern GENPD API for newer device-trees. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30 Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20 Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30 Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16spi: tegra20-slink: Add OPP supportDmitry Osipenko1-1/+8
The SPI on Tegra belongs to the core power domain and we're going to enable GENPD support for the core domain. Now SPI driver must use OPP API for driving the controller's clock rate because OPP API takes care of reconfiguring the domain's performance state in accordance to the rate. Add OPP support to the driver. Acked-by: Mark Brown <broonie@kernel.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16mtd: rawnand: tegra: Add runtime PM and OPP supportDmitry Osipenko1-8/+50
The NAND on Tegra belongs to the core power domain and we're going to enable GENPD support for the core domain. Now NAND must be resumed using runtime PM API in order to initialize the NAND power state. Add runtime PM and OPP support to the NAND driver. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16mmc: sdhci-tegra: Add runtime PM and OPP supportDmitry Osipenko1-16/+65
The SDHCI on Tegra belongs to the core power domain and we're going to enable GENPD support for the core domain. Now SDHCI must be resumed using runtime PM API in order to initialize the SDHCI power state. The SDHCI clock rate must be changed using OPP API that will reconfigure the power domain performance state in accordance to the rate. Add runtime PM and OPP support to the SDHCI driver. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16pwm: tegra: Add runtime PM and OPP supportDmitry Osipenko1-18/+64
The PWM on Tegra belongs to the core power domain and we're going to enable GENPD support for the core domain. Now PWM must be resumed using runtime PM API in order to initialize the PWM power state. The PWM clock rate must be changed using OPP API that will reconfigure the power domain performance state in accordance to the rate. Add runtime PM and OPP support to the PWM driver. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16bus: tegra-gmi: Add runtime PM and OPP supportDmitry Osipenko1-6/+44
The GMI bus on Tegra belongs to the core power domain and we're going to enable GENPD support for the core domain. Now GMI must be resumed using runtime PM API in order to initialize the GMI power state. Add runtime PM and OPP support to the GMI driver. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16usb: chipidea: tegra: Add runtime PM and OPP supportDmitry Osipenko1-7/+46
The Tegra USB controller belongs to the core power domain and we're going to enable GENPD support for the core domain. Now USB controller must be resumed using runtime PM API in order to initialize the USB power state. We already support runtime PM for the CI device, but CI's PM is separated from the RPM managed by tegra-usb driver. Add runtime PM and OPP support to the driver. Acked-by: Peter Chen <peter.chen@kernel.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16Merge branch 'tegra-for-5.17-soc-opp' of ↵Thierry Reding2-0/+40
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into for-5.17/drivers
2021-12-16soc/tegra: pmc: Rename core power domainDmitry Osipenko1-1/+1
CORE power domain uses name of device-tree node, which is inconsistent with the names of PMC domains. Set the name to "core" to make it consistent. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16soc/tegra: Add devm_tegra_core_dev_init_opp_table_common()Dmitry Osipenko1-0/+15
Only couple drivers need to get the -ENODEV error code and majority of drivers need to explicitly initialize the performance state. Add new common helper which sets up OPP table for these drivers. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16soc/tegra: pmc: Rename 3d power domainsDmitry Osipenko1-4/+4
Device-tree schema doesn't allow domain name to start with a number. We don't use 3d domain yet in device-trees, so rename it to the name used by Tegra TRMs: TD, TD2. Reported-by: David Heidelberg <david@ixit.cz> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16soc/tegra: Enable runtime PM during OPP state-syncingDmitry Osipenko1-0/+25
GENPD core now can set up domain's performance state properly while device is RPM-suspended. Runtime PM of a device must be enabled during setup because GENPD checks whether device is suspended and check doesn't work while RPM is disabled. Instead of replicating the boilerplate RPM-enable code around OPP helper for each driver, let's make OPP helper to take care of enabling it. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16soc/tegra: regulators: Prepare for suspendDmitry Osipenko2-0/+221
Depending on hardware version, Tegra SoC may require a higher voltages during resume from system suspend, otherwise hardware will crash. Set SoC voltages to a nominal levels during suspend. Link: https://lore.kernel.org/all/a8280b5b-7347-8995-c97b-10b798cdf057@gmail.com/ Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16soc/tegra: fuse: Use resource-managed helpersDmitry Osipenko2-17/+48
Use resource-managed helpers to make code cleaner and more correct, properly releasing all resources in case of driver probe error. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16soc/tegra: fuse: Reset hardwareDmitry Osipenko2-0/+26
The FUSE controller is enabled at a boot time. Reset it in order to put hardware and clock into clean and disabled state. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16soc/tegra: pmc: Add reboot notifierJon Hunter1-3/+28
The Tegra PMC driver implements a restart handler that supports Tegra specific reboot commands such as placing the device into 'recovery' mode in order to reprogram the platform. This is accomplished by setting the appropriate bit in the PMC scratch0 register prior to rebooting the platform. For Tegra platforms that support PSCI or EFI, the default Tegra restart handler is not called and the PSCI or EFI restart handler is called instead. Hence, for Tegra platforms that support PSCI or EFI, the Tegra specific reboot commands do not currently work. Fix this by moving the code that programs the PMC scratch0 register into a separate reboot notifier that will always be called on reboot. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16soc/tegra: Don't print error message when OPPs not availableDmitry Osipenko1-3/+1
Previously we assumed that devm_tegra_core_dev_init_opp_table() will be used only by drivers that will always have device with OPP table, but this is not true anymore. For example now Tegra30 will have OPP table for PWM, but Tegra20 not and both use the same driver. Hence let's not print the error message about missing OPP table in the common helper, we can print it elsewhere. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16soc: ti: knav_dma: Fix NULL vs IS_ERR() checking in dma_initMiaoqian Lin1-10/+10
Since devm_ioremap_resource() function return error pointers. The pktdma_get_regs() function does not return NULL, It return error pointers too. Using IS_ERR() to check the return value to fix this. Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20211214015544.7270-1-linmq006@gmail.com
2021-12-15Merge tag 'asahi-soc-pmgr-5.17-v2' of https://github.com/AsahiLinux/linux ↵Arnd Bergmann2-1/+8
into arm/drivers Apple SoC PMGR driver updates for 5.17 * Adds an auto-PM feature that is necessary for a single device * Disables module builds, which were broken anyway * tag 'asahi-soc-pmgr-5.17-v2' of https://github.com/AsahiLinux/linux: soc: apple: apple-pmgr-pwrstate: Do not build as a module soc: apple: apple-pmgr-pwrstate: Add auto-PM min level support Link: https://lore.kernel.org/r/660f6f7f-0857-b54c-c415-79bcb93f0e02@marcan.st Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-15soc: apple: apple-pmgr-pwrstate: Do not build as a moduleHector Martin1-1/+1
This doesn't make any sense as a module since it is a critical device, and it turns out of_phandle_iterator_args was not exported so the module version doesn't build anyway. Fixes: 6df9d38f9146 ("soc: apple: Add driver for Apple PMGR power state controls") Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Sven Peter <sven@svenpeter.dev> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-14Merge tag 'memory-controller-drv-renesas-5.17' of ↵Arnd Bergmann5-57/+122
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers Memory controller drivers for v5.17 - Renesas Changes to the Renesas RPC-IF driver: 1. Add support for R9A07G044 / RZ/G2L. 2. Several minor fixes and improvements to the driver. * tag 'memory-controller-drv-renesas-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl: memory: renesas-rpc-if: refactor MOIIO and IOFV macros memory: renesas-rpc-if: avoid use of undocumented bits memory: renesas-rpc-if: simplify register update memory: renesas-rpc-if: Silence clang warning memory: renesas-rpc-if: Add support for RZ/G2L memory: renesas-rpc-if: Drop usage of RPCIF_DIRMAP_SIZE macro memory: renesas-rpc-if: Return error in case devm_ioremap_resource() fails dt-bindings: memory: renesas,rpc-if: Add optional interrupts property dt-bindings: memory: renesas,rpc-if: Add support for the R9A07G044 Link: https://lore.kernel.org/r/20211213105618.5686-1-krzysztof.kozlowski@canonical.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-14Merge tag 'optee-async-notif-for-v5.17' of ↵Arnd Bergmann14-124/+523
https://git.linaro.org/people/jens.wiklander/linux-tee into arm/drivers OP-TEE Asynchronous notifications from secure world Adds support in the SMC based OP-TEE driver to receive asynchronous notifications from secure world using an edge-triggered interrupt as delivery mechanism. * tag 'optee-async-notif-for-v5.17' of https://git.linaro.org/people/jens.wiklander/linux-tee: optee: Fix NULL but dereferenced coccicheck error optee: add asynchronous notifications optee: separate notification functions tee: export teedev_open() and teedev_close_context() tee: fix put order in teedev_close_context() dt-bindings: arm: optee: add interrupt property docs: staging/tee.rst: add a section on OP-TEE notifications Link: https://lore.kernel.org/r/20211213102359.GA1638682@jade Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-14Merge tag 'zynqmp-soc-for-v5.17' of https://github.com/Xilinx/linux-xlnx ↵Arnd Bergmann3-42/+55
into arm/drivers arm64: dts: ZynqMP SoC changes for v5.17 - cleanup and fix PM_INIT_FINALIZE - check return value of zynqmp_pm_get_api_version() * tag 'zynqmp-soc-for-v5.17' of https://github.com/Xilinx/linux-xlnx: firmware: xilinx: check return value of zynqmp_pm_get_api_version() soc: xilinx: add a to_zynqmp_pm_domain macro soc: xilinx: use a properly named field instead of flags soc: xilinx: cleanup debug and error messages soc: xilinx: move PM_INIT_FINALIZE to zynqmp_pm_domains driver Link: https://lore.kernel.org/r/48dec441-2c1f-73a0-3e6c-aa0d7be5ba26@monstr.eu Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-14Merge tag 'asahi-soc-pmgr-5.17' of https://github.com/AsahiLinux/linux into ↵Arnd Bergmann5-0/+343
arm/drivers Apple SoC PMGR driver for 5.17 Adds the new PMGR driver. This includes the driver only; DT and MAINTAINERS changes are part of the DT pull. Minor change from v3: added `depends on PM` to the Kconfig to fix COMPILE_TEST randconfig failures. * tag 'asahi-soc-pmgr-5.17' of https://github.com/AsahiLinux/linux: soc: apple: Add driver for Apple PMGR power state controls Link: https://lore.kernel.org/r/049f4de9-51be-7be4-1f9a-a59756af88d7@marcan.st Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-14Merge tag 'renesas-drivers-for-v5.17-tag1' of ↵Arnd Bergmann3-62/+98
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/drivers Renesas driver updates for v5.17 - Add a remoteproc API for controlling the Cortex-R7 boot address on R-Car Gen3 SoCs, - Consolidate product register handling. * tag 'renesas-drivers-for-v5.17-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: Consolidate product register handling soc: renesas: rcar-rst: Add support to set rproc boot address Link: https://lore.kernel.org/r/cover.1638530612.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-14bus: imx-weim: optionally enable continuous burst clockIvan Bornyakov1-2/+16
To enable continuous burst clock, add "fsl,continuous-burst-clk" along with "fsl,burst-clk-enable" property to the weim bus's devicetree node. Example: weim: weim@21b8000 { compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim"; reg = <0x021b8000 0x4000>; clocks = <&clks 143>; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0x50000000 0x08000000>; fsl,weim-cs-gpr = <&gpr>; fsl,burst-clk-enable; fsl,continuous-burst-clk; client-device@0 { ... }; }; Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-12-13soc: ti: k3-socinfo: Add entry for J721S2 SoC familyAswath Govindraju1-1/+2
J721S2 SoC's JTAG PARTNO is 0xBB75. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20211203120913.14737-1-a-govindraju@ti.com
2021-12-13Merge tag 'samsung-dt64-exynos-usi-5.17' into next/driversKrzysztof Kozlowski2-0/+176
Samsung DTS ARM64 driver bindings for v5.17 Header with Samsung Exynos USI driver constants used by both DTS and driver.
2021-12-13dt-bindings: soc: samsung: Add Exynos USI bindingsSam Protsenko2-0/+176
Add constants for choosing USIv2 configuration mode in device tree. Those are further used in USI driver to figure out which value to write into SW_CONF register. Also document USIv2 IP-core bindings. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211204195757.8600-2-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-12-12soc: apple: apple-pmgr-pwrstate: Add auto-PM min level supportHector Martin1-0/+7
This is seemingly required for DCP/DCPEXT, without which they refuse to boot properly. They need to be set to minimum state 4 (clock gated). Reviewed-by: Sven Peter <sven@svenpeter.dev> Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-08ARM: at91: pm: Add of_node_put() before gotoWan Jiabing1-0/+2
Fix following coccicheck warning: ./arch/arm/mach-at91/pm.c:643:1-33: WARNING: Function for_each_matching_node_and_match should have of_node_put() before goto Early exits from for_each_matching_node_and_match should decrement the node reference counter. Signed-off-by: Wan Jiabing <wanjiabing@vivo.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211014084555.21422-1-wanjiabing@vivo.com
2021-12-08firmware: xilinx: check return value of zynqmp_pm_get_api_version()Rajan Vaja1-1/+4
Currently return value of zynqmp_pm_get_api_version() is ignored. Because of that, API version is checked in case of error also. So add check for return value of zynqmp_pm_get_api_version(). Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/1633509835-31949-1-git-send-email-rajan.vaja@xilinx.com Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-12-08soc: xilinx: add a to_zynqmp_pm_domain macroMichael Tretter1-12/+8
Replace container_of for converting a generic_pm_domain to a zynqmp_pm_domain with a macro definition to simplify the code. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Rajan Vaja <rajan.vaja@xilinx.com> Link: https://lore.kernel.org/r/20210825150313.4033156-5-m.tretter@pengutronix.de Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-12-08soc: xilinx: use a properly named field instead of flagsMichael Tretter1-7/+5
Instead of defining a flags field and a single bit in this field to signal that a PM node has been requested, use a boolean field with a descriptive name. No functional change, but using a proper name instead of flags makes the code easier to read. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Rajan Vaja <rajan.vaja@xilinx.com> Link: https://lore.kernel.org/r/20210825150313.4033156-4-m.tretter@pengutronix.de Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-12-08soc: xilinx: cleanup debug and error messagesMichael Tretter1-22/+23
Use dev_err/dev_dbg instead of pr_err/pr_debug. Add the PM node ids to supplement the (arbitrary) power domain names to include information which PM nodes are requested by the driver. Drop function names from the messages, because they can easily be added with dynamic debug. Remove comments explaining that error messages are printed on errors. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Rajan Vaja <rajan.vaja@xilinx.com> Link: https://lore.kernel.org/r/20210825150313.4033156-3-m.tretter@pengutronix.de Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-12-08soc: xilinx: move PM_INIT_FINALIZE to zynqmp_pm_domains driverMichael Tretter2-1/+16
PM_INIT_FINALIZE tells the PMU FW that Linux is able to handle the power management nodes that are provided by the PMU FW. Nodes that are not requested are shut down after this call. Calling PM_INIT_FINALIZE from the zynqmp_power driver is wrong. The PM node request mechanism is implemented in the zynqmp_pm_domains driver, which must also call PM_INIT_FINALIZE. Due to the behavior of the PMU FW, all devices must be powered up before PM_INIT_FINALIZE is called, because otherwise the devices might misbehave. Calling PM_INIT_FINALIZE from the sync_state device callback ensures that all users probed successfully before the PMU FW is allowed to power off unused domains. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Rajan Vaja <rajan.vaja@xilinx.com> Link: https://lore.kernel.org/r/20210825150313.4033156-2-m.tretter@pengutronix.de Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-12-07soc: renesas: rcar-rst: Add support for R-Car S4-8Yoshihiro Shimoda1-3/+4
Add support for R-Car S4-8 (R8A779F0) to the R-Car RST driver. The register map of R-Car S4-8 is the same as R-Car V3U so that renames "V3U" and "r8a779a0" to "Gen4". Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20211201073308.1003945-11-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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