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2021-02-04drm/mediatek: Enable dither functionYongqiang Niu1-0/+3
Enable dither function to improve the display quality. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: Enable OVL_LAYER_SMI_ID_EN for multi-layer usecaseYongqiang Niu1-0/+17
Enable OVL_LAYER_SMI_ID_EN for multi-layer usecase, without this patch, ovl will hang up when more than 1 layer enabled. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: Add support for SoC MT8183Yongqiang Niu4-0/+70
1. Add ovl private data 2. Add rdma private data 3. Add gamma privte data 4. Add main and external path module for crtc create Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: Add has_dither private data for gammaYongqiang Niu1-4/+10
Not all SoC has dither function in gamma module. Add private data to control this function setting. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: Separate gamma moduleYongqiang Niu6-61/+216
mt8183 gamma module will different with mt8173, so separate gamma for adding private data. Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: Add mtk_dither_set_common() functionHsin-Yi Wang2-9/+22
Current implementation of mtk_dither_set() cast dev data to struct mtk_ddp_comp_dev. But other devices with different dev data would also call this function. Separate necessary parameters out so other device components (dither, gamma) can call this function. Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04soc / drm: mediatek: Move mtk mutex driver to soc folderCK Hu7-7/+16
mtk mutex is used by DRM and MDP driver, and its function is SoC-specific, so move it to soc folder. Signed-off-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
2021-02-04drm/mediatek: Automatically search unclaimed mtk mutex in mtk_mutex_get()CK Hu3-10/+10
Moving mutex resource management from client driver to mutex driver could prevent client drivers negotiating for resource management. Signed-off-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: Change disp/ddp term to mutex in mtk mutex driverCK Hu5-183/+182
mtk mutex is used by both drm and mdp driver, so change disp/ddp term to mutex to show that it's a common driver for drm and mdp. Signed-off-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: Rename file mtk_drm_ddp to mtk_mutexCK Hu4-7/+7
After mmsys routing function is moved out of mtk_drm_ddp.c, mtk_drm_ddp.c has only mtk mutex function, so rename it to match the function in it. Signed-off-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: Remove redundant file includingCK Hu2-4/+0
Those file includings are useless, so remove them. Signed-off-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: Add fifo_size into rdma private dataYongqiang Niu1-1/+18
Get the fifo size from device tree because each rdma in the same SoC may have different fifo size Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: Fix aal size configYongqiang Niu1-1/+1
The orginal setting is not correct, fix it to follow hardware data sheet. If keep this error setting, mt8173/mt8183 display ok but mt8192 display abnormal. Fixes: 0664d1392c26 ("drm/mediatek: Add AAL engine basic function") Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04dt-bindings: mediatek: add description for postmaskYongqiang Niu1-0/+1
add description for postmask postmask is used control round corner for display frame Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: mtk_dpi: Create connector for bridgesHsin-Yi Wang1-1/+12
Similar to commit a9d9fea74be2 ("drm/mediatek: mtk_dsi: Create connector for bridges"): Use the drm_bridge_connector helper to create a connector for pipelines that use drm_bridge. This allows splitting connector operations across multiple bridges when necessary, instead of having the last bridge in the chain creating the connector and handling all connector operations internally. Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04dt-bindings: mediatek: add rdma-fifo-size description for mt8183 displayYongqiang Niu1-0/+9
rdma fifo size may be different even in same SOC, add this property to the corresponding rdma Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04drm/mediatek: Check if fb is nullYongqiang Niu1-1/+1
It's possible that state->base.fb is null. Add a check before access its format. Fixes: b6b1bb980ec4 ("drm/mediatek: Turn off Alpha bit when plane format has no alpha") Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2021-02-04Merge tag 'drm-intel-next-2021-01-29' of ↵Dave Airlie16-247/+434
git://anongit.freedesktop.org/drm/drm-intel into drm-next - WARN if plane src coords are too big (Ville) - Prevent double YUV range correction on HDR planes (Andres) - DP MST related Fixes (Sean, Imre) - More clean-up around DRAM detection code (Jose) - Actually async flips enable for all ilk+ platforms (Ville) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210129225328.GA1041349@intel.com
2021-02-04Merge tag 'drm/tegra/for-5.12-rc1' of ↵Dave Airlie9-20/+45
ssh://git.freedesktop.org/git/tegra/linux into drm-next drm/tegra: Changes for v5.12-rc1 Adds support for newer firmware image versions of the Video Image Composer (VIC) and adds a comment clarifying the use of the STREAMID registers. Fixes a couple of issues with display and gr2d on older Tegra SoCs such as Tegra114, as well as a runtime PM reference leak. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Thierry Reding <thierry.reding@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210129193807.3653456-1-thierry.reding@gmail.com
2021-02-02drm/amdgpu: Prevent shift wrapping in amdgpu_read_mask()Dan Carpenter1-3/+3
If the user passes a "level" value which is higher than 31 then that leads to shift wrapping. The undefined behavior will lead to a syzkaller stack dump. Fixes: 5632708f4452 ("drm/amd/powerplay: add dpm force multiple levels on cz/tonga/fiji/polaris (v2)") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02amd/display: remove unneeded variable: "pattern"Bernard Zhao1-3/+1
Remove unneeded variable: "pattern". Signed-off-by: Bernard Zhao <bernard@vivo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/pm: Disable GFXOFF when GFX DPM or PG disabledJinzhou Su1-4/+10
Check GFX DPM and PG bit before enable GFXOFF on Vangogh smu post init. Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: 3.2.121Aric Cyr1-1/+1
This version brings along following fixes: - Better handling of dummy p-state table - Workaround for some legacy DP-VGA dongles - Add Freesync HDMI support to DMCU - Enable "trigger_hotplug" debugfs on all outputs - fix initial bounding box values for dcn3.02 - implement support for DID2.0 dsc passthrough - fix calculation for the pwl backlight curve - Fix multiple memory leaks Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: [FW Promotion] Release 0.0.50Anthony Koo1-2/+2
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Reject too small viewport size when validating planeNikola Cornij3-3/+29
[why] Overlay won't move to a new positon if viewport size is smaller than what can be handled. It'd either disappear or stay at the old position. This condition is for example hit if overlay is moved too much outside of left or top edge of the screen, but it applies to any non-cursor plane type. [how] Reject this contidion at validation time. This gives the calling level a chance to handle this gracefully and avoid inconsistent behaivor. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Better handling of dummy p-state tableJoshua Aberback1-7/+5
[Why] Some scenarios where we use a UCLK frequency in between dummy p-state table entries result in a p-state hang, due to the table not having a close enough match, so the default DPM0 latency is used, which can be too long to support dummy p-state switching in these scenarios. [How] - old: match if current freq is within +- margin of table entry - new: find largest table entry that is lower than current freq + margin - lower than DPM0 will still use DPM0 Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Workaround for some legacy DP-VGA donglesTaimur Hassan1-1/+12
[Why] Maximum resolution is 1440*900 when connecting to FHD monitor via some DP-VGA dongles. The display EDID reading fails over AUX/I2C via DP->VGA dongle, and this leads to the maximum resolution 1920*1080 cannot be obtained from EDID. [How] Provide a workaround for some legacy DP-VGA dongles with a longer aux delay. Signed-off-by: Taimur Hassan <syed.hassan@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Decrement refcount of dc_sink before reassignmentVictor Lu1-1/+3
[why] An old dc_sink state is causing a memory leak because it is missing a dc_sink_release before a new dc_sink is assigned back to aconnector->dc_sink. [how] Decrement the dc_sink refcount before reassigning it to a new dc_sink. Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Free atomic state after drm_atomic_commitVictor Lu1-8/+6
[why] drm_atomic_commit was changed so that the caller must free their drm_atomic_state reference on successes. [how] Add drm_atomic_commit_put after drm_atomic_commit call in dm_force_atomic_commit. Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: remove unused force_ignore_link_settings debug optionWenjing Liu2-4/+0
[why] Remove force_ignore_link_settings debug option as it is no longer used. Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Add Freesync HDMI support to DMCUStylon Wang6-1/+268
[Why] Adding support for Freesync HDMI to DC and DMCU [How] Create DC interface and implementation on top of DMCU to support parsing CEA blocks in DMCU. Signed-off-by: Stylon Wang <stylon.wang@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Enable "trigger_hotplug" debugfs on all outputsStylon Wang1-4/+6
[Why] Per-connector debugfs entry "trigger_hotplug" is available on DP/eDP only. New IGT tests need this entry to test other outputs. [How] Enable this debugfs entry on all types of connectors Signed-off-by: Stylon Wang <stylon.wang@amd.com> Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Fix CW4 programming for dmub30 cached inboxNicholas Kazlauskas3-2/+4
[Why] The conditions for whether we used cached vs non-cached inbox1 depend on a version check that mismatches what the shared helpers in dmub20 implement. [How] Use the dmub_dcn20_use_cached_inbox check for dmub_dcn30 as well. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: fix initial bounding box values for dcn3.02Samson Tam3-10/+184
[Why] Initial bounding box values are updated in dcn30_update_bw_bounding_box but they use dcn3_0_soc and dcn3_0_ip instead of dcn3_02_soc and dcn3_02_ip [How] Add dcn302_update_bw_bounding_box and dcn302_get_optimal_dcfclk_fclk_for_uclk so it uses dcn3_02_soc and dcn3_02_ip. Use sr_exit_time_us, sr_enter_plus_exit_time_us, from dcn30 on dcn302 to fix flicker on eDP. Also use dram_clock_change_latency_us from dcn30. Signed-off-by: Samson Tam <Samson.Tam@amd.com> Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: implement support for DID2.0 dsc passthroughJun Lei3-14/+23
[Why] Some panels contain active converters (e.g. DP to MIPI) which only support restricted DSC configurations. DID2.0 adds support for such displays to explicitly define per timing BPP restrictions on DSC. Ignoring these restrictions leads to blackscreen. [How] Add parsing in DID2.0 parser to get this bpp info. Add support in DSC module to constraint target bpp based on this info. Signed-off-by: Jun Lei <jun.lei@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Fix dc_sink kref count in emulated_link_detectVictor Lu1-2/+2
[why] prev_sink is not used anywhere else in the function and the reference to it from dc_link is replaced with a new dc_sink. [how] Change dc_sink_retain(prev_sink) to dc_sink_release(prev_sink). Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Release DSC before acquiringMikita Lipski1-1/+5
[why] Need to unassign DSC from pipes that are not using it so other pipes can acquire it. That is needed for asic's that have unmatching number of DSC engines from the number of pipes. [how] Before acquiring dsc to stream resources, first remove it. Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Eryk Brol <Eryk.Brol@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Revert "Fix EDID parsing after resume from suspend"Stylon Wang1-2/+0
This reverts commit b24bdc37d03a0478189e20a50286092840f414fa. It caused memory leak after S3 on 4K HDMI displays. Signed-off-by: Stylon Wang <stylon.wang@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: fix calculation for the pwl backlight curveAnthony Koo1-1/+1
[Why] The PWL backlight curve is used by the firmware to convert between brightness and linear PWM value. Driver has a backlight LUT, but the firmware holds a PWL curve and interpolates between points. The calculations are incorrect leading to slightly off backlight values being programmed. [How] Fix the PWL backlight curve threshold/offset calculations Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Josip Pavic <Josip.Pavic@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: 3.2.120Aric Cyr1-1/+1
This DC update brings improvements in multiple areas. In summary, we highlight: - Fix display detection on HDMI ComboPHY - Drop SOC bounding box hookup - Fix DPCD values Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: [FW Promotion] Release 0.0.49Anthony Koo1-2/+3
- Add field for passing line time for a frame Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Add more Clock Sources to DCN2.1Sung Lee1-0/+10
[WHY] When enabling HDMI on ComboPHY, there are not enough clock sources to complete display detection. [HOW] Initialize more clock sources. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: correct some hdcp variable namingWenjing Liu6-17/+19
[why] In HDCP update stream config interface, some variables are named as xxx_supported, but in fact the variable indicates whether or not xxx_enabled. Correct the naming so it is less confusing to read the code. Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: George Shen <George.Shen@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Set power_gated to true for seamless boot pipe initLewis Huang1-0/+1
[Why] In seamless boot without a flip case, the flag power_gated didn't get cleared when resetting path mode because the plane_state is null. The following sequence will cause this issue: 1. OS call set mode to clone/extended 2. Reset path mode to remove edp [How] Set power gated default to true in seamless boot pipe Signed-off-by: Lewis Huang <Lewis.Huang@amd.com> Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: reuse current context instead of recreating oneBhawanpreet Lakha3-23/+30
[Why] Currently we discard the current context and recreate it. The current context is what is applied to the HW so we should be re-using this rather than creating a new context. Recreating the context can lead to mismatch between new context and the current context For example: gsl groups get changed when we create a new context this can cause issues in a multi display config (with flip immediate) because we don't align the existing gsl groups in the new and current context. If we reuse the current context the gsl group assignment stays the same. [How] Instead of discarding the current context, we instead just copy the current state and add/remove planes and streams. Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Add null pointer check to is_dig_enabled funcMichael Strauss1-1/+2
[WHY] Safeguarding as pointer may be null in diagnostic environment Signed-off-by: Michael Strauss <michael.strauss@amd.com> Reviewed-by: Sung Lee <Sung.Lee@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: initialize i2c speed if not initialized in dcnxxx__resource.cBrendan Steve Leder1-0/+4
Some dcnxxx__resource.c do not initialize the i2c speed; this patch adds the required initialization at dc_construct(). Signed-off-by: Brendan Steve Leder <brendanSteve.Leder@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Fix DPCD translation for LTTPR AUX_RD_INTERVALGeorge Shen1-3/+3
[Why] The translation between the DPCD value and the specified AUX_RD_INTERVAL in the DP spec do not match. [How] Update values to match the spec. Signed-off-by: George Shen <george.shen@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amd/display: Drop SOC bounding box hookup in DM/DCNicholas Kazlauskas6-330/+4
[Why] There aren't any ASIC where we use these binaries and they aren't useful for future use since it's inconvenient to extend and maintain these structures. [How] Drop the support from DM and DC for now. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Acked-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Hersen Wu <hersenxs.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-02drm/amdgpu: enable freesync for A+A configsChristian König2-3/+7
Some newer APUs can scanout directly from GTT, that saves us from allocating another bounce buffer in VRAM and enables freesync in such configurations. Without this patch creating a framebuffer from the imported BO will fail and userspace will fall back to a copy. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Shashank Sharma <shashank.sharma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-27 20:05:25 +0300