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2019-06-25Merge tag 'hisi-arm64-dt-for-5.3' of git://github.com/hisilicon/linux-hisi ↵Olof Johansson3-3/+461
into arm/dt ARM64: DT: Hisilicon SoCs DT updates for v5.3 * Hi3660 SoC and related boards: - Added CoreSight trace components * Hi6220 SoC and related boards: - Updated CoreSight funnel and replicator using new bindings to fix warning * tag 'hisi-arm64-dt-for-5.3' of git://github.com/hisilicon/linux-hisi: arm64: dts: hi3660: Add CoreSight support arm64: dts: hi6220: Update coresight DT bindings Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-25Merge tag 'arm-soc/for-5.3/devicetree-v2' of ↵Olof Johansson64-152/+104
https://github.com/Broadcom/stblinux into arm/dt This pull request contain Broadcom ARM-based SoCs Device Tree changes for 5.3 please pull the following: - Lukas enables DMA support for the BCM2835 (Raspberry Pi) SPI controller - Florian fixes a number of dtc W=1 warnings in the Broadcom DTS files and provides a fix for devices failing to boot after the removal of skelton.dtsi (that commit has been submitted as a separate fix) * tag 'arm-soc/for-5.3/devicetree-v2' of https://github.com/Broadcom/stblinux: ARM: dts: BCM5301X: Fix most DTC W=1 warnings ARM: dts: NSP: Fix the bulk of W=1 DTC warnings ARM: dts: BCM63xx: Fix DTC W=1 warnings ARM: dts: BCM53573: Fix DTC W=1 warnings ARM: dts: bcm-mobile: Fix most DTC W=1 warnings ARM: dts: Cygnus: Fix most DTC W=1 warnings ARM: dts: Fix BCM7445 DTC warnings ARM: bcm283x: Enable DMA support for SPI controller ARM: dts: bcm: Add missing device_type = "memory" property Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-23ARM: dts: BCM5301X: Fix most DTC W=1 warningsFlorian Fainelli28-84/+30
Fix the bulk of the unit_address_vs_reg warnings and unnecessary \#address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2019-06-23ARM: dts: NSP: Fix the bulk of W=1 DTC warningsFlorian Fainelli9-14/+11
Fix the bulk of the unit_address_vs_reg warnings and unnecessary \#address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2019-06-23ARM: dts: BCM63xx: Fix DTC W=1 warningsFlorian Fainelli2-7/+4
Fix the bulk of the unit_address_vs_reg warnings and unnecessary \#address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2019-06-23ARM: dts: BCM53573: Fix DTC W=1 warningsFlorian Fainelli5-13/+5
Fix the the unit_address_vs_reg warnings and unnecessary \#address-cells/#size-cells without "ranges" or child "reg" property warnings. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2019-06-23ARM: dts: bcm-mobile: Fix most DTC W=1 warningsFlorian Fainelli6-18/+18
Fix the bulk of the unit_address_vs_reg warnings and unnecessary \#address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2019-06-23ARM: dts: Cygnus: Fix most DTC W=1 warningsFlorian Fainelli3-11/+9
Fix the bulk of the unit_address_vs_reg warnings and unnecessary \#address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2019-06-23ARM: dts: Fix BCM7445 DTC warningsFlorian Fainelli2-5/+5
Fixes a number of unit_address_vs_reg warnings: DTC arch/arm/boot/dts/bcm7445-bcm97445svmb.dtb arch/arm/boot/dts/bcm7445.dtsi:66.6-225.4: Warning (unit_address_vs_reg): /rdb: node has a reg or ranges property, but no unit name arch/arm/boot/dts/bcm7445.dtsi:227.21-298.4: Warning (unit_address_vs_reg): /memory_controllers: node has a reg or ranges property, but no unit name arch/arm/boot/dts/bcm7445-bcm97445svmb.dts:9.9-14.4: Warning (unit_address_vs_reg): /memory: node has a reg or ranges property, but no unit name arch/arm/boot/dts/bcm7445.dtsi:255.10-275.5: Warning (simple_bus_reg): /memory_controllers/memc@1: simple-bus unit address format error, expected "80000" arch/arm/boot/dts/bcm7445.dtsi:277.10-297.5: Warning (simple_bus_reg): /memory_controllers/memc@2: simple-bus unit address format error, expected "100000" Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2019-06-23Merge tag 'tags/bcm2835-dt-next-2019-06-01' into devicetree/nextFlorian Fainelli1-0/+2
This pull requests enables DMA support for the main SPI controller on all Raspberry Pis. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2019-06-23ARM: bcm283x: Enable DMA support for SPI controllerLukas Wunner1-0/+2
Without this, the driver for the BCM2835 SPI controller uses interrupt mode instead of DMA mode, incurring a significant performance penalty. The Foundation's device tree has had these attributes for years, but for some reason they were never upstreamed. They were originally contributed by Noralf Trønnes and Martin Sperl: https://github.com/raspberrypi/linux/commit/25f3e064afc8 https://github.com/raspberrypi/linux/commit/e0edb52b47e6 The DREQ numbers 6 and 7 are documented in section 4.2.1.3 of: https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Lukas Wunner <lukas@wunner.de> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Martin Sperl <kernel@martin.sperl.org> Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Cc: Martin Sperl <kernel@martin.sperl.org> Cc: Noralf Trønnes <noralf@tronnes.org>
2019-06-19Merge tag 'ti-k3-soc-for-v5.3' of ↵Olof Johansson15-1/+896
git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into arm/dt Texas Instruments K3 SoC family changes for 5.3 - Add support for the new J721e SoC, includes basic peripherals needed for booting up the device - New peripheral support added for AM654x: * TI SCI irqchip * GPIO * MCU SRAM * R5Fs * MSMC RAM * SERDES and PCIe * tag 'ti-k3-soc-for-v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux: (26 commits) arm64: dts: ti: k3-j721e: Add the MCU SRAM node arm64: dts: ti: k3-j721e: Add interrupt controllers in wakeup domain arm64: dts: ti: k3-j721e: Add interrupt controllers in main domain arm64: dts: ti: k3-j721e-main: Add Main NavSS Interrupt controller node arm64: defconfig: Enable TI's J721E SoC platform arm64: dts: ti: Add support for J721E Common Processor Board soc: ti: Add Support for J721E SoC config option arm64: dts: ti: Add Support for J721E SoC dt-bindings: serial: 8250_omap: Add compatible for J721E UART controller dt-bindings: arm: ti: Add bindings for J721E SoC arm64: dts: ti: am654-base-board: Disable SERDES and PCIe arm64: dts: k3-am6: Add PCIe Endpoint DT node arm64: dts: k3-am6: Add PCIe Root Complex DT node arm64: dts: k3-am6: Add SERDES DT node arm64: dts: k3-am6: Add mux-controller DT node required for muxing SERDES arm64: dts: k3-am6: Add "socionext,synquacer-pre-its" property to gic_its arm64: dts: ti: k3-am65: Add MSMC RAM ranges in interconnect node arm64: dts: ti: k3-am65: Add R5F ranges in interconnect nodes arm64: dts: ti: k3-am65-mcu: Add the MCU RAM node arm64: dts: ti: k3-am65: Add MCU SRAM ranges in interconnect nodes ... Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-19Merge tag 'socfpga_dts_updates_for_v5.3' of ↵Olof Johansson3-15/+35
git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt SoCFPGA DTS updates for v5.3 - Use the new "altr,socfpga-stmmac-a10-s10" for the EMAC controllers on Arria10/Stratix10 - Add the ltc2497 i2c entry on the Arria10 devkit - Add the EMAC OCP reset property on the Arria10 * tag 'socfpga_dts_updates_for_v5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: dts: arria10: Add EMAC OCP reset property ARM: dts: socfpga: add ltc2497 on arria10 devkit arm64: dts: stratix10: use the "altr,socfpga-stmmac-a10-s10" binding ARM: dts: socfpga: use the "altr,socfpga-stmmac-a10-s10" binding Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-19arm64: dts: hi3660: Add CoreSight supportWanglai Shi2-0/+458
This patch adds DT bindings for the CoreSight trace components on hi3660, which is used by 96boards Hikey960. Signed-off-by: Wanglai Shi <shiwanglai@hisilicon.com> Reviewed-and-tested-by: Leo Yan <leo.yan@linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2019-06-19arm64: dts: hi6220: Update coresight DT bindingsLeo Yan1-3/+3
CoreSight DT bindings have been updated, thus the old compatible strings are obsolete and the drivers will report warning if DTS uses these obsolete strings. This patch switches to the new bindings for CoreSight dynamic funnel and static replicator, so can dismiss warning during initialisation. Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Guodong Xu <guodong.xu@linaro.org> Cc: Zhangfei Gao <zhangfei.gao@linaro.org> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Leo Yan <leo.yan@linaro.org> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2019-06-19Merge tag 'samsung-dt-5.3' of ↵Olof Johansson5-126/+142
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt Samsung DTS ARM changes for v5.3 1. Fixes for minor warnings. 2. Enable ADC on Exynos5410 Odroid XU board. * tag 'samsung-dt-5.3' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos: Add ADC node to Exynos5410 and Odroid XU ARM: dts: exynos: Raise maximum buck regulator voltages on Arndale Octa ARM: dts: exynos: Move CPU OPP tables out of SoC node on Exynos5420 Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-19Merge tag 'vexpress-updates-5.3' of ↵Olof Johansson2-3/+12
git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dt ARMv7 Vexpress updates for v5.3 1. Couple of updates switching to use new/updated bindings for CoreSight dynamic funnel components and NOR flash partition type 2. Disable NOR flash on Vexpress TC2 platform as it conflicts with CPU power management. This follows what we have on ARMv8 Juno platform and is required after recent commit that enabled CFI NOR FLASH in multi_v7 defconfig * tag 'vexpress-updates-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: ARM: dts: vexpress: set the right partition type for NOR flash arm: dts: vexpress-v2p-ca15_a7: disable NOR flash node by default ARM: dts: vexpress-v2p-ca15_a7: update coresight DT bindings Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-19Merge tag 'juno-updates-5.3' of ↵Olof Johansson3-6/+8
git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dt ARMv8 Juno updates for v5.3 Couple of updates switching to use new/updated bindings for CoreSight dynamic funnel components and NOR flash partition type * tag 'juno-updates-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: arm64: dts: juno: set the right partition type for NOR flash arm64: dts: juno: update coresight DT bindings Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-19Merge tag 'omap-for-v5.3/ti-sysc-dt-signed' of ↵Olof Johansson13-159/+394
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt ti-sysc dts changes for v5.3 We can now drop the custom dts property "ti,hwmods" for drivers that have the ti-sysc interconnect target module configured in dts. Let's start with a minimal changes to omap4 uart and mmc. We use omap4 as the starting point as it has runtime PM implemented and all the omap variants after that are based on it with similar clkctrl clock for the modules. More devices will be updated later on as they get tested. Note that these changes are based on the related ti-sysc driver changes. * tag 'omap-for-v5.3/ti-sysc-dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (21 commits) ARM: dts: Drop legacy custom hwmods property for omap4 mmc ARM: dts: Drop legacy custom hwmods property for omap4 uart bus: ti-sysc: Detect uarts also on omap34xx bus: ti-sysc: Do rstctrl reset handling in two phases bus: ti-sysc: Add support for disabling module without legacy mode bus: ti-sysc: Set ENAWAKEUP if available bus: ti-sysc: Handle swsup idle mode quirks bus: ti-sysc: Handle clockactivity for enable and disable bus: ti-sysc: Enable interconnect target module autoidle bit on enable bus: ti-sysc: Allow QUIRK_LEGACY_IDLE even if legacy_mode is not set bus: ti-sysc: Make OCP reset work for sysstatus and sysconfig reset bits bus: ti-sysc: Support 16-bit writes too bus: ti-sysc: Add support for missing clockdomain handling ARM: dts: dra71x: Disable usb4_tm target module ARM: dts: dra71x: Disable rtc target module ARM: dts: dra76x: Disable usb4_tm target module ARM: dts: dra76x: Disable rtc target module ARM: dts: dra76x: Update MMC2_HS200_MANUAL1 iodelay values ARM: dts: am57xx-idk: Remove support for voltage switching for SD card bus: ti-sysc: Handle devices with no control registers ... Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-19Merge tag 'omap-for-v5.3/dt-signed' of ↵Olof Johansson13-45/+372
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt dts changes for omap variants for v5.3 This series of changes improves support for few boards: - configure another lcd type for logicpd torpedo devkit - a series of updates for am335x phytec boards - configure mmc card detect pin for am335x-baltos * tag 'omap-for-v5.3/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: am335x-baltos: add support for MMC1 CD pin ARM: dts: am335x-baltos: Fix PHY mode for ethernet ARM: dts: Add support for phyBOARD-REGOR-AM335x ARM: dts: am335x-pcm-953: Remove eth phy delay ARM: dts: am335x-pcm-953: Update user led names ARM: dts: am335x-phycore-som: Enable gpmc node in dts files ARM: dts: am335x-phycore-som: Add emmc node ARM: dts: am335x phytec boards: Remove regulator node ARM: dts: Add LCD type 28 support to LogicPD Torpedo DM3730 devkit Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-19Merge tag 'arm-soc/for-5.3/devicetree-arm64' of ↵Olof Johansson2-0/+180
https://github.com/Broadcom/stblinux into arm/dt This pull request contains Broadcom ARM64-based SoCs Device Tree changes for 5.3, please pull the following: - Pramod adds the Device Tree nodes for thermal support on Stingray - Srinath adds the Device Tree nodes for both XHCI (host) and BDC (device) modes - Rayagonda adds the Device Tree node for slave I2C operation when Stingray operates as a SmartNIC * tag 'arm-soc/for-5.3/devicetree-arm64' of https://github.com/Broadcom/stblinux: arm64: dts: Stingray: Add NIC i2c device node arm64: dts: Add USB DT nodes for Stingray SoC arm64: dts: stingray: Add Stingray Thermal DT support. Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-19Merge tag 'v5.3-rockchip-dts64-1' of ↵Olof Johansson5-4/+135
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt PCIe for rockpro64, wifi+bt for Rock-PI4, spi for Rock960 family and a fix for the yet unused isp-iommus. * tag 'v5.3-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: add WiFi+BT support on ROCK Pi4 board arm64: dts: rockchip: fix isp iommu clocks and power domain arm64: dts: rockchip: Enable SPI1 on Ficus arm64: dts: rockchip: Enable SPI0 and SPI4 on Rock960 arm64: dts: rockchip: add PCIe nodes on rk3399-rockpro64 Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-19Merge tag 'v5.3-rockchip-dts32-1' of ↵Olof Johansson9-66/+1143
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt A lot more love for rk3288 in general and veyron specially with changes all over the place. * tag 'v5.3-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (21 commits) ARM: dts: rockchip: Split GPIO keys for veyron into multiple devices ARM: dts: rockchip: Add HDMI i2c unwedging for rk3288-veyron ARM: dts: rockchip: Add unwedge pinctrl entries for dw_hdmi on rk3288 ARM: dts: rockchip: Switch to builtin HDMI DDC bus on rk3288-veyron ARM: dts: rockchip: Add pin names for rk3288-veyron jaq, mickey, speedy ARM: dts: rockchip: fix pwm-cells for rk3288's pwm3 ARM: dts: rockchip: Configure the GPU thermal zone for mickey ARM: dts: rockchip: Use the GPU to cool CPU thermal zone of veyron mickey ARM: dts: rockchip: remove GPU 500 MHz OPP on rk3288 ARM: dts: rockchip: Use GPU as cooling device for the GPU thermal zone of the rk3288 ARM: dts: rockchip: Add #cooling-cells entry for rk3288 GPU ARM: dts: rockchip: Mark that the rk3288 timer might stop in suspend ARM: dts: rockchip: Add pin names for rk3288-veyron-jerry ARM: dts: rockchip: Add pin names for rk3288-veyron-minnie ARM: dts: raise GPU trip point temperature for speedy to 80 degC ARM: dts: rockchip: raise GPU trip point temperatures for veyron ARM: dts: rockchip: raise CPU trip point temperature for veyron to 100 degC ARM: dts: rockchip: Make rk3288-veyron-minnie run at hs200 ARM: dts: rockchip: Make rk3288-veyron-mickey's emmc work again ARM: dts: rockchip: Remove bogus 'i2s_clk_out' from rk3288-veyron-mickey ... Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-19arm64: qcom: qcs404: Add reset-cells to GCC nodeAndy Gross1-0/+1
This patch adds a reset-cells property to the gcc controller on the QCS404. Without this in place, we get warnings like the following if nodes reference a gcc reset: arch/arm64/boot/dts/qcom/qcs404.dtsi:261.38-310.5: Warning (resets_property): /soc@0/remoteproc@b00000: Missing property '#reset-cells' in node /soc@0/clock-controller@1800000 or bad phandle (referred from resets[0]) also defined at arch/arm64/boot/dts/qcom/qcs404-evb.dtsi:82.18-84.3 DTC arch/arm64/boot/dts/qcom/qcs404-evb-4000.dtb arch/arm64/boot/dts/qcom/qcs404.dtsi:261.38-310.5: Warning (resets_property): /soc@0/remoteproc@b00000: Missing property '#reset-cells' in node /soc@0/clock-controller@1800000 or bad phandle (referred from resets[0]) also defined at arch/arm64/boot/dts/qcom/qcs404-evb.dtsi:82.18-84.3 Signed-off-by: Andy Gross <agross@kernel.org> Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-19arm64: dts: sprd: Add Spreadtrum SD host controller supportBaolin Wang1-0/+35
Add one Spreadtrum SD host controller to support eMMC card for Spreadtrum SC9860 platform. Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-19Merge tag 'integrator-dts-v5.3-arm-soc' of ↵Olof Johansson8-0/+36
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into arm/dt DTS updates for the Integrator, target kernel v5.3. * tag 'integrator-dts-v5.3-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator: ARM: dts: vexpress: specify AFS partition ARM: dts: realview: specify AFS partition ARM: dts: versatile: specify AFS partition ARM: dts: integrator: specify AFS partition Signed-off-by: Olof Johansson <olof@lixom.net>
2019-06-19arm64: dts: ti: k3-j721e: Add the MCU SRAM nodeSuman Anna1-0/+8
Add the on-chip SRAM present within the MCU domain as a mmio-sram node. The K3 J721E SoCs have 1 MB of such memory. Any specific memory range within this RAM needed by a driver/software module ought to be reserved using an appropriate child node. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-19arm64: dts: ti: k3-j721e: Add interrupt controllers in wakeup domainLokesh Vutla1-0/+11
Wakeup domain in J721E SoC has an interrupt router connected to gpio in wakeup domain. Add DT node for this interrupt router. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-19arm64: dts: ti: k3-j721e: Add interrupt controllers in main domainLokesh Vutla1-0/+23
Main domain in J721E has the following interrupt controller instances: - Main Domain GPIO Interrupt router connected to gpio in main domain. - Under the Main Domain Navigator Subsystem(NAVSS) - Main Navss Interrupt Router connected to main navss inta and mailboxes. - Main Navss Interrupt Aggregator connected to main domain UDMASS Add DT nodes for the interrupt controllers available in main domain. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-19arm64: dts: ti: k3-j721e-main: Add Main NavSS Interrupt controller nodeSuman Anna1-0/+18
Add the Interrupt controller node for the Interrupt Router present within the Main NavSS module. This Interrupt Router can route 192 interrupts to the GIC_SPI in 3 sets of 64 interrupts each. Note that the last set is reserved for the host ID A72_3 for hypervisor usecases, so the node is added only with 2 sets for the Linux kernel context (host id A72_2). This is specified through the ti,sci-rm-range-girq property. Signed-off-by: Suman Anna <s-anna@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-19arm64: defconfig: Enable TI's J721E SoC platformNishanth Menon1-0/+1
Enable J721E SoC support from TI. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-19arm64: dts: ti: Add support for J721E Common Processor BoardNishanth Menon3-0/+81
Add Support for J721E Common Processor board support. The EVM architecture is as follows: +------------------------------------------------------+ | +-------------------------------------------+ | | | | | | | Add-on Card 1 Options | | | | | | | +-------------------------------------------+ | | | | | | +-------------------+ | | | | | | | SOM | | | +--------------+ | | | | | | | | | | | Add-on | +-------------------+ | | | Card 2 | | Power Supply | | Options | | | | | | | | | +--------------+ | <--- +------------------------------------------------------+ Common Processor Board Common Processor board is the baseboard that has most of the actual connectors, power supply etc. A SOM (System on Module) is plugged on to the common processor board and this contains the SoC, PMIC, DDR and basic high speed components necessary for functionality. Add-n card options add further functionality (such as additional Audio, Display, networking options). Note: A) The minimum configuration required to boot up the board is System On Module(SOM) + Common Processor Board. B) Since there is just a single SOM and Common Processor Board, we are maintaining common processor board as the base dts and SOM as the dtsi that we include. In the future as more SOM's appear, we should move common processor board as a dtsi and include configurations as dts. C) All daughter cards beyond the basic boards shall be maintained as overlays. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-19soc: ti: Add Support for J721E SoC config optionNishanth Menon1-0/+5
Add option to build J721E SoC specific components Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-19arm64: dts: ti: Add Support for J721E SoCNishanth Menon3-0/+450
The J721E SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable lower system costs of automotive applications such as infotainment, cluster, premium Audio, Gateway, industrial and a range of broad market applications. This SoC is designed around reducing the system cost by eliminating the need of an external system MCU and is targeted towards ASIL-B/C certification/requirements in addition to allowing complex software and system use-cases. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP, Two C66x floating point DSPs. * 3D GPU PowerVR Rogue 8XE GE8430 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual PRUs and dual RTUs * Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and up to two DPI interfaces. * Integrated Ethernet switch supporting up to a total of 8 external ports in addition to legacy Ethernet switch of up to 2 ports. * System MMU (SMMU) Version 3.0 and advanced virtualisation capabilities. * Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems, 16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL management. * Configurable L3 Cache and IO-coherent architecture with high data throughput capable distributed DMA architecture under NAVSS * Centralized System Controller for Security, Power, and Resource Management (DMSC) See J721E Technical Reference Manual (SPRUIL1, May 2019) for further details: http://www.ti.com/lit/pdf/spruil1 Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-19dt-bindings: serial: 8250_omap: Add compatible for J721E UART controllerNishanth Menon1-0/+1
J721e uses a UART controller that is compatible with AM654 UART. Introduce a specific compatible to help handle the differences if necessary. Cc: Sekhar Nori <nsekhar@ti.com> Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-19dt-bindings: arm: ti: Add bindings for J721E SoCNishanth Menon1-0/+3
The J721E SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable lower system costs of automotive applications such as infotainment, cluster, premium Audio, Gateway, industrial and a range of broad market applications. This SoC is designed around reducing the system cost by eliminating the need of an external system MCU and is targeted towards ASIL-B/C certification/requirements in addition to allowing complex software and system use-cases. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP, Two C66x floating point DSPs. * 3D GPU PowerVR Rogue 8XE GE8430 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual PRUs and dual RTUs * Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and up to two DPI interfaces. * Integrated Ethernet switch supporting up to a total of 8 external ports in addition to legacy Ethernet switch of up to 2 ports. * System MMU (SMMU) Version 3.0 and advanced virtualisation capabilities. * Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems, 16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL management. * Configurable L3 Cache and IO-coherent architecture with high data throughput capable distributed DMA architecture under NAVSS * Centralized System Controller for Security, Power, and Resource Management (DMSC) See J721E Technical Reference Manual (SPRUIL1, May 2019) for further details: http://www.ti.com/lit/pdf/spruil1 Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: ti: am654-base-board: Disable SERDES and PCIeKishon Vijay Abraham I1-0/+24
AM654 base board does not have any PCIe slots. Disable all the SERDES and PCIe instances. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: k3-am6: Add PCIe Endpoint DT nodeKishon Vijay Abraham I1-0/+26
Add PCIe Endpoint DT node. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: k3-am6: Add PCIe Root Complex DT nodeKishon Vijay Abraham I2-0/+54
Add PCIe Root Complex DT node. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: k3-am6: Add SERDES DT nodeKishon Vijay Abraham I1-0/+41
Add DT node for SERDES0 and SERDES1. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: k3-am6: Add mux-controller DT node required for muxing SERDESKishon Vijay Abraham I1-0/+7
Add mux-controller DT node as a child node of scm_conf. This is required for muxing SERDES between USB, PCIe and ICSS2 SGMII. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: k3-am6: Add "socionext,synquacer-pre-its" property to gic_itsKishon Vijay Abraham I1-0/+1
GIC_ITS used in AM654 platform has the same configuration as that of GIC_ITS used in Socionext SoCs. Add "socionext,synquacer-pre-its" property to get PCI MSI working. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: ti: k3-am65: Add MSMC RAM ranges in interconnect nodeRoger Quadros1-0/+1
Add the MSCM RAM address space to the ranges property of the cbass_main interconnect node so that the addresses can be translated properly. This fixes the probe failure in the sram driver for the MSMC RAM node. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: ti: k3-am65: Add R5F ranges in interconnect nodesSuman Anna1-0/+4
Add the address spaces for the R5F cores in MCU domain to the ranges property of the cbass_mcu interconnect node so that the addresses within the R5F nodes can be translated properly by the relevant OF address API. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: ti: k3-am65-mcu: Add the MCU RAM nodeSuman Anna1-0/+8
Add the on-chip SRAM present within the MCU domain as a mmio-sram node. The K3 AM65x SoCs have 512 KB of such memory. Any specific memory range within this RAM needed by a software module ought to be reserved using an appropriate child node. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: ti: k3-am65: Add MCU SRAM ranges in interconnect nodesSuman Anna1-0/+2
Add the address space for the MCU SRAM memory to the ranges property of the cbass_mcu interconnect node so that the addresses within the mcu_sram nodes and its children can be translated properly by the relevant OF address API. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: ti: am654-base-board: Add gpio_keys nodeKeerthy1-0/+27
There are 2 push buttons: SW5 and SW6 that are basically connected to WKUP_GPIO0_24 and WKUP_GPIO0_27 respectively. Add the respective nodes and the pinctrl data to set the mode to GPIO and Input. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: ti: am6-main: Add gpio nodesKeerthy1-0/+32
Add gpio0/1 nodes under main domain. They have 96 and 90 gpios respectively and all are capable of generating banked interrupts. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: ti: am6-wakeup: Add gpio nodeKeerthy1-0/+15
Add gpio0 node under wakeup domain. This has 56 gpios and all are capable of generating banked interrupts. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2019-06-17arm64: dts: ti: k3-am654: Add interrupt controllers in wakeup domainLokesh Vutla1-0/+11
Wakeup domain in AM654 SoC has an interrupt router connected to gpio in wakeup domain. Add DT node for this interrupt router. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-09-28 23:52:57 +0300