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2014-09-03drm/i915: make fbdev initialization asynchronous v2Jesse Barnes3-5/+9
This gets us out of our init code and out to userspace quite a bit faster, but does open us up to some bugs given the state of our init time locking. v2: switch to async_schedule (Chris) check with lockdep, seems happy (Jesse) move hotplug enable flag set to fbdev_initial_config (Jesse) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> [danvet: Rebase on top of the dev_priv->enable_hotplug_processing removal.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Init some CHV workarounds via LRIs in ring->init_context()Ville Syrjälä2-16/+44
Follow the BDW example and apply the workarounds touching registers which are saved in the context image through LRIs in the new ring->init_context() hook. This makes Mesa much happier and eg. glxgears doesn't hang after the first frame. Cc: Arun Siluvery <arun.siluvery@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [danvet: Add missing wa table initialization to avoid a functional conflict with Arun's wa table debugfs support.] Reviewed-by: "Barbalho, Rafael" <rafael.barbalho@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: trivial: remove unneed set to NULLGustavo Padovan1-1/+0
At this point of the code the obj var is already NULL, so we don't need to set it again to NULL. Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Warn about odd rps values on CHVVille Syrjälä1-0/+11
CHV wants even rps opcodes so print a warning of the min/max/rpe/rp1 values are odd, and warn if an odd value slips through to valleyview_set_rps() and truncate it to an even value. Also add a comment to chv_freq_opcode() to make sure no one changes the code without considering this requirement. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Deepak S <deepak.s@linux.intel.com> [danvet: Help git along in applying the patch, somehow it silently ended up in the vlv init_gt_powersave function.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03MAINTAINERS: Update Daniel Vetter's email addressDaniel Vetter1-1/+1
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
2014-09-03drm/i915/bdw: Render state init for ExeclistsOscar Mateo6-39/+135
The batchbuffer that sets the render context state is submitted in a different way, and from different places. We needed to make both the render state preparation and free functions outside accesible, and namespace accordingly. This mess is so that all LR, LRC and Execlists functionality can go together in intel_lrc.c: we can fix all of this later on, once the interfaces are clear. v2: Create a separate ctx->rcs_initialized for the Execlists case, as suggested by Chris Wilson. Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> v3: Setup ring status page in lr_context_deferred_create when the default context is being created. This means that the render state init for the default context is no longer a special case. Execute deferred creation of the default context at the end of logical_ring_init to allow the render state commands to be submitted. Fix style errors reported by checkpatch. Rebased. Signed-off-by: Thomas Daniel <thomas.daniel@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915/bdw: BDW Software TurboDaisy Sun5-39/+241
BDW supports GT C0 residency reporting in constant time unit. Driver calculates GT utilization based on C0 residency and adjusts RP frequency up/down accordingly. For offscreen workload specificly, set frequency to RP0. Offscreen task is not restricted by frame rate, it can be executed as soon as possible. Transcoding and serilized workload between CPU and GPU both need high GT performance, RP0 is a good option in this case. RC6 will kick in to compensate power consumption when GT is not active. v2: Rebase on recent drm-intel-nightly v3: Add flip timerout monitor, when no flip is deteced within 100ms, set frequency to RP0. Signed-off-by: Daisy Sun <daisy.sun@intel.com> [torourke: rebased on latest and resolved conflict] Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Populate mem_freq in init_gt_powerwave()Ville Syrjälä2-53/+43
init_clock_gating() is too late to read out the mem_freq. We already want to print out the GPU MHz numbers before it's called. Move the mem_freq setup to init_gt_powersave(). v2: Also kill the CHV_CZ_CLOCK_FREQ_MODE_* defines Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Deepak S <deepak.s@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: s, fb->bits_per_pixel/8, pixel_size, in primary plane codeVille Syrjälä1-4/+4
Use the pixel_size we got from drm_format_plane_cpp() instead of fb->bits_per_pixel/8 when computing the primary plane page/linear offsets. Avoids a few divs and makes the code more future proof against funky pixel formats where bits_per_pixel isn't well defined. This is what we already did in the sprite code. Note that the relevant sprite patch was commit ca320ac456099c29290568353d924157e626ede9 Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Wed Dec 19 12:14:22 2012 +0000 drm/i915: Use pixel size for computing linear offsets into a sprite This change was required on sprites because they support yuv formats which have fb->bits_per_pixel undefined. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> [danvet: Add Chris' software archeology as a note to the commit message.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Don't dereference fb when disabling primary planeVille Syrjälä1-6/+14
During driver init we may not have a valid framebuffer for the primary plane even though the plane is enabled due to failed BIOS fb takeover. This means we have to avoid dereferencing the fb in .update_primary_plane() when disabling the plane. The introduction of the primary plane rotation in commit d91a2cb8e5104233c02bbde539bd4ee455ec12ac Author: Sonika Jindal <sonika.jindal@intel.com> Date: Fri Aug 22 14:06:04 2014 +0530 drm/i915: Add 180 degree primary plane rotation support caused a regression by trying to look up the pixel format before we can be sure there's a valid fb available. This isn't entirely unsurprising since the rotation patches originally predate the change to the primary plane code that calls .update_primary_plane() also when disabling the plane: commit fdd508a6419217cce28213f3c9bd27c02a0d4c71 Author: Ville Syrjälä <ville.syrjala@linux.intel.com> Date: Fri Aug 8 21:51:11 2014 +0300 drm/i915: Call .update_primary_plane in intel_{enable, disable}_primary_hw_plane() v2: Warn but don't blow up when trying to enable a plane w/o an fb (Chris) Cc: Sonika Jindal <sonika.jindal@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915/bdw: Export workaround data to debugfsArun Siluvery3-0/+77
The workarounds that are applied are exported to a debugfs file; this is used to verify their state after the test case (reset or suspend/resume etc). This patch is only required to support i-g-t. Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915/bdw: Apply workarounds in render ring init functionArun Siluvery4-48/+87
For BDW workarounds are currently initialized in init_clock_gating() but they are lost during reset, suspend/resume etc; this patch moves the WAs that are part of register state context to render ring init fn otherwise default context ends up with incorrect values as they don't get initialized until init_clock_gating fn. v2: Add workarounds to golden render state This method has its own issues, first of all this is different for each gen and it is generated using a tool so adding new workaround and mainitaining them across gens is not a straightforward process. v3: Use LRIs to emit these workarounds (Ville) Instead of modifying the golden render state the same LRIs are emitted from within the driver. v4: Use abstract name when exporting gen specific routines (Chris) For: VIZ-4092 Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: FBC flush nuke for BDWRodrigo Vivi4-1/+22
According to spec FBC on BDW and HSW are identical without any gaps. So let's copy the nuke and let FBC really start compressing stuff. Without this patch we can verify with false color that nothing is being compressed. With the nuke in place and false color it is possible to see false color debugs. Unfortunatelly on some rings like BCS on BDW we have to avoid Bits 22:18 on LRIs due to a high risk of hung. So, when using Blt ring for frontbuffer rend cache would never been cleaned and FBC would stop compressing buffer. One alternative is to cache clean on software frontbuffer tracking. v2: Fix rebase conflict. v3: Do not clean cache on BCS ring. Instead use sw frontbuffer tracking. Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915/ddi: use struct for ddi buf translation tablesJani Nikula1-92/+97
Try to avoid confusion with ARRAY_SIZE()/2 and hdmi_level*2. Signed-off-by: Jani Nikula <jani.nikula@intel.com> [danvet: Resolve silent patch conflict (didn't even fail to build) with with Sonika's preceding patch to use the hsw_ddi_translations_fdi table to driver the fdi link training iteration loop. Also drop the double-write loop Damien spotted.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Rename defines for selection of ddi buffer translation slotSonika Jindal3-34/+16
Renaming the HSW-specific macros for ddi buffer translation slot to denote the slot and not the vswing/pre-emph values as they are platform-dependent. This patch is based on top of the patch series for renaming the DP training vswing/pre-emph defines: http://lists.freedesktop.org/archives/intel-gfx/2014-August/050407.html v2: Creating single macro with argument for slot number (Damien) v3: Adding macro for num of translation entries (Damien) Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915/dp: debug log whether backlight is being enabled or disabledJani Nikula1-1/+2
Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915/bdw: Let the memory controller do all the swizzlingDamien Lespiau1-1/+8
Previously, it was possible for the GPU memory accesses to be swizzled to try to optimize the fetches for tiled buffers. This swizzling was on top of what the memory controller in the uncore already does. With broadwell, we drop that GPU side swizzling, and the corresponding initialization in 3 units (GAM, GT, DE). All those bits are reserved, as specs put it: Before Gen8, there was a historical configuration control field to swizzle address bit[6] for in X/Y tiling modes. This was set in three different places: TILECTL[1:0], ARB_MODE[5:4], and DISP_ARB_CTL[14:13]" For Gen8 the swizzle fields are all reserved, and the CPU's memory controller performs all address swizzling modifications. This also means that user space doesn't have to manually swizzle when accessing tiled buffers from the CPU, and so we always return I915_BIT_6_SWIZZLE_NONE from i915_gem_detect_bit_6_swizzle(), which short-circuits the initialization of the registers mentionned above in i915_gem_init_swizzling(). v2: Refine the explanation a bit more (Daniel) v3: Make it BDW+ specific (Steve) Cc: Steve Aarnio <steve.j.aarnio@linux.intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> [danvet: Keep the actual code to set the tiling bits for now, in case some bios escaped to the wild that uses this - we'd need it for fastboot.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Add "Intel Corporation" as module authorDamien Lespiau1-0/+1
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Don't use a define when it's clearer to just put the valueDamien Lespiau2-3/+2
Instead of going through hoops, just put the driver author directly as DRM_AUTHOR() argument. This will also make it consistent when we add Intel to the list. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: improve assert_panel_unlockedJani Nikula1-7/+20
Fix assert_panel_unlocked for vlv/chv, and improve it a bit for non-LVDS. Also don't pretend it works for DDI. There's still work to do to get this right for eDP on PCH platforms, but this is a start. v2: WARN_ON(HAS_DDI) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915/bdw: Add BDW support in the i915 debugfs entryVedang Patel1-1/+1
The patch introduces fixes for the debugfs attributes emitted by the i915 driver for GEN8. Currently, it is not emitting the correct attributes which include the status of RC6 states. Change-Id: Ib2068a0cac9a5wq3f228e547fa1a097ad369d242df Signed-off-by: Vedang Patel <vedang.patel@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Differentiate between LLC or snooped for the userChris Wilson4-7/+11
Rather than describing an object as either "snooped or LLC", we can do better as we should know what machine we are running on! Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: send PCI_D3hot adapter opregion message on BDW RPM suspendPaulo Zanoni1-6/+22
On BDW we're seeing a problem that after we runtime resume, the outputs connected to DDI C are not detected: they don't appear in the SDEISR register and GMBUS transactions don't work. They stop working at the moment we call intel_opregion_notify_adapter() during runtime suspend, but they don't go back to work when we call the same function during runtime resume. They only work after we do a modeset and call intel_opregion_notify_encoder(), but this point is already too late. While debugging, I tried to pass PCI_D3hot which is the value that matches the spec, and it seems to have solved the problem. I couldn't find any explanation of why this solves the problem, but there's also no documented explanation - besides our code and git log - of why Haswell should use PCI_D1, so keep this for now in order to keep BDW runtime PM working. Also add a comment to point the fact that there's no spec documenting all the weirdness involved here. Cc: kristen.c.accardi@intel.com Testcase: igt/pm_rpm/drm-resources-equal Testcase: igt/pm_rpm/i2c Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: rename gen8_init_clock_gating to broadwell_init_clock_gatingPaulo Zanoni1-2/+2
Because CHV uses cherryview_init_clock_gating instead of gen8_init_clock_gating. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: call lpt_init_clock_gating on BDW tooPaulo Zanoni1-0/+2
Because BDW has WPT, which is equivalent to LPT. This is just like the CPT/PPT case. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: fix panel unlock register maskJani Nikula1-1/+1
Use the correct mask for the unlock bits. In theory this could have lead to incorrect asserts but this is unlikely in practise. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915/bdw: Don't execute context reset and switch with ExeclistsThomas Daniel2-4/+20
These two functions make no sense in an Logical Ring Context & Execlists world. v2: We got rid of lrc_enabled and centralized everything in the sanitized i915.enable_execlists instead. Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> v3: Rebased. Corrected a typo in comment for i915_switch_context and added a comment that it should not be called in execlist mode. Added WARN_ON if i915_switch_context is called in execlist mode. Moved check for execlist mode out of i915_switch_context and into callers. Added comment in context_reset explaining why nothing is done in execlist mode. Signed-off-by: Thomas Daniel <thomas.daniel@intel.com> [danvet: Simplify the patch subject so I can understand it.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Fix to Enable GT/PM InterruptsDeepak S1-5/+4
Programing GT IER interrupts was fumbled while enabling Interrupts for gen8 We forgot to program PM IER interrupt in gen8_gt_irq_postinstall based on the new re-worked interrupt routines. v2: Kill the loop and init GT interrupts individually (Ville) Signed-off-by: Deepak S <deepak.s@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [danvet: Adjust commit message as per discussion with Deepak.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915/bdw: Do not initialize PPGTT in the legacy way for execlistsThomas Daniel1-6/+6
A pending commit removes synchronous mode from switch_mm. This breaks execlists because switch_mm will always try to write to the legacy ring buffer. Return immediately from i915_ppgtt_init_gw in execlists mode. No longer check for execlists mode in gen8_ppgtt_enable() because this will no longer be called in execlists mode. Signed-off-by: Thomas Daniel <thomas.daniel@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Make wait-for-pending-flips more defensiveChris Wilson1-7/+5
Be sure to always flush a stuck pageflip even if we couldn't possibly expect one to be there. References: https://bugs.freedesktop.org/show_bug.cgi?id=82612 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Handle i915_ppgtt_put correctlyMichel Thierry1-4/+3
Unfortunately, the gem_obj/vma relationship is not symmetrical; a gem_obj can look up for the same vma more than once (where the ppgtt refcount is incremented), but will free the vma only once (i915_gem_free_object). This difference in refcount get/put means that the ppgtt is not removed after the context and vma are destroyed, because sometimes the refcount will never go back to zero. v2: Just move the ppgtt refcount into vma_create. OTC-Jira: VIZ-3719 Signed-off-by: Michel Thierry <michel.thierry@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Flatten intel_edp_panel_vdd_on()Ville Syrjälä1-4/+7
Less pointless indentation is always nice. There will be a bit more code in this function once the power sequencer locking is fixed. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Warn about want_panel_vdd in edp_panel_vdd_off_sync()Ville Syrjälä1-2/+5
If we force vdd off warn if someone is still using it. With this change the delayed vdd off work needs to check want_panel_vdd itself to make sure it doesn't try to turn vdd off when someone is using it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Replace big nested if block with early returnVille Syrjälä1-20/+20
Looks nicer. Not functional change. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> [danvet: Add "No functional change" as requested by Jani.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Add a note explaining vdd on/off handling in intel_dp_aux_ch()Ville Syrjälä1-0/+6
Add a comment to explain why we care about the current want_panel_vdd state in intel_dp_aux_ch(). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Rename edp vdd funcs for consistencyVille Syrjälä1-8/+13
edp_* are now the lower level functions and intel_edp_* the higher level ones. One should use them in pairs. v2: Don't return void (Jani) Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Use intel_edp_panel_vdd_on() in intel_dp_probe_mst()Ville Syrjälä1-1/+1
We want to use the higher level vdd on func here. Not a big deal yet (we'd just get the warn when things go awry) but when the locking gets fixed this becomes more important. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Parametrize PANEL_PORT_SELECT_VLVVille Syrjälä2-10/+5
Passing the port as a parameter to PANEL_PORT_SELECT_VLV results in neater code. Sadly the PCH port select bits aren't suitable for the same treatment and the resulting macro would be much uglier, so leave those defines as is. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915/bdw: Populate lrc with aliasing ppgtt if requiredThomas Daniel1-0/+5
A previous commit broke aliasing PPGTT for lrc, resulting in a kernel oops on boot. Add a check so that is full PPGTT is not in use the context is populated with the aliasing PPGTT. Issue: VIZ-4278 Signed-off-by: Thomas Daniel <thomas.daniel@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: honour forced connector modesChris Wilson1-21/+12
In the move over to use BIOS connector configs, we lost the ability to force a specific set of connectors on or off. Try to remedy that by dropping back to the old behavior if we detect a hard coded connector config that tries to enable a connector (disabling is easy!). Based on earlier patches by Jesse Barnes. v2: Remove Jesse's patch Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Don't save/restore RS when not usedBen Widawsky1-4/+6
v2: fix conflict on rebase. Cc: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Bring UP Power Wells before disabling RC6.Deepak S1-0/+6
We need do forcewake before Disabling RC6, This is what the BIOS expects while going into suspend. v2: updated commit message. (Daniel) Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Deepak S <deepak.s@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Print the pipe on which the vblank wait times outDamien Lespiau1-2/+4
Improve the debug message that tells us we've been waiting for a vblank that never arrived. Printing the pipe could lead a "doh!" moment where we've been waiting for a vblank on a pipe that was off for instance. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Thomas Wood <thomas.wood@intel.com> [danvet: Polish commit message a bit.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Use dev_priv as first argument of for_each_pipe()Damien Lespiau8-59/+60
Chris has decided that enough is enough. It's time to fixup dev Vs dev_priv. This is a modest contribution to the crusade. v2: Still use INTEL_INFO(), for the (mythical!) case we want to hardcode the info struct with defines (Chris) Rename the macro argument from 'dev' to 'dev_priv' (Jani) v3: Use names unlikely to be used as macro arguments (Chris) Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: don't check for i830 in vlv specific codeJani Nikula1-1/+1
Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915/bdw: Make sure error capture keeps working with ExeclistsOscar Mateo1-4/+18
Since the ringbuffer does not belong per engine anymore, we have to make sure that we are always recording the correct ringbuffer. TODO: This is only a small fix to keep basic error capture working, but we need to add more information for it to be useful (e.g. dump the context being executed). v2: Reorder how the ringbuffer is chosen to clarify the change and rename the variable, both changes suggested by Chris Wilson. Also, add the TODO comment to the code, as suggested by Daniel. Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Suppress a WARN on reading an object back for a GPU hangChris Wilson1-1/+4
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Remove num_pages parameter to i915_error_object_create()Chris Wilson1-15/+10
For cleanliness, i915_error_object_create() was written to handle the NULL pointer in a central location. The macro that wrapped it and passed it a num_pages to use, was not safe. As we now never limit the num_pages to use (we did so at one point to only capture the first page of the context), we can remove the redundant macro and be NULL safe again. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: John Harrison <John.C.Harrison@Intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: Do not access stolen memory directly by the CPU, even for error ↵Chris Wilson1-19/+31
capture For stolen pages, since it is verboten to access them directly on many architectures, we have to read them through the GTT aperture. If they are not accessible through the aperture, then we have to abort. This was complicated by commit 8b6124a633d8095b0c8364f585edff9c59568a96 Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Thu Jan 30 14:38:16 2014 +0000 drm/i915: Don't access snooped pages through the GTT (even for error capture) and the desire to use stolen memory for ringbuffers, contexts and batches in the future. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-03drm/i915: switch off backlight for backlight class 0 brightnessJani Nikula1-1/+2
Make backlight class sysfs brightness 0 value switch off the backlight for connectors that have the backlight_power callback defined. For eDP, this has the similar caveats regarding power savings as bl_power as only the power sequencer backlight control is switched off. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed_by: Clinton Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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