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2021-01-29drm/i915: Nuke not needed members of dram_infoJosé Roberto de Souza3-42/+12
Valid, ranks and bandwidth_kbps are set into dram_info but are not used anywhere else so nuking it. Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210128164312.91160-1-jose.souza@intel.com
2021-01-28drm/i915: Fix the MST PBN divider calculationImre Deak1-1/+3
Atm the driver will calculate a wrong MST timeslots/MTP (aka time unit) value for MST streams if the link parameters (link rate or lane count) are limited in a way independent of the sink capabilities (reported by DPCD). One example of such a limitation is when a MUX between the sink and source connects only a limited number of lanes to the display and connects the rest of the lanes to other peripherals (USB). Another issue is that atm MST core calculates the divider based on the backwards compatible DPCD (at address 0x0000) vs. the extended capability info (at address 0x2200). This can result in leaving some part of the MST BW unused (For instance in case of the WD19TB dock). Fix the above two issues by calculating the PBN divider value based on the rate and lane count link parameters that the driver uses for all other computation. Bugzilla: https://gitlab.freedesktop.org/drm/intel/-/issues/2977 Cc: Lyude Paul <lyude@redhat.com> Cc: Ville Syrjala <ville.syrjala@intel.com> Cc: <stable@vger.kernel.org> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjala <ville.syrjala@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125173636.1733812-2-imre.deak@intel.com
2021-01-28drm/dp/mst: Export drm_dp_get_vc_payload_bw()Imre Deak2-6/+19
This function will be needed by the next patch where the driver calculates the BW based on driver specific parameters, so export it. At the same time sanitize the function params, passing the more natural link rate instead of the encoding of the same rate. v2: - Fix function documentation. (Lyude) Cc: Lyude Paul <lyude@redhat.com> Cc: Ville Syrjala <ville.syrjala@intel.com> Cc: <stable@vger.kernel.org> Cc: dri-devel@lists.freedesktop.org Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Lyude Paul <lyude@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125173636.1733812-1-imre.deak@intel.com
2021-01-28drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MSTSean Paul1-11/+1
The HDCP 1.4 spec does not require the QUERY_STREAM_ENCRYPTION_STATUS check, it was always a nice-to-have. After deploying this across various devices, we've determined that some MST bridge chips do not properly support this call for HDCP 1.4 (namely Synaptics and Realtek). I had considered creating a quirk for this, but I think it's more prudent to just disable the check entirely since I don't have an idea how widespread support is. Changes in v2: -Rebased on -tip Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210106223909.34476-1-sean@poorly.run #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20210121172620.33066-1-sean@poorly.run
2021-01-28drm/i915/display: Prevent double YUV range correction on HDR planesAndres Calderon Jaramillo2-55/+12
Prevent the ICL HDR plane pipeline from performing YUV color range correction twice when the input is in limited range. This is done by removing the limited-range code from icl_program_input_csc(). Before this patch the following could happen: user space gives us a YUV buffer in limited range; per the pipeline in [1], the plane would first go through a "YUV Range correct" stage that expands the range; the plane would then go through the "Input CSC" stage which would also expand the range because icl_program_input_csc() would use a matrix and an offset that assume limited-range input; this would ultimately cause dark and light colors to appear darker and lighter than they should respectively. This is an issue because if a buffer switches between being scanned out and being composited with the GPU, the user will see a color difference. If this switching happens quickly and frequently, the user will perceive this as a flickering. [1] https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-icllp-vol12-displayengine_0.pdf#page=281 Cc: stable@vger.kernel.org Signed-off-by: Andres Calderon Jaramillo <andrescj@chromium.org> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201215224219.3896256-1-andrescj@google.com
2021-01-28drm/i915: WARN if plane src coords are too bigVille Syrjälä2-0/+11
Inform us if we're buggy and are about to exceed the size of the bitfields in the plane TILEOFF/OFFSET registers. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210111163711.12913-2-ville.syrjala@linux.intel.com Reviewed-by: Karthik B S <karthik.b.s@intel.com>
2021-01-27drm/i915/display/vrr: Skip the VRR HW state readout on DSI transcoderManasi Navare1-1/+1
DSI transcoder does not support VRR and hence skip the HW state readout if its a DSI transcoder. Fixes: c7f0f4372b30 ("drm/i915/display: Add HW state readout for VRR") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210126185224.32340-1-manasi.d.navare@intel.com
2021-01-26drm/i915/adl_s: Update combo PHY master/slave relationshipsMatt Roper1-2/+9
ADL-S switches up which PHYs are considered a master to other PHYs; PHY-C is no longer a master, but PHY-D is now. Bspec: 49291 Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125140753.347998-11-aditya.swarup@intel.com
2021-01-26drm/i915/adl_s: Add vbt port and aux channel settings for adlsAditya Swarup1-11/+46
- ADL-S driver internal mapping uses PORT D, E, F, G for Combo phy B, C, D and E. - Add ADLS specific port mappings for vbt port dvo settings. - Select appropriate AUX CH specific to ADLS based on port mapping. Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125140753.347998-10-aditya.swarup@intel.com
2021-01-26drm/i915/adl_s: Add adl-s ddc pin mappingAditya Swarup3-2/+35
ADL-S requires TC pins to set up ddc for Combo PHY B, C, D and E. Combo PHY A still uses the old ddc pin mapping. From VBT, ddc pin info suggests the following mapping: VBT DRIVER DDI B->ddc_pin=2 should translate to PORT_D->0x9 DDI C->ddc_pin=3 should translate to PORT_E->0xa DDI D->ddc_pin=4 should translate to PORT_F->0xb DDI E->ddc_pin=5 should translate to PORT_G->0xc Adding pin map to facilitate this translation as we cannot use existing icl ddc pin map due to conflict with DDI B and DDI C info. Bspec:20124 v2: Replace IS_ALDERLAKE_S() with HAS_PCH_ADP() as the pin map pairing depends on the PCH being used rather than the platform.(mdroper) v3: - Modify adls_port_to_ddc_pin() to make PHY_A the special case for check, else return pin mapping based on correct arithmetic with phy offset. Remove redundant platform checks and use HAS_PCH_ADP() instead of IS_ALDERLAKE_S() in intel_hdmi_ddc_pin().(mdroper) Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125140753.347998-9-aditya.swarup@intel.com
2021-01-26drm/i915/adl_s: Initialize display for ADL-SAditya Swarup1-1/+7
Initialize display outputs for ADL-S. ADL-S has 5 display outputs -> 1 eDP, 2 HDMI and 2 DP++ outputs. v2: - Use PORT_TCx instead of PORT_D,E.. to stay consistent with other platforms.(mdroper) Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125140753.347998-8-aditya.swarup@intel.com
2021-01-26drm/i915/adl_s: Configure Port clock registers for ADL-SAditya Swarup3-24/+72
Add changes to configure port clock registers for ADL-S. Combo phy port clocks are configured by DPCLKA_CFGCR0 and DPCLKA_CFGCR1 registers. The DDI to internal clock mappings in DPCLKA_CFGCR0 register for ADL-S translates to DDI A -> DDIA DDI B -> USBC1 DDI I -> USBC2 For DPCLKA_CFGCR1 DDI J -> USBC3 DDI K -> USBC4 Bspec: 50287 Bspec: 53812 Bspec: 53723 v2: Replace I915_READ() with intel_de_read().(Jani) v3: - Use reg variable to assign ADLS specific registers inorder to replace branching with intel_de_read/write() calls.(mdroper) - Reuse icl_get_ddi_pll() for ADLS to fix issue with updating active dpll on driver load.(aswarup) Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125140753.347998-7-aditya.swarup@intel.com
2021-01-26drm/i915/adl_s: Configure DPLL for ADL-SAditya Swarup2-6/+54
Add changes for configuring DPLL for ADL-S - Reusing DG1 DPLL 2 & DPLL 3 for ADL-S - Extend CNL macro to choose DPLL_ENABLE for ADL-S. - Select CFGCR0 and CFGCR1 for ADL-S plls. On BSpec: 53720 PLL arrangement dig for adls: DPLL2 cfgcr is programmed using _ADLS_DPLL3_CFGCR(0/1) DPLL3 cfgcr is programmed using _ADLS_DPLL4_CFGCR(0/1) v2 (Lucas): add missing update_ref_clks Bspec: 50288 Bspec: 50289 Bspec: 49443 v3 : Adding another bit to HDPORT_DPLL_USED_MASK bitfield for DPLL3_USED.(mdroper) Bspec: 53707 v4: BSpec 53723 has been updated with note - DPLL2 is controlled by DPLL4 CFGCR 0/1.(mdroper) Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125140753.347998-6-aditya.swarup@intel.com
2021-01-26drm/i915/adl_s: Add PHYs for Alderlake SAnusha Srivatsa2-6/+11
Alderlake-S has 5 combo phys, add reg definitions for combo phys and update the port to phy helper for ADL-S. v2: - Change IS_GEN() >= 12 to IS_TIGERLAKE() in intel_phy_is_tc() and return false for platforms RKL,DG1 and ADLS.(mdroper) Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125140753.347998-5-aditya.swarup@intel.com
2021-01-26drm/i915/adl_s: Add Interrupt SupportAnusha Srivatsa1-2/+1
ADLS follows ICP/TGP like interrupts. v2: Use "INTEL_PCH_TYPE(dev_priv) >= PCH_ICP" of hpd_icp (Lucas) Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125140753.347998-4-aditya.swarup@intel.com
2021-01-26drm/i915/adl_s: Add PCH supportAnusha Srivatsa2-1/+10
Add support for Alderpoint(ADP) PCH used with Alderlake-S. v2: - Use drm_dbg_kms and drm_WARN_ON based on Jani's feedback.(aswarup) Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Caz Yokoyama <caz.yokoyama@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125140753.347998-3-aditya.swarup@intel.com
2021-01-26x86/gpu: Add Alderlake-S stolen memory supportCaz Yokoyama1-0/+1
Alderlake-S is a Gen 12 based hybrid processor architecture. As it belongs to Gen 12 family, it uses the same GTT stolen memory settings like its predecessors - ICL(Gen 11) and TGL(Gen 12). Inherit gen11 and gen 9 quirks for determining base and size of stolen memory. Bspec: 52055 Bspec: 49589 Bspec: 49636 Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: x86@kernel.org Cc: Ingo Molnar <mingo@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Borislav Petkov <bp@suse.de> Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Borislav Petkov <bp@suse.de> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210126001744.29442-2-aditya.swarup@intel.com
2021-01-26drm/i915: Do a bit more initial readout for dbufVille Syrjälä2-6/+48
Readout the dbuf related stuff during driver init/resume and stick it into our dbuf state. v2: Keep crtc_state->wm.skl.ddb Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122205633.18492-9-ville.syrjala@linux.intel.com
2021-01-26drm/i915: Encapsulate dbuf state handling harderVille Syrjälä5-271/+140
In order to make the dbuf state computation less fragile let's make it stand on its own feet by not requiring someone to peek into a crystall ball ahead of time to figure out which pipes need to be added to the state under which potential future conditions. Instead we compute each piece of the state as we go along, and if any fallout occurs that affects more than the current set of pipes we add the affected pipes to the state naturally. That requires that we track a few extra thigns in the global dbuf state: dbuf slices for each pipe, and the weight each pipe has when distributing the same set of slice(s) between multiple pipes. Easy enough. We do need to follow a somewhat careful sequence of computations though as there are several steps involved in cooking up the dbuf state. Thoguh we could avoid some of that by computing more things on demand instead of relying on earlier step of the algorithm to have filled it out. I think the end result is still reasonable as the entire sequence is pretty much consolidated into a single function instead of being spread around all over. The rough sequence is this: 1. calculate active_pipes 2. calculate dbuf slices for every pipe 3. calculate total enabled slices 4. calculate new dbuf weights for any crtc in the state 5. calculate new ddb entry for every pipe based on the sets of slices and weights, and add any affected crtc to the state 6. calculate new plane ddb entries for all crtcs in the state, and add any affected plane to the state so that we'll perform the requisite hw reprogramming And as a nice bonus we get to throw dev_priv->wm.distrust_bios_wm out the window. v2: Keep crtc_state->wm.skl.ddb Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122205633.18492-8-ville.syrjala@linux.intel.com
2021-01-26drm/i915: Extract intel_crtc_dbuf_weights()Ville Syrjälä1-55/+88
Extract the code to calculate the weights used to chunk up the dbuf between pipes. There's still extra stuff in there that shouldn't be there and must be moved out, but that requires a bit more state to be tracked in the dbuf state. v2: Keep crtc_state->wm.skl.ddb Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122205633.18492-7-ville.syrjala@linux.intel.com
2021-01-26drm/i915: Add pipe ddb entries into the dbuf stateVille Syrjälä2-11/+12
The dbuf state will be where we collect all the inter-pipe dbuf allocation stuff. Start by adding the actual per-pipe ddb entries there. Originally the plan was to move them there outright, but that no longer works as we're no longer guaranteed to have a dbuf state when it comes time to sanity check the ddb overlaps in skl_commit_modeset_enables(). I think when I wrote this originally we did the watermark/ddb calculation last, and so we couldn't have any crtcs in the state w/o also having the dbuf state. But that has since changed and we do the watermark/ddb calculation much earlier, and thus it is now possible to commit crtcs w/o a dbuf state. So we keep another copy of the information in the crtc state. v2: Rebase v3: Duplicate the entries instead of moving Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122205633.18492-6-ville.syrjala@linux.intel.com
2021-01-26drm/i915: Introduce skl_ddb_entry_for_slices()Ville Syrjälä1-37/+18
Generalize icl_get_first_dbuf_slice_offset() into something that just gives us the start+end of the dbuf chunk covered by the specified slices as a standard ddb entry. Initial idea was to use it during readout as well, but we shall see. Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122205633.18492-5-ville.syrjala@linux.intel.com
2021-01-26drm/i915: Introduce intel_dbuf_slice_size()Ville Syrjälä2-16/+21
Put the code into a function with a descriptive name. Also relocate the code a bit help future work. Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122205633.18492-4-ville.syrjala@linux.intel.com
2021-01-26drm/i915: Pass the crtc to skl_compute_dbuf_slices()Ville Syrjälä1-12/+10
skl_compute_dbuf_slices() has no use for the crtc state, so just pass the crtc itself. Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122205633.18492-3-ville.syrjala@linux.intel.com
2021-01-26drm/i915: Extract intel_crtc_ddb_weight()Ville Syrjälä1-18/+27
skl_ddb_get_pipe_allocation_limits() doesn't care how the weights for distributing the ddb are caclculated for each pipe. Put that calculation into a separate function so that such mundane details are hidden from view. v2: s/adjusted_mode/pipe_mode/ Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122205633.18492-2-ville.syrjala@linux.intel.com
2021-01-26drm/i915: Fix vblank evasion with vrrVille Syrjälä1-1/+4
With vrr enabled the hardware no longer latches the registers automagically at vblank start. The point at which it will do the latching even when no push has been sent is the vmax decision boundary. That is the thing we need to evade to avoid our register latching to get split between two frames. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-18-manasi.d.navare@intel.com
2021-01-26drm/i915: Fix vblank timestamps with VRRVille Syrjälä4-6/+34
To get sensible vblank timestamping behaviour we need to feed the vmax based timings to the vblank code, otherwise it'll chop off the scanline counter when it exceeds the minumum vtotal. Additionally with VRR we have three cases to consider when we generate the vblank timestamp: 1) we are in vertical active -> nothing special needs to be done, just return the current scanout position and the core will calculate the timestamp corresponding to the past time when the current vertical active started 2) we are in vertical blank and no push has been sent -> the hardware will keep extending the vblank presumably to its maximum length, so we make the timestmap match the expected time when the max length vblank will end. Since the timings used for this are now based on vmax nothing special actually needs to be done 3) we are in vblank and a push has been sent so the vblank is about to terminate -> presumably we want the timestmap to accurately reflect when the vblank will terminate, so we use the sampled frame timestamp vs. current timestamp to guesstimate how far along the vblank exit we are, and then we adjust the reported scanout position accordingly so that the core will see that the vblank is close to ending. v2: * Fix the else if (use_scanline_Counter) (Manasi) Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-17-manasi.d.navare@intel.com
2021-01-26drm/i915: Add vrr state dumpVille Syrjälä1-0/+7
Dump vrr state alongside everything else. Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-16-manasi.d.navare@intel.com
2021-01-26drm/i915/display: Helpers for VRR vblank min and max startVille Syrjälä2-0/+38
With VRR the earliest the registers can get latched are at flipline decision boundary, calculate that as vrr_vmin_vblank_start() and the latest the regsiters can get latched are vmax decision boundary calculate that as vrr_vmax_vblank_start() v2: * Remove TODO and adjust extra scanline const (Manasi) Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-15-manasi.d.navare@intel.com
2021-01-26drm/i915/display: Add HW state readout for VRRManasi Navare3-0/+26
This functions gets the VRR config from the VRR registers to match the crtc state variables for VRR. v2: * Rebase (Manasi) * Use HAS_VRR (Jani N) v3: * Get pipeline_full, flipline (Ville) Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-14-manasi.d.navare@intel.com
2021-01-26drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP SinkManasi Navare2-1/+20
If VRR is enabled, the sink should ignore MSA parameters and regenerate incoming video stream without depending on these parameters. Hence set the MSA_TIMING_PAR_IGNORE_EN bit if VRR is enabled. Reset this bit on VRR disable. v2: * ACtually set the dpcd msa ignore bit (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-13-manasi.d.navare@intel.com
2021-01-26drm/i915/display/vrr: Disable VRR in modeset disable pathManasi Navare3-0/+16
This patch disables the VRR enable and VRR PUSH bits in the HW during commit modeset disable sequence. Thsi disable will happen when the port is disabled or when the userspace sets VRR prop to false and requests to disable VRR. v2: * Use intel_de_rmw (Jani N) v3: * Remove rmw (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-12-manasi.d.navare@intel.com
2021-01-26drm/i915/display/vrr: Send VRR push to flip the frameManasi Navare3-0/+18
VRR achieves vblank stretching using the HW PUSH functionality. So once the VRR is enabled during modeset then for each flip request from userspace, in the atomic tail pipe_update_end() we need to set the VRR push bit in HW for it to terminate the vblank at configured flipline or anytime after flipline or latest at the Vmax. The HW clears the PUSH bit after the double buffer updates are completed. v2: * Move send push to after irq en (Manasi) * Call send push unconditionally (Jani N) v3: * Stall w.r.t Vrr vmax (Manasi, Gary Smith) v4: * Remove the rmw (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Gary Smith <gary.k.smith@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-11-manasi.d.navare@intel.com
2021-01-26drm/i915/display/vrr: Configure and enable VRR in modeset enableManasi Navare3-0/+28
This patch computes the VRR parameters from VRR crtc states and configures them in VRR registers during CRTC enable in the modeset enable sequence. v2: * Remove initialization to 0 (Jani N) * Use correct pipe %c (Jani N) v3: * Remove debug prints (Ville) * Use cpu_trans instead of pipe for TRANS_VRR regs (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-10-manasi.d.navare@intel.com
2021-01-26drm/i915: Rename VRR_CTL reg fieldsVille Syrjälä1-7/+7
Give the pipeline full line count bits more descriptive names Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-9-manasi.d.navare@intel.com
2021-01-26drm/i915/display: VRR + DRRS cannot be enabled togetherVille Syrjälä1-0/+3
If VRR is enabled, DRRS cannot be enabled, so make this check in atomic check. Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-8-manasi.d.navare@intel.com
2021-01-26drm/i915/display/dp: Do not enable PSR if VRR is enabledManasi Navare1-0/+7
Even though our HW supports PSR + VRR, the available panels do not work reliably with PSR and VRR together. So if user requested VRR and is supported by HW enable that and do not enable PSR in that case. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-7-manasi.d.navare@intel.com
2021-01-26drm/i915/display/dp: Compute VRR state in atomic_checkManasi Navare5-0/+95
This forces a complete modeset if vrr drm crtc state goes from enabled to disabled and vice versa. This patch also computes vrr state variables from the mode timings and based on the vrr property set by userspace as well as hardware's vrr capability. v2: *Rebase v3: * Vmin = max (vtotal, vmin) (Manasi) v4: * set crtc_state->vrr.enable = 0 for disable request v5: * drm_dbg_kms, squash crtc states def patch (Jani N) v6: * Move vrr modeset check to separate function (Jani N) v7: * Ville's fixes - vmin, vmax rename, fix rounding dir * Add pipeline full, flipline to crtc state * Pass conn state to vrr_compute_config (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-6-manasi.d.navare@intel.com
2021-01-26drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp()Ville Syrjälä1-14/+24
Extract intel_crtc_scanlines_since_frame_timestamp() from __intel_get_crtc_scanline_from_timestamp(). We'll reuse this for VRR vblank timestamps. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-5-manasi.d.navare@intel.com
2021-01-26drm/i915: Extract intel_mode_vblank_start()Ville Syrjälä1-3/+11
We want to calculate the vblank_start for vblank evasion differently for vrr. To make that nicer lets first extract the current non-vrr case to a helper. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-4-manasi.d.navare@intel.com
2021-01-26drm/i915: Store framestart_delay in dev_privVille Syrjälä2-11/+14
The vrr calculations will need to know the framestart delay value we use. Currently we program it always to zero, but should that change we probably want to stash it somewhere. Could stick it into the crtc_state I suppose, but since we never change it let's just stuff it into dev_priv for now. v2: * Rebase on drm-tip (Manasi) v3: * Framestart_delay as 1 - 4 to align with HW Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-3-manasi.d.navare@intel.com
2021-01-26drm/i915/display/dp: Attach and set drm connector VRR propertyAditya Swarup2-2/+10
This function sets the VRR property for connector based on the platform support, EDID monitor range and DP sink DPCD capability of outputing video without msa timing information. v8: * Use HAS_VRR, remove drm_conn declaration (Jani N) * Fix typos in Comment (Jani N) v7: * Move the helper to separate file (Manasi) v6: * Remove unset of prop v5: * Fix the vrr prop not being set in kernel (Manasi) * Unset the prop on connector disconnect (Manasi) v4: * Rebase (Mansi) v3: * intel_dp_is_vrr_capable can be used for debugfs, make it non static (Manasi) v2: * Just set this in intel_dp_get_modes instead of new hook (Jani) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122232647.22688-2-manasi.d.navare@intel.com
2021-01-26drm/i915/display/vrr: Create VRR file and add VRR capability checkManasi Navare4-0/+49
We create a new file for all VRR related helpers. Also add a function to check vrr capability based on platform support, DPCD bits and EDID monitor range. v2: * Remove author (Jani N) * Define HAS_VRR (Jani N) * Ensure intel_dp can be obtained from conn (Jani N) v3: * Fix the header indent (Manasi) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125200818.2015-1-manasi.d.navare@intel.com
2021-01-22drm/i915/tgl: Add Clear Color support for TGL Render DecompressionRadhakrishna Sripada4-5/+116
Render Decompression is supported with Y-Tiled main surface. The CCS is linear and has 4 bits of data for each main surface cache line pair, a ratio of 1:256. Additional Clear Color information is passed from the user-space through an offset in the GEM BO. Add a new modifier to identify and parse new Clear Color information and extend Gen12 render decompression functionality to the newly added modifier. v2: Fix has_alpha flag for modifiers, omit CC modifier during initial plane config(Matt). Fix Lookup error. v3: Fix the panic while running kms_cube v4: Add alignment check and reuse the comments for ge12_ccs_formats(Matt) v5: Fix typos and wrap comments(Matt) v6: - Use format block descriptors to get the subsampling calculations for the CCS surface right. - Use helpers to convert between main and CCS surfaces. - Prevent coordinate checks for the CC surface. - Simplify reading CC value from surface map, add description of CC val layout. - Remove redundant ccval variable from skl_program_plane(). v7: - Move the CC value readout after syncing against any GPU write on the FB obj (Nanley, Chris) - Make sure the CC value readout works on platforms w/o struct pages (dGFX) and other non-coherent platforms wrt. CPU reads (none atm). (Chris) v8: - Rebase on the function param order change of i915_gem_object_read_from_page(). - Clarify code comment on the clear color value format and the required FB obj pinning/syncing by the caller. - Remove redundant variables in intel_atomic_prepare_plane_clear_colors(). v9: - Fix s/sizeof(&ccval)/sizeof(ccval)/ typo. Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Ville Syrjala <ville.syrjala@intel.com> Cc: Shashank Sharma <shashank.sharma@intel.com> Cc: Rafael Antognolli <rafael.antognolli@intel.com> Cc: Nanley G Chery <nanley.g.chery@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210115213952.1040398-1-imre.deak@intel.com
2021-01-22drm/i915/gem: Add a helper to read data from a GEM object pageImre Deak2-0/+73
Add a simple helper to read data with the CPU from the page of a GEM object. Do the read either via a kmap if the object has struct pages or an iomap otherwise. This is needed by the next patch, reading a u64 value from the object (w/o requiring the obj to be mapped to the GPU). Suggested by Chris. v2 (Chris): - Sanitize the type and order of func params. - Avoid consts requiring too many casts. - Use BUG_ON instead of WARN_ON, simplify the conditions. - Fix __iomem sparse errors. - Leave locking/syncing/pinning up to the caller, require only that the caller has pinned the object pages. - Check for iomem backing store before reading via an iomap. v3: - Fix offset passed to io_mapping_map_wc() missing a mem.region.start delta. (Chris, Matthew) Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Matthew Auld <matthew.william.auld@gmail.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20210120213834.1435710-1-imre.deak@intel.com
2021-01-22drm/framebuffer: Format modifier for Intel Gen 12 render compression with ↵Radhakrishna Sripada1-0/+19
Clear Color Gen12 display can decompress surfaces compressed by render engine with Clear Color, add a new modifier as the driver needs to know the surface was compressed by render engine. V2: Description changes as suggested by Rafael. V3: Mention the Clear Color size of 64 bits in the comments(DK) v4: Fix trailing whitespaces v5: Explain Clear Color in the documentation. v6: Documentation Nitpicks(Nanley) Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Kalyan Kondapally <kalyan.kondapally@intel.com> Cc: Rafael Antognolli <rafael.antognolli@intel.com> Cc: Nanley Chery <nanley.g.chery@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210114201314.783648-2-imre.deak@intel.com
2021-01-22drm/i915/hdcp: Fix uninitialized symbolAnshuman Gupta1-10/+10
Move (num_hdcp_streams > 0) condition to stream_encryption() code block, where it actually belongs. This fixes the static analysis error of uninitialized symbol 'ret'. v2: - return 0 as the return value is already checked. [Ankit] Cc: Ramalingam C <ramalingam.c@intel.com> Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210120103032.15198-1-anshuman.gupta@intel.com
2021-01-22drm/i915/hdcp: Fix WARN_ON(data->k > INTEL_NUM_PIPES)Anshuman Gupta1-0/+2
Initialize no. of streams transmitted on a port to zero such that intel_hdcp_required_content_stream() can prepared the content stream after subsequemt attmept to enable hdcp after a HDCP failure. v2: - Initialize k at top level instead of else branch. [Jani] Cc: Ramalingam C <ramalingam.c@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210119064655.1605-2-anshuman.gupta@intel.com
2021-01-22drm/i915/dp: Don't use DPCD backlights that need PWM enable/disableLyude Paul1-1/+6
We haven't yet implemented support for backlights that need to be enabled/disabled via PWM instead of AUX, which means we'll break things if we enable DPCD backlight control on these machines. Luckily though since most of these machines work fine just using the plain PWM backlight controls anyway, there shouldn't be any issue with just leaving DPCD backlight controls disabled in such situations. This should fix the issues with PWM being left on that were being observed on fi-bdw-samus. Signed-off-by: Lyude Paul <lyude@redhat.com> Reviewed-by: "Ville Syrjälä" <ville.syrjala@linux.intel.com> Fixes: 4a8d79901d5b ("drm/i915/dp: Enable Intel's HDR backlight interface (only SDR for now)") Testcase: igt/gem_exec_suspend/basic-s0 # fi-bdw-samus Cc: Lyude Paul <lyude@redhat.com> Cc: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210121183644.2627282-1-lyude@redhat.com
2021-01-21drm/i915: Unify the sanity checks for the buf trans tablesVille Syrjälä1-13/+10
Get rid of the "I like my random new style best" approach and unify the handling for the DDI buf trans table sanity checks once again. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201207203512.1718-2-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
generated by cgit v1.2.3 (git 2.39.0) at 2025-03-04 02:02:58 +0300