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2023-03-31drm/i915/psr: Implement Display WA #1136Jouni Högander2-5/+7
Implement Display WA #1136 for Pre-ICL. Bspec: 21664 v2: Handle disable psr in pre/post plane hooks Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230329150703.432072-7-jouni.hogander@intel.com
2023-03-31drm/i915/psr: Check that vblank is long enough for psr2Jouni Högander1-0/+9
Ensure vblank >= psr2 vblank where Psr2 vblank = PSR2_CTL Block Count Number maximum line count. Bspec: 71580, 49274 v2: Use calculated block count number maximum line count Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230329150703.432072-6-jouni.hogander@intel.com
2023-03-31drm/i915/psr: Add helpers for block count number handlingJouni Högander1-4/+14
Add helpers to make it more clear how PSR2_CTL[Block Count Number] is configured. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230329150703.432072-5-jouni.hogander@intel.com
2023-03-31drm/i915/psr: Implement Wa_14015648006Jouni Högander3-3/+21
PSR WM optimization should be disabled based on any wm level being disabled. Also same WA should be applied for ICL as well. Bspec: 71580 v5: - Set in pre plane hook and clear in post plane hook v4: - Handle mode change in psr enable/disable - Handle wm_level_disable changes separately in pre plane hook v3: - Split patch v2: - set/clear chicken bit in post_plane_update - apply for ICL as well Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230329150703.432072-4-jouni.hogander@intel.com
2023-03-31drm/i915/psr: Modify/Fix Wa_16013835468 and prepare for Wa_14015648006Jouni Högander1-11/+24
Wa_16013835468 is a separate from Wa_14015648006 and needs to be applied for display version 12. Fix this by removing all the references to Wa_14015648006 and apply Wa_16013835468 according to Bspec. Also move workaround into separate function as a preparation for Wa_14015648006 implementation. Bspec: 55378 v3: - apply for display version 12 only v2: - keep applying the wa in intel_psr_enable_source Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230329150703.432072-3-jouni.hogander@intel.com
2023-03-31drm/i915/psr: Unify pre/post hooksJouni Högander1-6/+5
pre/post hooks are doing things differently. Unify them. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230329150703.432072-2-jouni.hogander@intel.com
2023-03-31drm/i915/mtl: Fix MTL stolen memory GGTT mappingDaniele Ceraolo Spurio1-8/+7
The PTEs expect the offset from the base of the fake LMEM region (i.e. the base of stolen) and not from the base of the DSM. Quoting the specs: "Driver will set the Device Memory bit = 1 in the PTE when pointing to a page in DSM and program the PTE with offset from LMEM_BAR. Device Memory Offset from LMEM_BAR is same as offset from BGSM." DSM starts 8MBs from BGSM, so we set dsm_base = 8MB. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Nirmoy Das <nirmoy.das@intel.com> Cc: Fei Yang <fei.yang@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230328012430.2524330-1-daniele.ceraolospurio@intel.com
2023-03-30drm/i915/mtl: Add Wa_22015279794Radhakrishna Sripada2-0/+11
Wa_22015279794 applies to MTL P from stepping A0 to B0 (exclusive). Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230329212336.106161-3-gustavo.sousa@intel.com
2023-03-30drm/i915/mtl: Add workarounds Wa_14017066071 and Wa_14017654203Radhakrishna Sripada2-0/+10
Both workarounds require the same implementation and apply to MTL P and M from stepping A0 to B0 (exclusive). v2: - Remove unrelated brace removal. (Matt) Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230329212336.106161-2-gustavo.sousa@intel.com
2023-03-30drm: Use of_property_read_bool() for boolean propertiesRob Herring2-7/+3
It is preferred to use typed property access functions (i.e. of_property_read_<type> functions) rather than low-level of_get_property/of_find_property functions for reading properties. Convert reading boolean properties to of_property_read_bool(). Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20230310144706.1542295-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
2023-03-30drm/msm/a5xx: add devcoredump support to the fault handlerDmitry Baryshkov1-5/+8
Use adreno_fault_handler() to implement a5xx_fault_handler(). This enables devcoredump support on a5xx platforms, allowing one to capture the crashed GPU state at the time of context fault. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/522724/ Link: https://lore.kernel.org/r/20230214123504.3729522-4-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
2023-03-30drm/i915/dsb: split out DSB regs to a separate fileJani Nikula3-56/+68
Clean up i915_reg.h by splitting out DSB regs to display/intel_dsb_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/d74b3c564b2d080bf689b3360f1a5e62e47f2e7c.1678973283.git.jani.nikula@intel.com
2023-03-30drm/i915/fdi: split out FDI regs to a separate fileJani Nikula8-141/+157
Clean up i915_reg.h by splitting out FDI regs to display/intel_fdi_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/bba37e46d767e2193d49d1d2e289040c6bf8229b.1678973282.git.jani.nikula@intel.com
2023-03-30drm/i915/aux: split out DP AUX regs to a separate fileJani Nikula7-73/+89
Clean up i915_reg.h by splitting out DP AUX regs to display/intel_dp_aux_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/aa93b34e786c5566acf8f053ffed96c160a23898.1678973282.git.jani.nikula@intel.com
2023-03-30drm/i915/tv: split out TV regs to a separate fileJani Nikula3-480/+492
Clean up i915_reg.h by splitting out TV regs to display/intel_tv_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/be4a946a7772f5b4483ad9e078cb62158849683e.1678973282.git.jani.nikula@intel.com
2023-03-30drm/i915/pps: split out PPS regs to a separate fileJani Nikula7-67/+83
Clean up i915_reg.h by splitting out PPS regs to display/intel_pps_regs.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/80d66ee6d7e56153a0ab25640ac2dad239b1ef6e.1678973282.git.jani.nikula@intel.com
2023-03-30drm/i915: Make utility pin asserts more accurateVille Syrjälä2-4/+8
Only the PWM output mode of the utility pin is incompatible with DC6/LCPLL disable. Check for that specifically. References: https://gitlab.freedesktop.org/drm/intel/-/issues/6609 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230328164938.8193-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2023-03-30dt-bindings: display: seiko,43wvf1g: Change the maintainer's contactFabio Estevam1-1/+1
Marco's NXP email is no longer valid. Marco told me offline that he has no interest to be listed as the maintainer contact for this binding, so add my contact. Signed-off-by: Fabio Estevam <festevam@denx.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20230329201150.741106-1-festevam@gmail.com
2023-03-30Merge remote-tracking branch 'drm/drm-next' into drm-misc-nextMaarten Lankhorst1622-76635/+48000
Backmerge to get rc4. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
2023-03-29dt-bindings: display: boe,tv101wum-nl6: document rotationKrzysztof Kozlowski1-0/+1
Allow 'rotation' property (coming from panel-common.yaml) already used in DTS: sc7180-trogdor-quackingstick-r0.dtb: panel@0: 'rotation' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230326155425.91181-6-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring <robh@kernel.org>
2023-03-29dt-bindings: display: visionox,rm69299: document regKrzysztof Kozlowski1-8/+17
Panels are supposed to have one reg. This fixes dtbs_check warnings like: sc7180-idp.dtb: panel@0: 'reg' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230326155425.91181-5-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring <robh@kernel.org>
2023-03-29dt-bindings: display: panel-simple-dsi: document portKrzysztof Kozlowski1-0/+8
Panels are supposed to have one port (coming from panel-common.yaml binding): msm8916-samsung-a3u-eur.dtb: panel@0: 'port' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230326155425.91181-4-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring <robh@kernel.org>
2023-03-29dt-bindings: display: panel-simple-dsi: allow vddio variantKrzysztof Kozlowski1-4/+20
Few panels like Samsung s6e3fc2x01 and sofef00 use vddio-supply instead of power-supply (in DTS and Linux driver), so allow it to fix: sdm845-oneplus-enchilada.dtb: panel@0: 'power-supply' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230326155425.91181-3-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring <robh@kernel.org>
2023-03-29dt-bindings: display: novatek,nt36672a: correct VDDIO supplyKrzysztof Kozlowski1-3/+3
The nt36672a bindings were added with a mistake on VDDIO supply calling it in one place vddio and in other vddi0. Typical name is rather vddio which is also now used by DTS (sdm845-xiaomi-beryllium-common.dtsi) and Linux driver. Fixes: c2abcf30efb8 ("dt-bindings: display: novatek,nt36672a: Fix unevaluated properties warning") Fixes: 9528a02430df ("dt-bindings: display: panel: Add bindings for Novatek nt36672a") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230326155425.91181-2-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring <robh@kernel.org>
2023-03-29dt-bindings: display: panel-simple: merge Innolux p120zdg-bf1Krzysztof Kozlowski2-43/+2
There is nothing special in Innolux p120zdg-bf1 panel, so just like other Innolux panels it can be made part of panel-simple. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230326155425.91181-1-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring <robh@kernel.org>
2023-03-29Merge v6.3-rc4 into drm-nextDaniel Vetter774-5614/+8147
I just landed the fence deadline PR from Rob that a bunch of drivers want/need to apply driver-specific patches. Backmerge -rc4 so that they don't have to be stuck on -rc2 for no reason at all. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2023-03-29Merge tag 'dma-fence-deadline' of https://gitlab.freedesktop.org/drm/msm ↵Daniel Vetter14-34/+303
into drm-next This series adds a deadline hint to fences, so realtime deadlines such as vblank can be communicated to the fence signaller for power/ frequency management decisions. This is partially inspired by a trick i915 does, but implemented via dma-fence for a couple of reasons: 1) To continue to be able to use the atomic helpers 2) To support cases where display and gpu are different drivers See https://patchwork.freedesktop.org/series/93035/ This does not yet add any UAPI, although this will be needed in a number of cases: 1) Workloads "ping-ponging" between CPU and GPU, where we don't want the GPU freq governor to interpret time stalled waiting for GPU as "idle" time 2) Cases where the compositor is waiting for fences to be signaled before issuing the atomic ioctl, for example to maintain 60fps cursor updates even when the GPU is not able to maintain that framerate. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> From: Rob Clark <robdclark@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGt5nDQpa6J86V1oFKPA30YcJzPhAVpmF7N1K1g2N3c=Zg@mail.gmail.com
2023-03-29drm/i915: fix race condition UAF in i915_perf_add_config_ioctlMin Li1-3/+3
Userspace can guess the id value and try to race oa_config object creation with config remove, resulting in a use-after-free if we dereference the object after unlocking the metrics_lock. For that reason, unlocking the metrics_lock must be done after we are done dereferencing the object. Signed-off-by: Min Li <lm0963hack@gmail.com> Fixes: f89823c21224 ("drm/i915/perf: Implement I915_PERF_ADD/REMOVE_CONFIG interface") Cc: <stable@vger.kernel.org> # v4.14+ Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230328093627.5067-1-lm0963hack@gmail.com [tursulin: Manually added stable tag.]
2023-03-29drm/i915: Use compressed bpp when calculating m/n value for DP MST DSCStanislav Lisovskiy1-1/+1
For obvious reasons, we use compressed bpp instead of pipe bpp for DSC DP SST case. Lets be consistent and use compressed bpp instead of pipe bpp, also in DP MST DSC case. Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Fixes: d51f25eb479a ("drm/i915: Add DSC support to MST path") Link: https://patchwork.freedesktop.org/patch/msgid/20230327064217.24033-1-stanislav.lisovskiy@intel.com
2023-03-29drm/msm/adreno: split a6xx fault handler into generic and a6xx partsDmitry Baryshkov3-57/+71
Split the a6xx_fault_handler() into the generic adreno_fault_handler() and platform-specific parts. The adreno_fault_handler() can further be used by a5xx and hopefully by a4xx (at some point). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/522722/ Link: https://lore.kernel.org/r/20230214123504.3729522-3-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
2023-03-29drm/msm/adreno: stall translation on fault for all GPU familiesDmitry Baryshkov4-12/+31
The commit e25e92e08e32 ("drm/msm: devcoredump iommu fault support") enabled SMMU stalling to collect GPU state, but only for a6xx. It tied enabling the stall with tha per-instance pagetables creation. Since that commit SoCs with a5xx also gained support for adreno-smmu-priv. Move stalling into generic code and add corresponding resume_translation calls. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/522720/ Link: https://lore.kernel.org/r/20230214123504.3729522-2-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
2023-03-29drm/msm/atomic: Switch to vblank_start helperRob Clark3-26/+5
Drop our custom thing and switch to drm_crtc_next_vblank_start() for calculating the time of the start of the next vblank period. Signed-off-by: Rob Clark <robdclark@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/525819/ Link: https://lore.kernel.org/r/20230308155322.344664-15-robdclark@gmail.com
2023-03-29drm/msm: Add wait-boost supportRob Clark3-6/+25
Add a way for various userspace waits to signal urgency. Signed-off-by: Rob Clark <robdclark@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/525817/ Link: https://lore.kernel.org/r/20230308155322.344664-14-robdclark@gmail.com
2023-03-29drm/msm: Add deadline based boost supportRob Clark2-0/+94
Track the nearest deadline on a fence timeline and set a timer to expire shortly before to trigger boost if the fence has not yet been signaled. v2: rebase Signed-off-by: Rob Clark <robdclark@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/525816/ Link: https://lore.kernel.org/r/20230308155322.344664-13-robdclark@gmail.com
2023-03-29Merge tag 'dma-fence-deadline' into HEADRob Clark14-34/+303
This series adds a deadline hint to fences, so realtime deadlines such as vblank can be communicated to the fence signaller for power/ frequency management decisions. This is partially inspired by a trick i915 does, but implemented via dma-fence for a couple of reasons: 1) To continue to be able to use the atomic helpers 2) To support cases where display and gpu are different drivers See https://patchwork.freedesktop.org/series/93035/ This does not yet add any UAPI, although this will be needed in a number of cases: 1) Workloads "ping-ponging" between CPU and GPU, where we don't want the GPU freq governor to interpret time stalled waiting for GPU as "idle" time 2) Cases where the compositor is waiting for fences to be signaled before issuing the atomic ioctl, for example to maintain 60fps cursor updates even when the GPU is not able to maintain that framerate. Signed-off-by: Rob Clark <robdclark@chromium.org>
2023-03-29drm/atomic-helper: Set fence deadline for vblankRob Clark1-0/+37
For an atomic commit updating a single CRTC (ie. a pageflip) calculate the next vblank time, and inform the fence(s) of that deadline. v2: Comment typo fix (danvet) v3: If there are multiple CRTCs, consider the time of the soonest vblank Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2023-03-29drm/vblank: Add helper to get next vblank timeRob Clark2-9/+45
Will be used in the next commit to set a deadline on fences that an atomic update is waiting on. v2: Calculate time at *start* of vblank period, not end v3: Fix kbuild complaints Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Mario Kleiner <mario.kleiner.de@gmail.com>
2023-03-29drm/scheduler: Add fence deadline supportRob Clark3-1/+64
As the finished fence is the one that is exposed to userspace, and therefore the one that other operations, like atomic update, would block on, we need to propagate the deadline from from the finished fence to the actual hw fence. v2: Split into drm_sched_fence_set_parent() (ckoenig) v3: Ensure a thread calling drm_sched_fence_set_deadline_finished() sees fence->parent set before drm_sched_fence_set_parent() does this test_bit(DMA_FENCE_FLAG_HAS_DEADLINE_BIT). Signed-off-by: Rob Clark <robdclark@chromium.org> Acked-by: Luben Tuikov <luben.tuikov@amd.com>
2023-03-28dma-buf/sync_file: Surface sync-file uABIRob Clark2-24/+23
We had all of the internal driver APIs, but not the all important userspace uABI, in the dma-buf doc. Fix that. And re-arrange the comments slightly as otherwise the comments for the ioctl nr defines would not show up. v2: Fix docs build warning coming from newly including the uabi header in the docs build Signed-off-by: Rob Clark <robdclark@chromium.org> Acked-by: Pekka Paalanen <pekka.paalanen@collabora.com>
2023-03-28dma-buf/dma-resv: Add a way to set fence deadlineRob Clark2-0/+24
Add a way to set a deadline on remaining resv fences according to the requested usage. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Christian König <christian.koenig@amd.com>
2023-03-28dma-buf/fence-chain: Add fence deadline supportRob Clark1-0/+12
Propagate the deadline to all the fences in the chain. v2: Use dma_fence_chain_contained [Tvrtko] Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Christian König <christian.koenig@amd.com>
2023-03-28drm: Use of_property_present() for testing DT property presenceRob Herring7-7/+7
It is preferred to use typed property access functions (i.e. of_property_read_<type> functions) rather than low-level of_get_property/of_find_property functions for reading properties. As part of this, convert of_get_property/of_find_property calls to the recently added of_property_present() helper when we just want to test for presence of a property and nothing more. Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Liu Ying <victor.liu@nxp.com> # i.MX bridge Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20230310144705.1542207-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
2023-03-28drm/i915/gsc: implement wa 14015076503Daniele Ceraolo Spurio3-7/+93
The WA states that we need to alert the GSC FW before doing a GSC engine reset and then wait for 200ms. The GuC owns engine reset, so on the i915 side we only need to apply this for full GT reset. Given that we do full GT resets in the resume paths to cleanup the HW state and that a long wait in those scenarios would not be acceptable, a faster path has been introduced where, if the GSC is idle, we try first to individually reset the GuC and all engines except the GSC and only fall back to full reset if that fails. Note: according to the WA specs, if the GSC is idle it should be possible to only wait for the uC wakeup time (~15ms) instead of the whole 200ms. However, the GSC FW team have mentioned that the wakeup time can change based on other things going on in the HW and pcode, so a good security margin would be required. Given that when the GSC is idle we already skip the wait & reset entirely and that this reduced wait would still likely be too long to use in resume paths, it's not worth adding support for this reduced wait. v2: add comment to explain why it is safe to skip the GSC reset (John) Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: John Harrison <john.c.harrison@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: John Harrison <John.C.Harrison@Intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230323231857.2194435-2-daniele.ceraolospurio@intel.com
2023-03-28drm/i915: limit double GT reset to pre-MTLDaniele Ceraolo Spurio1-15/+20
Commit 3db9d590557d ("drm/i915/gt: Reset twice") modified the code to always hit the GDRST register twice when doing a reset, with the reported aim to fix invalid post-reset engine state on some platforms (Jasperlake being the only one actually mentioned). This is a problem on MTL, due to the fact that we have to apply a time consuming WA (coming in the next patch) every time we hit the GDRST register in a way that can include the GSC engine. Even post MTL, the expectation is that we'll have some work to do before and after hitting the GDRST if the GSC is involved. Since the issue requiring the double reset seems to be limited to older platforms, instead of trying to handle the double-reset on MTL and future platforms it is just easier to turn it off. The default on MTL is also for GuC to own engine reset, with i915 only covering full-GT reset. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Andi Shyti <andi.shyti@linux.intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Cc: John Harrison <John.C.Harrison@Intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230323231857.2194435-1-daniele.ceraolospurio@intel.com
2023-03-28drm/i915/huc: Cancel HuC delayed load timer on reset.Daniele Ceraolo Spurio2-6/+8
In the rare case where we do a full GT reset after starting the HuC load and before it completes (which basically boils down to i915 hanging during init), we need to cancel the delayed load fence, as it will be re-initialized in the post-reset recovery. Fixes: 27536e03271d ("drm/i915/huc: track delayed HuC load with a fence") Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230313205556.1174503-1-daniele.ceraolospurio@intel.com
2023-03-28Merge tag 'exynos-drm-next-for-v6.4' of ↵Daniel Vetter8-1729/+2191
git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next A patch series for moving MIPI-DSI driver for Exynos DRM to drm/bridge directory so that I.MX SoC family can also share the same device driver. Samsung MIPI DSIM device is a common IP that can be used by Exynos and I.MX8M Mini/Nano/Plus SoC. Regarding this, this patch series has added several things below to existing MIPI DSI driver, - Add exynos_dsi_type enum type to provide controller data from different platforms. - Add two pipeline detection ways support - existing Exynos DSI child node and I.MX family of-graph port or ports. - Consider component and bridged based DRM drivers. - Add device tree binding support of I.MX family. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> From: Inki Dae <inki.dae@samsung.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230328040524.49278-1-inki.dae@samsung.com
2023-03-28drm/i915: remove unused config DRM_I915_UNSTABLEJani Nikula2-27/+0
Essentially this is a revert of commit d9d54a530a70 ("drm/i915: Put future HW and their uAPIs under STAGING & BROKEN"). We currently have no users for this config option. The last one was removed in commit 8c26491f5853 ("drm/i915: Kill the fake lmem support"). Drop it altogether; it's easy enough to resurrect if need arises. Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230327105330.312131-2-jani.nikula@intel.com
2023-03-28Merge drm/drm-next into drm-intel-nextRodrigo Vivi13453-467759/+627584
Catch up with 6.3-rc cycle... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2023-03-28drm/i915: Check for unreliable MMIO during forcewakeMatt Roper1-3/+10
Although we now sanitycheck MMIO access during driver load to make sure the MMIO BAR isn't returning all 0xFFFFFFFF, there have been a few cases where (temporarily?) unreliable MMIO access has happened after GPU resets or power events. We'll often notice this on our next GT register access since forcewake handling will fail; let's change our handling slightly so that when this happens we print a more meaningful message clarifying that the problem is the MMIO access, not forcewake specifically. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230327195547.356584-3-andi.shyti@linux.intel.com
2023-03-28drm/i915: Sanitycheck MMIO access early in driver loadMatt Roper1-0/+34
We occasionally see the PCI device in a non-accessible state at the point the driver is loaded. When this happens, all BAR accesses will read back as 0xFFFFFFFF. Rather than reading registers and misinterpreting their (invalid) values, let's specifically check for 0xFFFFFFFF in a register that cannot have that value to see if the device is accessible. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230327195547.356584-2-andi.shyti@linux.intel.com
generated by cgit v1.2.3 (git 2.39.0) at 2025-10-02 20:49:27 +0300