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2024-10-17phy: airoha: Fix REG_CSR_2L_JCPLL_SDM_HREN config in ↵Lorenzo Bianconi1-1/+1
airoha_pcie_phy_init_ssc_jcpll() Fix typo configuring REG_CSR_2L_JCPLL_SDM_HREN register in airoha_pcie_phy_init_ssc_jcpll routine. Fixes: d7d2818b9383 ("phy: airoha: Add PCIe PHY driver for EN7581 SoC.") Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/20240918-airoha-en7581-phy-fixes-v1-3-8291729a87f8@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: airoha: Fix REG_PCIE_PMA_TX_RESET config in airoha_pcie_phy_init_csr_2l()Lorenzo Bianconi1-2/+2
Fix typos configuring REG_PCIE_PMA_TX_RESET register in airoha_pcie_phy_init_csr_2l routine for lane0 and lane1 Fixes: d7d2818b9383 ("phy: airoha: Add PCIe PHY driver for EN7581 SoC.") Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/20240918-airoha-en7581-phy-fixes-v1-2-8291729a87f8@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: airoha: Fix REG_CSR_2L_PLL_CMN_RESERVE0 config in ↵Lorenzo Bianconi1-1/+1
airoha_pcie_phy_init_clk_out() Fix typo configuring REG_CSR_2L_PLL_CMN_RESERVE0 register in airoha_pcie_phy_init_clk_out routine. Fixes: d7d2818b9383 ("phy: airoha: Add PCIe PHY driver for EN7581 SoC.") Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/20240918-airoha-en7581-phy-fixes-v1-1-8291729a87f8@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: phy-rockchip-samsung-hdptx: Don't request RST_PHY/RST_ROPLL/RST_LCPLLAndy Yan1-16/+1
RST_PHY/RST_ROPLL/RST_LCPLL are used for debug only on rk3588, and they are not exported on rk3576, no need to request it in driver. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Link: https://lore.kernel.org/r/20240920093629.7410-1-andyshrk@163.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: add NXP PTN3222 eUSB2 to USB2 redriverDmitry Baryshkov3-0/+135
The NXP PTN3222 is the single-port eUSB2 to USB2 redriver that performs translation between eUSB2 and USB2 signalling schemes. It supports all three data rates: Low Speed, Full Speed and High Speed. The reset state enables autonegotiation of the PHY role and of the data rate, so no additional programming is required. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Konrad Dybcio <konradybcio@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Stephan Gerhold <stephan.gerhold@linaro.org> Tested-by: Stephan Gerhold <stephan.gerhold@linaro.org> Link: https://lore.kernel.org/r/20240830-nxp-ptn3222-v2-2-4c6d8535cf6c@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17dt-bindings: phy: add NXP PTN3222 eUSB2 to USB2 redriverDmitry Baryshkov1-0/+55
The NXP PTN3222 is the single-port eUSB2 to USB2 redriver that performs translation between eUSB2 and USB2 signalling schemes. It supports all three data rates: Low Speed, Full Speed and High Speed. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Stephan Gerhold <stephan.gerhold@linaro.org> Link: https://lore.kernel.org/r/20240830-nxp-ptn3222-v2-1-4c6d8535cf6c@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17dt-bindings: phy: mxs-usb-phy: add imx8qxp compatibleXu Yang1-0/+1
Add "fsl,imx8qxp-usbphy" compatible. Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240926073951.783869-2-xu.yang_2@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17dt-bindings: phy: rk3228-hdmi-phy: convert to yamlHeiko Stuebner2-43/+97
Convert the binding to yaml and rename it according to its first compatible instead of the unspecific rockchip-inno-hdmi naming. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20241007162732.2450168-1-heiko@sntech.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: Switch back to struct platform_driver::remove()Uwe Kleine-König35-59/+59
After commit 0edb555a65d1 ("platform: Make platform_driver::remove() return void") .remove() is (again) the right callback to implement for platform drivers. Convert all platform drivers below drivers/phy/ to use .remove(), with the eventual goal to drop struct platform_driver::remove_new(). As .remove() and .remove_new() have the same prototypes, conversion is done by just changing the structure member name in the driver initializer. While touching these files, make indention of the struct initializer consistent in several files. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Link: https://lore.kernel.org/r/20241009065307.504930-2-u.kleine-koenig@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17dt-bindings: phy: mediatek: tphy: add a property for power-domainsMacpaul Lin1-0/+10
Include the MediaTek TPHY in a power domain. Add the 'power-domains' property in the Device Tree (DT) Schema and set 'maxItems: 1'. Also, include a reminder in the description of the 'power-domains' property. Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241012035016.17667-1-macpaul.lin@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: qcom: edp: Add support for eDP PHY on SA8775PSoutrik Mukhopadhyay1-0/+33
Add support for eDP PHY v5 found on the Qualcomm SA8775P platform. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com> Link: https://lore.kernel.org/r/20241004103046.22209-4-quic_mukhopad@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: qcom: edp: Introduce aux_cfg array for version specific aux settingsSoutrik Mukhopadhyay1-24/+17
In order to support different HW versions, introduce aux_cfg array to move v4 specific aux configuration settings. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com> Link: https://lore.kernel.org/r/20241004103046.22209-3-quic_mukhopad@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17dt-bindings: phy: Add eDP PHY compatible for sa8775pSoutrik Mukhopadhyay1-0/+1
Add compatible string for the supported eDP PHY on sa8775p platform. Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241004103046.22209-2-quic_mukhopad@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: rockchip: usbdp: add rk3576 device match dataFrank Wang1-0/+41
This adds RK3576 device match data support. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Acked-by: Dragan Simic <dsimic@manjaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20241014020342.15974-2-frawang.cn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17dt-bindings: phy: rockchip-usbdp: add rk3576Frank Wang1-0/+1
Add compatible for the USBDP phy in the Rockchip RK3576 SoC. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/20241014020342.15974-1-frawang.cn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: freescale: fsl-samsung-hdmi: Remove unnecessary LUT entriesAdam Ford1-70/+13
The lookup table contains entries which use the integer divider instead of just the fractional divider. Since the set and round functions check both the integer divider values and the LUT values, it's no longer necessary to keep the integer divider values in the lookup table, as can be dynamically calcuated. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Tested-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Link: https://lore.kernel.org/r/20240914112816.520224-6-aford173@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: freescale: fsl-samsung-hdmi: Use closest dividerAdam Ford1-11/+29
Currently, if the clock values cannot be set to the exact rate, the round_rate and set_rate functions use the closest value found in the look-up-table. In preparation of removing values from the LUT that can be calculated evenly with the integer calculator, it's necessary to ensure to check both the look-up-table and the integer divider clock values to get the closest values to the requested value. It does this by measuring the difference between the requested clock value and the closest value in both integer divider calucator and the fractional clock look-up-table. Which ever has the smallest difference between them is returned as the closest rate. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Tested-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Link: https://lore.kernel.org/r/20240914112816.520224-5-aford173@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: freescale: fsl-samsung-hdmi: Support dynamic integerAdam Ford1-107/+270
There is currently a look-up table for a variety of resolutions. Since the phy has the ability to dynamically calculate the values necessary to use the intger divider which should allow more resolutions without having to update the look-up-table. If the lookup table cannot find an exact match, fall back to the dynamic calculator of the integer divider. Previously, the value of P was hard-coded to 1, this required an update to the phy_pll_cfg table to add in the extra value into the table, so if the value of P is calculated to be something else by the PMS calculator, the calculated_phy_pll_cfg structure can be used instead without having to keep track of which method was used. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Tested-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Link: https://lore.kernel.org/r/20240914112816.520224-4-aford173@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: freescale: fsl-samsung-hdmi: Simplify REG21_PMS_S_MASK lookupAdam Ford1-35/+4
The value of 'S' is writen to two places, PHY_REG3[7:4] and PHY_REG21[3:0]. There is a lookup table which contains the value of PHY_REG3. Rather than using a switch statement based on the pixel clock to search for the value of 'S' again, just shift the contents of PHY_REG3[7:4] >> 4 and place the value in PHY_REG21[3:0]. Doing this can eliminate an entire function. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Tested-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Link: https://lore.kernel.org/r/20240914112816.520224-3-aford173@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: freescale: fsl-samsung-hdmi: Replace register defines with macroAdam Ford1-90/+43
There are 47 registers defined as PHY_REG_xx were xx goes from 00 to 47. Simplify this by replacing them all with a macro which is passed the register number to return the proper register offset. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Tested-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Link: https://lore.kernel.org/r/20240914112816.520224-2-aford173@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: rockchip: inno-usb2: Add usb2 phys support for rk3576William Wu1-0/+103
The RK3576 SoC has two independent USB2.0 PHYs, and each PHY has one port. This adds device specific data for it. Signed-off-by: William Wu <william.wu@rock-chips.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20241016073713.14133-4-frawang.cn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17dt-bindings: phy: rockchip,inno-usb2phy: add rk3576Frank Wang1-2/+43
Add compatible for the USB2 phy in the Rockchip RK3576 SoC. This change also refactor the clocks list as there are new clocks adding used for the USB MMU in RK3576 SoC. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20241016073713.14133-3-frawang.cn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: rockchip: inno-usb2: convert clock management to bulkFrank Wang1-8/+37
Since some Rockchip SoCs (e.g RK3576) have more than one clock, this converts the clock management from single to bulk method to make the driver more flexible. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20241016073713.14133-1-frawang.cn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: stm32: Remove unneeded semicolonYang Li1-1/+1
This patch removes an unneeded semicolon after a switch statement. ./drivers/phy/st/phy-stm32-combophy.c:226:2-3: Unneeded semicolon Reported-by: Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=11403 Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/20241017040657.33992-1-yang.lee@linux.alibaba.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3Qiang Yu3-0/+258
Currently driver supports only x4 lane based functionality using tx/rx and tx2/rx2 pair of register sets. To support 8 lane functionality with PCIe3, PCIe3 related QMP PHY provides additional programming which are available as txz and rxz based register set. Hence add txz and rxz based registers usage and programming sequences. As soon as software programs the txz and rxz based register set, hardware shall "broadcast" the same settings to the tx/rx pair of registers for all the 8 lanes, which saves the effort of software programming them one by one. There might be some tx and/or rx registers on some lanes need minor tweaks, program them after programming the txz and rxz reigster set. In addition, x1e80100 uses QMP PHY ver 6.30 for PCIe Gen4 x8, hence add two new header files to reflect the new register offsets. Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20241017030412.265000-5-quic_qianyu@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe ↵Qiang Yu1-0/+3
PHY Gen4 x8 PCIe 3rd instance of X1E80100 supports Gen 4 x8 which needs different 8 lane capable QMP PCIe PHY with hardware revision v6.30. Document Gen 4 x8 PHY as separate module. Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20241017030412.265000-2-quic_qianyu@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17dt-bindings: phy: Add QMP UFS PHY comptible for QCS615Sayali Lokhande1-20/+25
Document the QMP UFS PHY compatible for Qualcomm QCS615 to support physical layer functionality for UFS found on the SoC. Use fallback to indicate the compatibility of the QMP UFS PHY on the QCS615 with that on the SM6115. Signed-off-by: Sayali Lokhande <quic_sayalil@quicinc.com> Co-developed-by: Xin Liu <quic_liuxin@quicinc.com> Signed-off-by: Xin Liu <quic_liuxin@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241017042300.872963-2-quic_liuxin@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-17dt-bindings: phy: describe the Qualcomm SGMII PHYYijie Yang1-1/+6
Describe the SGMII/SerDes PHY present on the qcs8300 platforms. Since qcs8300 shares the same SerDes as sa8775p, so it fallback to the compatible. Signed-off-by: Yijie Yang <quic_yijiyang@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241017-schema-v2-2-2320f68dc126@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-11phy: sun4i-usb: Fix a typoAndrew Kreimer1-1/+1
Fix a typo in comments: wether -> whether. Signed-off-by: Andrew Kreimer <algonell@gmail.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Link: https://lore.kernel.org/r/20241010091355.8271-1-algonell@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-11phy: qcom: qmp: Add qmp configuration for QCS8300Krishna Kurapati1-0/+65
Add qmp configuration for QCS8300. It is similar to SA8775P and SC8280XP except for some Lane configuration settings specific to QCS8300. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241009195348.2649368-5-quic_kriskura@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-11dt-bindings: phy: qcom,sc8280xp-qmp-usb3-uni: Add QCS8300 compatibleKrishna Kurapati1-0/+2
Update dt-bindings to add QCS8300 to QMP Uni Phy list. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20241009195348.2649368-4-quic_kriskura@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-11dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for QCS8300Krishna Kurapati1-0/+1
Update dt-bindings to add QCS8300 to USB2 SNPS Femto Phy list. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20241009195348.2649368-3-quic_kriskura@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-11dt-bindings: usb: qcom,dwc3: Add QCS8300 to USB DWC3 bindingsKrishna Kurapati1-0/+4
Update dt-bindings to add QCS8300 to USB DWC3 controller list. The second controller of QCS8300 is High speed only capable and doesn't have ss_phy_irq. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20241009195348.2649368-2-quic_kriskura@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-11phy: ti: gmii-sel: Enable USXGMII mode for J7200Siddharth Vadapalli1-1/+2
TI's J7200 SoC supports USXGMII mode with the CPSW5G instance's MAC Port1. Add USXGMII mode to the extra_modes member of J7200's SoC data. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20241010144845.2555983-1-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-07dt-bindings: phy: cadence-sierra: Allow PHY types QSGMII and SGMIISiddharth Vadapalli1-1/+1
The Sierra SERDES can be configured for QSGMII and SGMII protocols. Hence, update the bindings to treat "PHY_TYPE_QSGMII" and "PHY_TYPE_SGMII" as valid values for the "cdns,phy-type" property. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240930095145.3004053-1-s-vadapalli@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-07MAINTAINERS: add entry for ST STM32MP25 COMBOPHY driverChristian Bruel1-0/+6
Add myself as STM32MP25 COMBOPHY maintainer Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Link: https://lore.kernel.org/r/20240930170847.948779-4-christian.bruel@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-07phy: stm32: Add support for STM32MP25 COMBOPHY.Christian Bruel3-0/+610
Addition of the COMBOPHY driver found on STM32MP25 platforms This single lane PHY is shared (exclusive) between the USB3 and PCIE controllers. Supports 5Gbit/s for PCIE gen2 or 2.5Gbit/s for PCIE gen1. Supports wakeup-source capability to wakeup system using remote-wakeup capable USB device Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Link: https://lore.kernel.org/r/20240930170847.948779-3-christian.bruel@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-07dt-bindings: phy: Add STM32MP25 COMBOPHY bindingsChristian Bruel1-0/+119
Document the bindings for STM32 COMBOPHY interface, used to support the PCIe and USB3 stm32mp25 drivers. Following entries can be used to tune caracterisation parameters - st,output-micro-ohms and st,output-vswing-microvolt bindings entries to tune the impedance and voltage swing using discrete simulation results - st,rx-equalizer register to set the internal rx equalizer filter value. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Link: https://lore.kernel.org/r/20240930170847.948779-2-christian.bruel@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-07phy: mvebu-cp110-utmi: support swapping d+/d- lanes by dts propertyJosua Mayer1-0/+16
CP11x UTMI PHY supports swapping D+/D- signals via digital control register 1. Add support for the "swap-dx-lanes" device-tree property, which lists the port-ids that should swap D+ and D-. The property is evaluated in probe and applied before power-on during mvebu_cp110_utmi_port_setup. Signed-off-by: Josua Mayer <josua@solid-run.com> Link: https://lore.kernel.org/r/20241002-mvebu-utmi-phy-v4-1-83783dc89b9d@solid-run.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-07phy: phy-rockchip-inno-usb2: Use dev_err_probe() in the probe pathDragan Simic1-17/+10
Improve error handling in the probe path by using function dev_err_probe() instead of function dev_err(), where appropriate. Signed-off-by: Dragan Simic <dsimic@manjaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/d4ccd9fc278fb46ea868406bf77811ee507f0e4e.1725524803.git.dsimic@manjaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-07phy: phy-rockchip-inno-usb2: Handle failed extcon allocation betterDragan Simic1-1/+2
Return the actual error code upon failure to allocate extcon device, instead of hardcoding -ENOMEM. Use dev_err_probe() to also log appropriate messages, which is fine because the containing function is used in the probe path. Helped-by: Heiko Stubner <heiko@sntech.de> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/cc4995aa3e569be6bc23ca126b41fba82d50eeee.1725524802.git.dsimic@manjaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-07phy: phy-rockchip-inno-usb2: Perform trivial code cleanupsDragan Simic1-17/+9
Perform a few trivial code cleanups, e.g. to obey the reverse Christmas tree rule, to avoid use of "{ ... }" code blocks where they aren't really needed, or to avoid line wrapping by using the 100-column width better. No intended functional changes are introduced by these code cleanups. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/adce7309f6fd9e1191c53bab552a8531d1a71216.1725524802.git.dsimic@manjaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-07phy: usb: update Broadcom driver table to use designated initializersSam Edwards1-220/+215
The Broadcom USB PHY driver contains a lookup table (`reg_bits_map_tables`) to resolve register bitmaps unique to certain versions of the USB PHY as found in various Broadcom chip families. Historically, this table was just kept carefully in sync with the "selector" enum every time the latter changed to ensure consistency. However, a recent commit [1] introduced two new enumerators but did not adjust the array for BCM4908, thus breaking the xHCI controller (and boot process) on this platform and revealing the fragility of this approach. Since these arrays are a little sparse (many elements are zero) and the position of the array elements is significant only insofar as they agree with the enumerators, designated initializers are a better fit than positional initializers here. Convert this table accordingly. [1] 4536fe9640b6 ("phy: usb: suppress OC condition for 7439b2") Signed-off-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Reviewed-by: Justin Chen <justin.chen@broadcom.com> Link: https://lore.kernel.org/r/20241004034131.1363813-3-CFSworks@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-07phy: usb: Fix missing elements in BCM4908 USB init arraySam Edwards1-0/+2
The Broadcom USB PHY driver contains a lookup table (`reg_bits_map_tables`) to resolve register bitmaps unique to certain versions of the USB PHY as found in various Broadcom chip families. A recent commit (see 'fixes' tag) introduced two new elements to each chip family in this table -- except for one: BCM4908. This resulted in the xHCI controller not being initialized correctly, causing a panic on boot. The next patch will update this table to use designated initializers in order to prevent this from happening again. For now, just add back the missing array elements to resolve the regression. Fixes: 4536fe9640b6 ("phy: usb: suppress OC condition for 7439b2") Signed-off-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Justin Chen <justin.chen@broadcom.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/r/20241004034131.1363813-2-CFSworks@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-09-30Linux 6.12-rc1Linus Torvalds1-2/+2
2024-09-30x86: kvm: fix build errorLinus Torvalds1-0/+2
The cpu_emergency_register_virt_callback() function is used unconditionally by the x86 kvm code, but it is declared (and defined) conditionally: #if IS_ENABLED(CONFIG_KVM_INTEL) || IS_ENABLED(CONFIG_KVM_AMD) void cpu_emergency_register_virt_callback(cpu_emergency_virt_cb *callback); ... leading to a build error when neither KVM_INTEL nor KVM_AMD support is enabled: arch/x86/kvm/x86.c: In function ‘kvm_arch_enable_virtualization’: arch/x86/kvm/x86.c:12517:9: error: implicit declaration of function ‘cpu_emergency_register_virt_callback’ [-Wimplicit-function-declaration] 12517 | cpu_emergency_register_virt_callback(kvm_x86_ops.emergency_disable_virtualization_cpu); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/x86/kvm/x86.c: In function ‘kvm_arch_disable_virtualization’: arch/x86/kvm/x86.c:12522:9: error: implicit declaration of function ‘cpu_emergency_unregister_virt_callback’ [-Wimplicit-function-declaration] 12522 | cpu_emergency_unregister_virt_callback(kvm_x86_ops.emergency_disable_virtualization_cpu); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Fix the build by defining empty helper functions the same way the old cpu_emergency_disable_virtualization() function was dealt with for the same situation. Maybe we could instead have made the call sites conditional, since the callers (kvm_arch_{en,dis}able_virtualization()) have an empty weak fallback. I'll leave that to the kvm people to argue about, this at least gets the build going for that particular config. Fixes: 590b09b1d88e ("KVM: x86: Register "emergency disable" callbacks when virt is enabled") Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Sean Christopherson <seanjc@google.com> Cc: Kai Huang <kai.huang@intel.com> Cc: Chao Gao <chao.gao@intel.com> Cc: Farrah Chen <farrah.chen@intel.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2024-09-29Merge tag 'mailbox-v6.12' of ↵Linus Torvalds10-51/+32
git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox Pull mailbox updates from Jassi Brar: - fix kconfig dependencies (mhu-v3, omap2+) - use devie name instead of genereic imx_mu_chan as interrupt name (imx) - enable sa8255p and qcs8300 ipc controllers (qcom) - Fix timeout during suspend mode (bcm2835) - convert to use use of_property_match_string (mailbox) - enable mt8188 (mediatek) - use devm_clk_get_enabled helpers (spreadtrum) - fix device-id typo (rockchip) * tag 'mailbox-v6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox: mailbox, remoteproc: omap2+: fix compile testing dt-bindings: mailbox: qcom-ipcc: Document QCS8300 IPCC dt-bindings: mailbox: qcom-ipcc: document the support for SA8255p dt-bindings: mailbox: mtk,adsp-mbox: Add compatible for MT8188 mailbox: Use of_property_match_string() instead of open-coding mailbox: bcm2835: Fix timeout during suspend mode mailbox: sprd: Use devm_clk_get_enabled() helpers mailbox: rockchip: fix a typo in module autoloading mailbox: imx: use device name in interrupt name mailbox: ARM_MHU_V3 should depend on ARM64
2024-09-29Merge tag 'i2c-for-6.12-rc1-additional_fixes' of ↵Linus Torvalds6-3/+58
git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux Pull i2c fixes from Wolfram Sang: - fix DesignWare driver ENABLE-ABORT sequence, ensuring ABORT can always be sent when needed - check for PCLK in the SynQuacer controller as an optional clock, allowing ACPI to directly provide the clock rate - KEBA driver Kconfig dependency fix - fix XIIC driver power suspend sequence * tag 'i2c-for-6.12-rc1-additional_fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: i2c: xiic: Fix pm_runtime_set_suspended() with runtime pm enabled i2c: keba: I2C_KEBA should depend on KEBA_CP500 i2c: synquacer: Deal with optional PCLK correctly i2c: designware: fix controller is holding SCL low while ENABLE bit is disabled
2024-09-29Merge tag 'dma-mapping-6.12-2024-09-29' of ↵Linus Torvalds1-18/+19
git://git.infradead.org/users/hch/dma-mapping Pull dma-mapping fix from Christoph Hellwig: - handle chained SGLs in the new tracing code (Christoph Hellwig) * tag 'dma-mapping-6.12-2024-09-29' of git://git.infradead.org/users/hch/dma-mapping: dma-mapping: fix DMA API tracing for chained scatterlists
2024-09-29Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsiLinus Torvalds34-154/+415
Pull more SCSI updates from James Bottomley: "These are mostly minor updates. There are two drivers (lpfc and mpi3mr) which missed the initial pull and a core change to retry a start/stop unit which affect suspend/resume" * tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi: (32 commits) scsi: lpfc: Update lpfc version to 14.4.0.5 scsi: lpfc: Support loopback tests with VMID enabled scsi: lpfc: Revise TRACE_EVENT log flag severities from KERN_ERR to KERN_WARNING scsi: lpfc: Ensure DA_ID handling completion before deleting an NPIV instance scsi: lpfc: Fix kref imbalance on fabric ndlps from dev_loss_tmo handler scsi: lpfc: Restrict support for 32 byte CDBs to specific HBAs scsi: lpfc: Update phba link state conditional before sending CMF_SYNC_WQE scsi: lpfc: Add ELS_RSP cmd to the list of WQEs to flush in lpfc_els_flush_cmd() scsi: mpi3mr: Update driver version to 8.12.0.0.50 scsi: mpi3mr: Improve wait logic while controller transitions to READY state scsi: mpi3mr: Update MPI Headers to revision 34 scsi: mpi3mr: Use firmware-provided timestamp update interval scsi: mpi3mr: Enhance the Enable Controller retry logic scsi: sd: Fix off-by-one error in sd_read_block_characteristics() scsi: pm8001: Do not overwrite PCI queue mapping scsi: scsi_debug: Remove a useless memset() scsi: pmcraid: Convert comma to semicolon scsi: sd: Retry START STOP UNIT commands scsi: mpi3mr: A performance fix scsi: ufs: qcom: Update MODE_MAX cfg_bw value ...
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