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2018-06-15drm/amdgpu: avoid sleep while executing atombios table (V2)Shirish S1-1/+1
This patch replaces kzalloc's flag from GFP_KERNEL to GFP_ATOMIC to avoid sleeping in atomic context. Below is the stack trace: BUG: sleeping function called from invalid context at mm/slab.h:*** in_atomic(): 1, irqs_disabled(): 0, pid: 1137, name: DrmThread CPU: 1 PID: 1137 Comm: DrmThread Tainted: G W 4.14.43 #10 Call Trace: dump_stack+0x4d/0x63 ___might_sleep+0x11f/0x12e __kmalloc+0x76/0x126 amdgpu_atom_execute_table_locked+0xfc/0x285 amdgpu_atom_execute_table+0x5d/0x72 transmitter_control_v1_5+0xef/0x11a hwss_edp_backlight_control+0x132/0x151 dce110_disable_stream+0x133/0x16e core_link_disable_stream+0x1c5/0x23b dce110_reset_hw_ctx_wrap+0xb4/0x1aa dce110_apply_ctx_to_hw+0x4e/0x6da ? generic_reg_get+0x1f/0x33 dc_commit_state+0x33f/0x3d2 amdgpu_dm_atomic_commit_tail+0x2cf/0x5d2 ? wait_for_common+0x5b/0x69 commit_tail+0x42/0x64 drm_atomic_helper_commit+0xdc/0xf9 drm_atomic_helper_set_config+0x5c/0x76 __drm_mode_set_config_internal+0x64/0x105 drm_mode_setcrtc+0x474/0x56f ? drm_mode_getcrtc+0x155/0x155 drm_ioctl_kernel+0x6c/0xa8 drm_ioctl+0x267/0x353 ? drm_mode_getcrtc+0x155/0x155 amdgpu_drm_ioctl+0x4f/0x7f vfs_ioctl+0x21/0x2f do_vfs_ioctl+0x4c4/0x4e7 ? security_file_ioctl+0x3b/0x4f SyS_ioctl+0x57/0x79 do_syscall_64+0x64/0x72 entry_SYSCALL_64_after_hwframe+0x3d/0xa2 V2: Added stack trace in commit message. Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amdgpu: Add documentation for PRIME related codeMichel Dänzer2-0/+133
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/doc: Add initial amdgpu driver documentationMichel Dänzer2-0/+7
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/doc: Add a label for the PRIME Buffer Sharing chapterMichel Dänzer1-0/+2
So that it can be referenced from e.g. DOC comments. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amdgpu/pp: switch the default dpm implementation for CIAlex Deucher1-4/+4
Switch hawaii and bonaire to use powerplay rather than the old dpm implementation. Powerplay supports more features and is better maintained. Ultimately, we can drop the older dpm implementation like we did for other older asics. Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Rex Zhu <rezhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amdgpu/display: enable CONFIG_DRM_AMD_DC_DCN1_0 by defaultAlex Deucher1-0/+1
It's required for displays on Raven. The DCN bandwidth calcs use floating point, but DCN is APU only and it already depends on X86. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amdgpu/display: drop DRM_AMD_DC_FBC kconfig optionAlex Deucher8-50/+5
Just enable it always. This was leftover from feature bring up. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amdgpu: add kernel doc for memory domains.Samuel Li1-0/+23
Document the GEM domains exposed to userspace. Suggested-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Samuel Li <Samuel.Li@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amdgpu: add kernel doc for amdgpu_object.cSamuel Li1-0/+269
Document the amdgpu buffer object API. v2: Add a DOC section and some more clarification. v3: Add some clarification and fix a spelling. Suggested-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Samuel Li <Samuel.Li@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amd/display: dal 3.1.47Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amd/display: add dentist frequency to resource poolDmytro Laktyushkin1-0/+1
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amd/display: DP YCbCr 4:2:0 supportEric Bernstein1-2/+12
Update MSA MISC1 bit 6 programming to handle YCbCr 4:2:0 and BT2020 cases. Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amd/display: Prefix TIMING_STANDARD entries with DC_Reza Amini5-28/+35
Signed-off-by: Reza Amini <Reza.Amini@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amd/display: dal 3.1.46Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amd/display: Added documentation for some DC interface functionsYasir Al Shekerchi3-0/+43
Signed-off-by: Yasir Al Shekerchi <YasirAl.Shekerchi@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amd/display: HLG supportVitaly Prosyak2-0/+139
Low level calculation methods. Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amd/display: Refactor audio programmingAnthony Koo5-142/+163
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amd/display: Dynamic HDR metadata mem bufferKrunoslav Kovac2-0/+3
Basic framework: - caps for reporting dynamic HDR metadata support - allocation of frame buffer memory and storage Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amd/display: Optimize DP_SINK_STATUS_ESI range read on HPDNikola Cornij1-9/+13
DP_SINK_STATUS_ESI range data is not continual, but rather than getting it in two AUX reads, it's quicker to read more bytes in a AUX read and then memcpy the required fields (it's only 8 more bytes to read). Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amd/display: Default log masks should include all connectivity eventsAric Cyr3-41/+46
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amd/display: Fix indentation in dcn10 resource constructorHersen Wu1-1/+2
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amd/display: add DPCD read for Sink ieee OUIAnthony Koo1-0/+12
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amd/display: Add function to get optc active sizeEric Bernstein3-0/+39
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amd/display: AUX will exit when HPD LOW detectedHersen Wu5-8/+41
This change shorten wait time when HPD LOW. With HPD LOW, without this change, AUX routine delay is 450us. With this change, it is 42us. Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amd/display: Prefix event prints with ==Event==Anthony Koo1-1/+1
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amd/display: dal 3.1.45Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amd/display: upgrade scaler mathDmytro Laktyushkin1-130/+289
This change will allow the viewport overlap to apply to rotated/ mirrored surfaces. Viewport overlap results in extra pixels being added to viewport allowing the first few pixels to be scaled as if there is no cut-off(mpo or pipe split) and allows us to get matching crc's between scaled split and unsplit outputs of the same thing. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amd/display: Clean up submit_channel_requestCharlene Liu1-17/+17
Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Vitaly Prosyak <Vitaly.Prosyak@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amd/display: pass pipe_ctx straight to blank_pixel_dataEric Bernstein2-7/+6
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/doc: add a chapter for gpu schedulerNayan Deshmukh1-0/+18
Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/scheduler: add documentationNayan Deshmukh2-71/+296
convert existing raw comments into kernel-doc format as well as add new documentation v2: reword the overview Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Daniel Vetter <daniel@ffwll.ch>
2018-06-15drm/amd/display: fix type of variableGustavo A. R. Silva1-1/+1
Currently, the maximum value that *counter* can reach is 255, and code at line 150: while (counter < 1000) { implies a bigger value could be expected. Fix this by changing the type of variable *counter* from uint8_t to uint16_t. Addresses-Coverity-ID: 1470030 ("Operands don't affect result") Fixes: 2b6199a1d1b7 ("drm/amd/display: replace msleep with udelay in fbc path") Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amdgpu: Fix uvd firmware version information for vega20 (v2)Alex Deucher1-18/+24
The uvd version information was not set correctly for vega20. Rearrange the logic to set it correctly and fix the warnings as a result. v2: fix version formatting for userspace based on feedback from Leo Fixes: 96ca7f298f (drm/amdgpu/vg20:support new UVD FW version naming convention) Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amdgpu/vg20:support new UVD FW version naming conventionJames Zhu1-5/+16
Vega20 UVD Firmware has a new version naming convention: [31, 30] for encode interface major [29, 24] for encode interface minor [15, 8] for decode interface minor [7, 0] for hardware family id Signed-off-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amd/pp: Make sure clock_voltage_limit_table on dc is validRex Zhu1-0/+5
if vbios not set the max clock voltage limit table for DC mode, Set the table as sama as the table for AC mode. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amd/pp: Add S3 support for OD featureRex Zhu2-98/+107
make custom values survive when S3 sleep transitions. so not reset the od table if it is not null. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15drm/amdgpu: allocate shared fence slot in VA IOCTLChristian König1-1/+1
Per VM BOs share the reservation object with the PD and so need to reserve a shared fence slot for the update. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-15Merge branch 'drm-next-4.18' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie43-255/+372
into drm-next Fixes for 4.18. Highlights: - Fixes for gfxoff on Raven - Remove an ATPX quirk now that the root cause is fixed - Runtime PM fixes - Vega20 register header update - Wattman fixes - Misc bug fixes Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180614141428.2909-1-alexander.deucher@amd.com
2018-06-14drm/amd/powerplay: Set higher SCLK&MCLK frequency than dpm7 in OD (v2)Kenneth Feng1-2/+5
Fix the issue that SCLK&MCLK can't be set higher than dpm7 when OD is enabled in SMU7. v2: fix warning (Alex) Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Acked-by: Rex Zhu<rezhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-13drm/amd/powerplay: remove uncessary extra gfxoff control callEvan Quan1-9/+0
Gfxoff is already enabled in amdgpu_device_ip_set_powergating_state. So, no need to enable it again in pp_late_init. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-13drm/amdgpu: fix parsing indirect register list v2Evan Quan1-6/+9
WARN_ON possible buffer overflow and avoid unnecessary dereference. v2: change BUG_ON to WARN_ON Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-13drm/amd/include: Update df 3.6 mask and shift definitionShaoyun Liu1-4/+4
The register field hsas been changed in df 3.6, update to correct setting Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-13drm/amd/pp: Fix OD feature enable failed on Vega10 workstation cardsRex Zhu1-2/+7
As hw required, soc clock must large than mclk, So we set max soc clock to OD Max Memory clk. But on workstation, vbios do not support OD feature, the OD max memory clock is equal to 0. In this case, driver can support underclocking. and set od max memory clock to the value in highest memory dpm level. So the od max memory clock should be less than highest soc clock. and driver should not change the soc clock. caused by commit ca57b9b0a156 ("drm/amd/pp: Allow underclocking when od table is empty in vbios") Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-13drm/amd/display: Fix stale buffer object (bo) usePratik Vishwakarma1-11/+0
Fixes stale buffer object (bo) usage for cursor plane Cursor plane's bo operations are handled in DC code. Currently, atomic_commit() does not handle bo operations for cursor plane, as a result the bo assigned for cursor plane in dm_plane_helper_prepare_fb() is not coherent with the updates to the same made in dc code.This mismatch leads to "bo" corruption and hence crashes during S3 entry. This patch cleans up the code which was added as a hack for 4.9 version only. Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-13drm/amd/pp: initialize result to before or'ing in dataColin Ian King1-1/+1
The current use of result is or'ing in values and checking for a non-zero result, however, result is not initialized to zero so it potentially contains garbage to start with. Fix this by initializing it to the first return from the call to vega10_program_didt_config_registers. Detected by cppcheck: "(error) Uninitialized variable: result" Fixes: 9b7b8154cdb8 ("drm/amd/powerplay: added didt support for vega10") Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Huang Rui <ray.huang@amd.com> [Fix the subject as Colin's comment] Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2018-06-13drm/amd/powerplay: fix wrong clock adjust sequenceEvan Quan1-7/+6
The clocks should be adjusted after display configuration changed. Otherwise, the socclk and memclk may be forced on an unnecessary higher level. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-13drm/amdgpu: Grab/put runtime PM references in atomic_commit_tail()Lyude Paul1-0/+13
So, unfortunately I recently made the discovery that in the upstream kernel, the only reason that amdgpu is not currently suffering from issues with runtime PM putting the GPU into suspend while it's driving displays is due to the fact that on most prime systems, we have sound devices associated with the GPU that hold their own runtime PM ref for the GPU. What this means however, is that in the event that there isn't any kind of sound device active (which can easily be reproduced by building a kernel with sound drivers disabled), the GPU will fall asleep even when there's displays active. This appears to be in part due to the fact that amdgpu has not actually ever relied on it's rpm_idle() function to be the only thing keeping it running, and normally grabs it's own power references whenever there are displays active (as can be seen with the original pre-DC codepath in amdgpu_display_crtc_set_config() in amdgpu_display.c). This means it's very likely that this bug was introduced during the switch over the DC. So to fix this, we start grabbing runtime PM references every time we enable a previously disabled CRTC in atomic_commit_tail(). This appears to be the correct solution, as it matches up with what i915 does in i915/intel_runtime_pm.c. The one sideaffect of this is that we ignore the variable that the pre-DC code used to use for tracking when it needed runtime PM refs, adev->have_disp_power_ref. This is mainly because there's no way for a driver to tell whether or not all of it's CRTCs are enabled or disabled when we've begun committing an atomic state, as there may be CRTC commits happening in parallel that aren't contained within the atomic state being committed. So, it's safer to just get/put a reference for each CRTC being enabled or disabled in the new atomic state. Signed-off-by: Lyude Paul <lyude@redhat.com> Acked-by: Christian König <christian.koenig@amd.com>. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2018-06-13drm/amd/powerplay: fix missed hwmgr check warning before call ↵Huang Rui1-1/+2
gfx_off_control handler Patch 9667849bbb8d: "drm/amd/powerplay: add control gfxoff enabling in late init" from Mar 13, 2018, leads to the following static checker warning: drivers/gpu/drm/amd/amdgpu/../powerplay/amd_powerplay.c:194 pp_late_init() error: we previously assumed 'hwmgr' could be null (see line 185) drivers/gpu/drm/amd/amdgpu/../powerplay/amd_powerplay.c This patch fixes the warning to add hwmgr checking. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-13drm/amdgpu: fix CG enabling hang with gfxoff enabledHuang Rui4-8/+15
After defer the execution of clockgating enabling, at that time, gfx already enter into "off" state. Howerver, clockgating enabling will use MMIO to access the gfx registers, then get the gfx hung. So here we should move the gfx powergating and gfxoff enabling behavior at the end of initialization behind clockgating. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Cc: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-06-13drm/amdgpu: fix clear_all and replace handling in the VM (v2)Junwei Zhang1-2/+4
v2: assign bo_va as well We need to put the lose ends on the invalid list because it is possible that we need to split up huge pages for them. Cc: stable@vger.kernel.org Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> (v2) Reviewed-by: David Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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