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The PCA95xx GPIO expander requires GPIO controller properties to operate
properly.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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While the DT parser recognizes "ok" as a valid value for the
"status" property, it is actually mentioned nowhere. Use the
proper value "okay" instead, as done in the majority of files
already.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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MikroTik CRS328-4C-20S-4S board has a switch chip with an integrated
Marvell Prestera 98DX3236 CPU.
This commit includes two board variants, namely the factory
default one and a Bit variant. The Bit variant has a
bigger Macronix flash.
This device tree includes basic Linux support.
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Jakov Petrina <jakov.petrina@sartura.hr>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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MikroTik CRS305-1G-4S board has a switch chip with an integrated
Marvell Prestera 98DX3236 CPU.
This commit includes two board variants, namely the factory
default one and a Bit variant. The Bit variant has a
bigger Macronix flash.
This device tree includes basic Linux support.
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Jakov Petrina <jakov.petrina@sartura.hr>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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MikroTik CRS326-24G-2S board has a switch chip with an integrated
Marvell Prestera 98DX3236 CPU.
This commit includes two board variants, namely the factory
default one and a Bit variant. The Bit variant has a
bigger Macronix flash.
This device tree includes basic Linux support.
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Jakov Petrina <jakov.petrina@sartura.hr>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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Add support for onboard MCP2518FD SPI CAN transceiver attached to SPI0
of RB5.
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20201127173044.55144-1-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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This property is used by io-channel consumers, not providers so should
not present here. Note dt_schema will now detect this error as there
is a dependency between this property and io-channels.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Andy Gross <andy.gross@linaro.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20201115192951.1073632-7-jic23@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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There are couple of places where INTA interrupt controller
lacks #interrupt-cells property. This leads to warnings of
the type:
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi:147.51-156.5: Warning (interrupt_provider): /bus@100000/main-navss/interrupt-controller@33d00000: Missing #interrupt-cells in interrupt provider
when building TI device-tree files with W=2 warning level.
Fix these.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Link: https://lore.kernel.org/r/20201127210128.9151-1-nsekhar@ti.com
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git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
arm64: tegra: Device tree changes for v5.11-rc1
These changes are mostly minor fixes across the board, but they also
enable PMUs on Tegra186 and enable SATA support on Jetson TX2.
* tag 'tegra-for-5.11-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: Fix Tegra194 HDA {clock,reset}-names ordering
arm64: tegra: Enable AHCI on Jetson TX2
arm64: tegra: Change order of SATA resets for Tegra132 and Tegra210
arm64: tegra: Add XUSB pad controller interrupt
arm64: tegra: Rename ADMA device nodes for Tegra210
arm64: tegra: Hook up edp interrupt on Tegra132 SOCTHERM
arm64: tegra: Add missing hot temperatures to Tegra210 thermal-zones
arm64: tegra: Add missing gpu-throt-level to Tegra210 soctherm
arm64: tegra: Add missing hot temperatures to Tegra132 thermal-zones
arm64: tegra: Fix DT binding for IO High Voltage entry
arm64: tegra: Fix GIC400 missing GICH/GICV register regions
arm64: tegra: Add missing CPU PMUs on Tegra186
arm64: tegra: Fix Tegra234 VDK node names
arm64: tegra: Wrong AON HSP reg property size
arm64: tegra: Fix USB_VBUS_EN0 regulator on Jetson TX1
arm64: tegra: Correct the UART for Jetson Xavier NX
arm64: tegra: Disable the ACONNECT for Jetson TX2
Link: https://lore.kernel.org/r/20201127144329.124891-5-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
ARM: tegra: Device tree changes for v5.11-rc1
This adds support for the Tegra30-based Ouya game console and enhances a
number of existing device trees. It also fixes a couple of minor issues
that were found during DT validation.
* tag 'tegra-for-5.11-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (23 commits)
ARM: tegra: Add EMC OPP and ICC properties to Tegra124 EMC and ACTMON device-tree nodes
ARM: tegra: Add EMC OPP and ICC properties to Tegra30 EMC and ACTMON device-tree nodes
ARM: tegra: Add EMC OPP properties to Tegra20 device-trees
ARM: tegra: Add nvidia,memory-controller phandle to Tegra20 EMC device-tree
ARM: tegra: Add interconnect properties to Tegra124 device-tree
ARM: tegra: Add interconnect properties to Tegra30 device-tree
ARM: tegra: Add interconnect properties to Tegra20 device-tree
ARM: tegra: acer-a500: Add Embedded Controller
ARM: tegra: Change order of SATA resets for Tegra124
ARM: tegra: Correct EMC registers size in Tegra20 device-tree
ARM: tegra: Properly align clocks for SOCTHERM
ARM: tegra: Hook up edp interrupt on Tegra124 SOCTHERM
ARM: tegra: Add missing hot temperatures to Tegra124 thermal-zones
ARM: tegra: Add missing gpu-throt-level to Tegra124 soctherm
ARM: tegra: Populate OPP table for Tegra20 Ventana
ARM: tegra: nexus7: Use panel-lvds as the only panel compatible
ARM: tegra: nexus7: Rename gpio-hog nodes
ARM: tegra: nexus7: Add power-supply to lvds-encoder node
ARM: tegra: nexus7: Improve CPU passive-cooling threshold
ARM: tegra: nexus7: Correct thermal zone names
...
Link: https://lore.kernel.org/r/20201127144329.124891-4-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt
dt-bindings: Changes for v5.11-rc1
This contains a couple of conversions of bindings to json-schema, as
well as symbolic names for the various memory clients on Tegra20,
Tegra30 and Tegra124. There's also a couple of fixes for Tegra194
pinmux and ARM GIC bindings. Finally, a new vendor prefix is added
for Ouya and the Ouya game console compatible string is defined.
* tag 'tegra-for-5.11-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt-bindings: bus: Convert ACONNECT doc to json-schema
dt-bindings: interrupt-controller: arm,gic: Update Tegra compatibles
dt-bindings: dma: Convert ADMA doc to json-schema
dt-bindings: Fix entry name for I/O High Voltage property
dt-bindings: ARM: tegra: Add Ouya game console
dt-bindings: Add vendor prefix for Ouya Inc.
dt-bindings: memory: tegra124: Add memory client IDs
dt-bindings: memory: tegra30: Add memory client IDs
dt-bindings: memory: tegra20: Add memory client IDs
Link: https://lore.kernel.org/r/20201127144329.124891-1-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt
Renesas ARM DT updates for v5.11 (take two)
- PCIe endpoint support for the R-Car H3 ES2.0+ SoC.
* tag 'renesas-arm-dt-for-v5.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: r8a77951: Add PCIe EP nodes
Link: https://lore.kernel.org/r/20201127132155.77418-2-geert@linux-m68k.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt
STM32 DT updates for v5.11, round 1
Highlights:
----------
MCU part:
-Fix dmamux reg property (length) on stm32h743.
-Explicitly set DCMI bus type on stm32429i eval board.
MPU part:
-Enable FIFO mode with half-full threshold for DCMI.
-Harmonize EHCI/OHCI nodes.
-Move SDMMC IP version to v2.0 to get features improvements.
-Add LP-timer wakeup support.
-Enable crypto/hash/crc support.
-Explicitly set DCMI bus type on stm32mp157 eval board.
-Add USB type-c controller (STUSB1600) on stm32mp15 DK boards
(It is connected to I2C4).
-Fix dmamux reg property (length) on stm32mp151.
-Optimize USB OTG FIFO sizes on stm32mp151.
-Declare tamp node also as "simple-mfd".
-LXA:
-Document Octavo vendor-prefixes yaml file.
-Document lxa,stm32mp157c-mc1 in STM32 yaml file.
-DH:
-Connect PHY IRQ line on DH SoM.
-Add KS8851 Ethernet support on DHCOM which is mapped to FMC2.
-Document all DH compatible strings in STM32 yaml file.
-Add DHCOM based PicoITX board. This board embedds ethernet port,
USB, CAN LEDS and a custom board-to-board connector.
* tag 'stm32-dt-for-v5.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (34 commits)
ARM: dts: stm32: lxa-mc1: add OSD32MP15x to list of compatibles
dt-bindings: arm: stm32: add extra SiP compatible for lxa,stm32mp157c-mc1
dt-bindings: vendor-prefixes: document Octavo Systems oct prefix
ARM: dts: stm32: Add DHCOM based PicoITX board
dt-bindings: arm: stm32: Add compatible strings for DH SoMs and boards
ARM: dts: stm32: support child mfd cells for the stm32mp1 TAMP syscon
dt-bindings: arm: stm32: add simple-mfd compatible for tamp node
ARM: dts: stm32: update stm32mp151 for remote proc synchronization support
ARM: dts: stm32: adjust USB OTG gadget fifo sizes in stm32mp151
ARM: dts: stm32: fix dmamux reg property on stm32h743
ARM: dts: stm32: fix dmamux reg property on stm32mp151
ARM: dts: stm32: fix mdma1 clients channel priority level on stm32mp151
ARM: dts: stm32: add STUSB1600 Type-C using I2C4 on stm32mp15xx-dkx
dt-bindings: usb: Add DT bindings for STUSB160x Type-C controller
dt-bindings: connector: add typec-power-opmode property to usb-connector
ARM: dts: stm32: reorder spi4 within stm32mp15-pinctrl
ARM: dts: stm32: set bus-type in DCMI endpoint for stm32429i-eval board
ARM: dts: stm32: set bus-type in DCMI endpoint for stm32mp157c-ev1 board
ARM: dts: stm32: enable CRYP by default on stm32mp15
ARM: dts: stm32: enable CRC1 by default on stm32mp15
...
Link: https://lore.kernel.org/r/873c17a5-28d5-9261-f691-1b917611c932@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt
Devicetree changes for omaps for v5.11 merge window
- Two non-urgent pandaboard updates to get gpio button and bluetooth
working on pandaboard-es
- Updates to follow devicetree binding docs for dwc3 and pwm-leds
- Add initial support for droid bionic based on what we have for droid4
- Add second sha instance for dra7
- Add eQEP nodes for am335x for boneblue
- Fix wrong comments for am335x gpio_31
* tag 'omap-for-v5.11/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: am335x: Fix comments for AM335X_PIN_GPMC_WPN pin in GPIO mode
ARM: dts: am335x-boneblue: Enable eQEP
ARM: dts: am33xx: Add nodes for eQEP
ARM: dts: dra7: add second SHA instance
ARM: dts: xt875: add section for kionix kxtf9
ARM: dts: mapphone: separate out xt894 specific things
ARM: dts: omap: Fix schema warnings for pwm-leds
ARM: dts: omap5: Harmonize DWC USB3 DT nodes name
ARM: dts: am437x: Correct DWC USB3 compatible string
ARM: dts: pandaboard es: add bluetooth uart for HCI
ARM: dts: pandaboard: fix pinmux for gpio user button of Pandaboard ES
Link: https://lore.kernel.org/r/pull-1606462656-588116@atomide.com-2
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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MDI_TP_P0 (gpio51) is used by pwm1 and uart2 (uart1 on gpio-header)
MDI_RP_P4 (gpio67) is used by pwm4 and spi1
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Link: https://lore.kernel.org/r/20201016204019.2606-3-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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mt7622 only supports 6 pwm-channels so drop pwm7
third pwm (pwm2) is inverted and connected to fan-socket
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Link: https://lore.kernel.org/r/20201016204019.2606-2-linux@fw-web.de
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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on main_i2c1
J7200 main_i2c1 is connected to the i2c bus on the CPB marked as main_i2c3
The i2c1 devices on the CPB are _not_ connected to the SoC, they are not
usable with the J7200 SOM.
Correct the expander name from exp4 to exp3 and at the same time add the
line names as well.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Link: https://lore.kernel.org/r/20201120073533.24486-3-peter.ujfalusi@ti.com
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The J7200 SOM have additional io expander which is used to control several
SOM level muxes to make sure that the correct signals are routed to the
correct pin on the SOM <-> CPB connectors.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Link: https://lore.kernel.org/r/20201120073533.24486-2-peter.ujfalusi@ti.com
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Add display subsystem device nodes to allow video output.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20201127104930.1981497-4-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Add iommu and larb nodes to the MT8183.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20201127104930.1981497-3-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Add dsi and mipitx nodes to the MT8183.
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20201127104930.1981497-2-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Add pwm to mt8183 and backlight to mt8183-kukui.
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20201124041253.4181273-1-hsinyi@chromium.org
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Add power domains controller node for SoC mt8183
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20201030113622.201188-14-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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The SMI (Smart Multimedia Interface) Common is a bridge between the m4u
(Multimedia Memory Management Unit) and the Multimedia HW. This block is
needed to support different multimedia features, like display, video
decode, and camera. Also is needed to control the power domains of such
HW blocks.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20201030113622.201188-13-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Add power domain controller node for SoC mt8173.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Link: https://lore.kernel.org/r/20201030113622.201188-4-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Add power domains dt-bindings for MT8192.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201030113622.201188-15-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Add power domains dt-bindings for MT8183.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201030113622.201188-11-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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controller
The System Control Processor System (SCPSYS) has several power management
related tasks in the system. Add the bindings to define the power
domains for the SCPSYS power controller.
Co-developed-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201030113622.201188-2-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Add basic chip support for Mediatek MT8192
Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
Link: https://lore.kernel.org/r/20201030092207.26488-2-seiya.wang@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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The pumpkin board is made by Gossamer Engineering and is using
a MediaTek SoC. The board currently comes in two available version:
MT8516 SoC and MT8167 SoC.
The board provides the following IOs: eMMC, NAND, SD card, USB type-A,
Ethernet, Wi-Fi, Bluetooth, Audio (jack out, 2 PDM port, 1 analog in),
serial over USB, HDMI, DSI, CSI, and an expansion header.
The board can be powered by battery and/or via a USB Type-C port and
is using a PMIC MT6392.
The eMMC and NAND are sharing pins and cannot be used together.
This commit is adding the basic boot support for the Pumpkin MT8167
board.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Link: https://lore.kernel.org/r/20201027194816.1227654-3-fparent@baylibre.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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The MT8167 SoC provides the following peripherals: GPIO, UART, USB2,
SPI, eMMC, SDIO, NAND, Flash, ADC, I2C, PWM, TImers, IR, Ethernet,
Audio (I2S, SPDIF, TDM, HDMI), HDMI, DSI, CSI, MDP (Multimedia Data
Path), Video encoding (H.264), Video Decoding (H.264, VP8).
The MT8167 is compatible with MT8516 but provides multimedia IPs to it.
This commit is just adding the basic dtsi file with the support of the
following IOs: GPIO, Clocks.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Link: https://lore.kernel.org/r/20201027194816.1227654-2-fparent@baylibre.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Add binding documentation for the MT8167 Pumpkin board.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201027194816.1227654-1-fparent@baylibre.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Add node to support e-fuses on MT8516
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Link: https://lore.kernel.org/r/20201016171837.3261310-2-fparent@baylibre.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Add PCIe EP nodes for R8A77951 SoC dtsi.
Signed-off-by: Yuya Hamamachi <yuya.hamamachi.sx@renesas.com>
Link: https://lore.kernel.org/r/20201125073303.19057-3-yuya.hamamachi.sx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
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into arm/dt
ARM64: DT: Hisilicon ARM64 DT updates for 5.11
- Cleanups of the hisilicon DTS to align with the dtschema. All of them do not
have any functional effect except passing dtschema checks or dtc W=2 builds.
* tag 'hisi-arm64-dt-for-5.11' of git://github.com/hisilicon/linux-hisi:
arm64: dts: hisilicon: Use generic "ngpios" rather than "snps,nr-gpios"
arm64: dts: hi3660: Harmonize DWC USB3 DT nodes name
arm64: dts: hisilicon: list all clocks required by snps-dw-apb-uart.yaml
arm64: dts: hisilicon: list all clocks required by pl011.yaml
arm64: dts: hisilicon: list all clocks required by spi-pl022.yaml
arm64: dts: hisilicon: normalize the node name of the UART devices
arm64: dts: hisilicon: normalize the node name of the usb devices
arm64: dts: hisilicon: normalize the node name of the SMMU devices
arm64: dts: hisilicon: place clock-names "biu" before "ciu"
arm64: dts: hisilicon: remove unused property pinctrl-names
arm64: dts: hisilicon: write the values of property-units into a uint32 array
arm64: dts: hisilicon: separate each group of data in the property "reg"
arm64: dts: hisilicon: normalize the node name of the ITS devices
Link: https://lore.kernel.org/r/5FBDC416.5060008@hisilicon.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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into arm/dt
ARM: DT: Hisilicon ARM32 DT updates for 5.11
- Cleanups of the hisilicon DTS to align with the dtschema including
serial, usb, amba-bus, memory, mmc, spi and syscon. All of them do not
have any functional effect except passing dtschema checks or dtc W=2
builds.
* tag 'hisi-arm32-dt-for-5.11' of git://github.com/hisilicon/linux-hisi:
ARM: dts: hisilicon: fix errors detected by syscon.yaml
ARM: dts: hisilicon: fix errors detected by spi-pl022.yaml
ARM: dts: hisilicon: fix errors detected by synopsys-dw-mshc.yaml
ARM: dts: hisilicon: fix errors detected by root-node.yaml
ARM: dts: hisilicon: fix errors detected by simple-bus.yaml
ARM: dts: hisilicon: fix errors detected by usb yaml
ARM: dts: hisilicon: fix errors detected by pl011.yaml
ARM: dts: hisilicon: fix errors detected by snps-dw-apb-uart.yaml
Link: https://lore.kernel.org/r/5FBDC347.4050102@hisilicon.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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device-tree nodes
Add EMC OPP DVFS/DFS tables and interconnect paths that will be used for
dynamic memory bandwidth scaling based on memory utilization statistics.
Update board device-trees by removing unsupported EMC OPPs.
Note that ACTMON watches all memory interconnect paths, but we use a
single CPU-READ interconnect path for driving memory bandwidth, for
simplicity.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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device-tree nodes
Add EMC OPP tables and interconnect paths that will be used for
dynamic memory bandwidth scaling based on memory utilization statistics.
Update board device-trees by removing unsupported EMC OPPs.
Note that ACTMON watches all memory interconnect paths, but we use a
single CPU-READ interconnect path for driving memory bandwidth, for
simplicity.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add EMC OPP DVFS tables and update board device-trees by removing
unsupported OPPs.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add nvidia,memory-controller to the Tegra20 External Memory Controller
node. This allows to perform a direct lookup of the Memory Controller
instead of walking up the whole tree. This puts Tegra20 device-tree on
par with Tegra30+.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add interconnect properties to the Memory Controller, External Memory
Controller and the Display Controller nodes in order to describe hardware
interconnection.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add interconnect properties to the Memory Controller, External Memory
Controller and the Display Controller nodes in order to describe hardware
interconnection.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add interconnect properties to the Memory Controller, External Memory
Controller and the Display Controller nodes in order to describe hardware
interconnection.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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This patch adds device-tree node for the Embedded Controller which is
found on the Picasso board. The Embedded Controller itself is ENE KB930,
it provides functions like battery-gauge/LED/GPIO/etc and it uses firmware
that is specifically customized for the Acer A500 device.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Tegra AHCI dt-binding doc is converted from text based to yaml based.
dtbs_check valdiation strictly follows reset-names order specified
in yaml dt-binding.
Tegra124 thru Tegra210 has 3 resets sata, sata-oob and sata-cold.
Tegra186 has 2 resets sata and sata-cold.
This patch changes order of SATA resets to maintain proper resets
order for commonly available resets across Tegra124 thru Tegra186
for dtbs_check to pass.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Fix the size of Tegra20 EMC registers, which should be twice bigger.
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Entries on subsequent lines should be aligned with the entry on the
first line.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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For some reason this was never hooked up. Do it now so that over-current
interrupts can be logged.
Reported-by: Nicolas Chauvet <kwizart@gmail.com>
Suggested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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According to dmesg, thermal-zones for mem and cpu are missing hot
temperatures properties.
throttrip: pll: missing hot temperature
...
throttrip: mem: missing hot temperature
...
Adding them will clear the messages.
Signed-off-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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